JPH04141889A - Semiconductor device - Google Patents

Abstract

PURPOSE:To speed up data transmission through the use of an equalizing system by varying potential in such a way that the output of an equalizing control circuit is set on a low voltage-side and the performance of an equalizing transistor is deteriorated. CONSTITUTION:When the potential of a power source line is less than prescribed potential, a P-channel transistor 13 comes to a nonconducted state and therefore an equalizing operation is not executed. Thus, stability can be prevented from being furthermore deteriorating by the equalizing operation in a low voltage area, namely, an area where the high potential of a stored node in a memory cell is low and stability is deteriorated. Then, speed up being the original target of the equalizing operation can be realized in a high voltage area, namely, an area where the high potential of the stored node in the memory cell is high and stability is sufficient. Namely, a trouble which is the deterioration of stability in the memory cell and the lack of sense amplifier input amplitude, which come into question at the time of low power line potential, is not deteriorated. Thus, the transmission of data can be speeded up.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an equalization transistor that equalizes data on a data line pair.

[Prior Art] Conventionally, a data line equalization method has been proposed for the purpose of speeding up the data output transition of the data line.

FIG. 5 is a diagram showing data line pairs and equalizing transistors in a conventional device, taking as an example the configuration of a bit line section in a static random access memory (SRAM).

In FIG. 5, reference numerals 11 and 12 indicate memory cells. For example, the memory cell 11 selected by the word line WLI outputs complementary data to the data line pair D.■. A data line load circuit 14 is connected between the power supply line and the data line pair D-U, and clamps the data line pair D-17 to a predetermined potential. 13 is an equalizing transistor for equalizing complementary data output to the data line pair DU;
It consists of a P-channel transistor. Here, the gate electrode of the P-channel equalize transistor 13 has a high level during a write operation and a low level during a read operation.
An internal write control signal WE, which is w, is connected.

The operation of the conventional device configured as described above is as follows.

During a write operation, write data is output to the data line pair DU, and the data is written into the memory cell selected by the word line. At this time, the gate electrode of the P-channel transistor 13 is at the H1gh level, and the transistor becomes non-conductive.

During a read operation, the data of the selected memory cell is output to the data line pair DH. At this time, the gate electrode of the P-channel transistor 13 is at a low level, and the transistor becomes conductive.

For example, considering a read operation in which memory cell 11 is selected after memory cell 12 is selected, WL
2 falls and the memory cell 12 becomes unselected, at the same time the P-channel transistor 13 connects the data line pair D-D.
The potentials of are equalized. That is, since the data on the data line pair D-H is equalized in advance before WLI rises, after the memory cell 11 is selected, the data in the memory cell 11 is not output to the data line pair D-H. We were able to realize a faster time.

[Problems to be Solved by the Invention] The conventional semiconductor device as described above has the following problems because it is configured as described above.

In FIG. 5, the gate electrode of the P-channel transistor 13 is always at a low level during the read operation, and the
Channel transistor 13 is always conductive. Normally, the low level of the storage node potential of a memory cell is not 0■, but increases to about 1■ due to the load circuit 14 and the conductive P-channel transistor 13. When the power supply voltage is sufficiently high, for example, 5■ or more, the high level of the storage node potential of the memory cell is sufficiently high, so that the original purpose can be achieved without threatening the data in the memory cell.
When the power supply voltage becomes low, the store node in the memory cell goes high.
Since the potential on the gh data side becomes low, the potential difference between the memory cell store nodes decreases, and there is a risk that the data is likely to be inverted.

Furthermore, since the P-channel transistor 13 is conductive, the signal amplitude of the data line pair DU decreases, but the influence becomes greater on the low power supply voltage side and further decreases, so that the data line pair DU There is a risk that the operation of the input sense amplifier may become unstable.

As described above, the conventional semiconductor device has a problem in that the P-channel transistor 13 is always conductive during reading, which reduces the operating margin on the low power supply voltage side.

The present invention has been made to solve such problems, and an object thereof is to obtain a semiconductor device that achieves high speed by using a data line equalization method without reducing the operating margin on the low power supply voltage side. shall be.

[Means for Solving the Problems] A semiconductor device of the present invention includes at least one pair of data lines to which complementary data is output, and an equalization transistor for equalizing the data on each pair of data lines. A semiconductor device comprising: an equalize control circuit that controls a gate potential of an equalize transistor; and an output of the equalize control circuit has a potential that is varied such that the ability of the equalize transistor is reduced on the low source voltage side. This is a semiconductor device.

[Operation] In the semiconductor device according to the present invention, the gate electrode potential of the equalizing transistor is set so that the equalizing transistor becomes non-conductive or its performance decreases below a predetermined power supply voltage.

[Embodiment] FIG. 1 is a diagram showing a data line pair and an equalizing transistor in the present invention. The configuration of the memory cell 11, 12, data line load circuit 14, and equalizing transistor 13 is such that the gate electrode of the equalizing transistor 13 is The configuration is the same as that of the conventional device shown in FIG. 5, except that it is connected to the output EQ of the equalization control circuit shown in FIG.

FIG. 2 shows an equalization control circuit, which includes resistors R1 and R2 connected in series between the power supply line and the ground line, a P-channel transistor 24 whose gate electrode is connected to the ground line, and the resistor R1 whose gate electrode is connected to the ground line. and an N-channel transistor 23 connected to the midpoint VA of R2.

The output Effi of the equalize control circuit is taken out between the drains of the P-channel transistor 24 and the N-channel transistor 230, and is connected to the gate electrode of the if-rise transistor 13 as described above.

FIG. 3 is a characteristic diagram showing the operating characteristics of the equalization control circuit with respect to the electric R line potential VDD, and the potential of VA is indicated by r with respect to the horizontal axis VDD.

The operation of the equalization control circuit will be explained based on FIG.

The potential of VA is a value obtained by dividing the power line potential VDD by resistors R1 and R2, and becomes VA=R2/(R1+R2)XVDD. When the power supply line potential VDD rises, it rises while satisfying the above relationship, and VA of the N-channel transistor 23 becomes V TH
At V DD 1 or higher, which is equal to N, the N-channel transistor 23 becomes conductive. On the other hand, since the gate electrode of the P-channel transistor 24 is connected to the ground line, it is always in a conductive state, and when the power line potential is below VDDI, the potential at r becomes VDD. Here, if the capability of the N-channel transistor 23 is made sufficiently larger than that of the P-channel transistor 24, when the power supply line potential is equal to or higher than VDDI,
When the channel transistor 23 becomes conductive, VA becomes approximately the potential of the ground line, and its characteristics with respect to the power supply line potential VDD are the third.
It will look like the figure.

The P-channel transistor 13, which has the above power supply voltage characteristics and whose gate electrode is connected to the gate electrode, does not perform an equalizing operation because it becomes non-conductive when the power line potential VDD is below VDDI, and becomes conductive when it is above VDDI. Therefore, an equalization operation is performed. Therefore VDD
In the low voltage region below I, that is, in the region where the high potential of the memory cell store node is low and the stability deteriorates, the equalization operation can prevent the stability from further deteriorating, and the high voltage above VDDI In this region, that is, in a region where the high potential of the store node of the memory cell is high and stability is sufficient, the original purpose of the equalization operation can be increased in speed.

The value of V DD 1 that switches the equalization operation is VDDI = (R1 + R2) x VTllN
/R2, and can be arbitrarily changed by the resistance ratio of the resistors R1 and R2 and the threshold voltage VTIIN of the N-channel transistor 23, so it can be set according to the circuit configuration and required characteristics. In addition, the direct current flowing through the resistors R1 and R2 can be made very small by using, for example, high-resistance polycrystalline silicon, etc., and by inserting a transistor in series with R1 and R2, the gate is connected to an internal chip. If a configuration is adopted in which control is performed using a selection signal or the like, current consumption when the chip is not selected can be suppressed.

FIG. 4 is a diagram showing another embodiment of the equalization control circuit, in which an N-channel transistor 25 is inserted between the VA point of the equalization control circuit shown in FIG. 2 and the ground line, and its gate is internally written. It is connected to the control signal WE. In FIG. 4, when the signal WE is High, that is, in the write state, the N-channel transistor 25 becomes conductive, and the potential of VA is Ov at any power line potential, so 1lffi is fixed at High, that is, in a state where no equalization is performed. Become. On the other hand, when the signal WE is Low, that is, in the read state, the N-channel transistor 25 becomes non-conductive, and the operation changes depending on the power line potential described above. Therefore, the configuration of the equalization control circuit shown in FIG. 4 realizes an equalization operation with the addition of a control function using a write control signal similar to that of the conventional circuit shown in FIG. In the embodiment shown in FIG. 4, the internal write control signal WE is connected, but it is obvious that it is also effective to connect, for example, the address signal transition detection signal (ATD).

[Effects of the Invention] As explained above, according to the present configuration of the present invention, the equalization operation of data lines, etc. can be performed selectively depending on the power line potential, particularly at a predetermined potential or higher, so that problems can be solved when the power line potential is low. The original purpose of equalization, which is to realize high-speed data propagation, can be achieved without aggravating problems such as decreased stability of memory cells and insufficient sense amplifier input amplitude.

[Brief explanation of the drawing]

FIG. 1 is a configuration circuit diagram of a semiconductor device showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of an equalization control circuit of the present invention, and FIG. 3 is an operating characteristic of the equalization control circuit in FIG. 2. FIG. 4 is a circuit diagram showing another embodiment of the equalization control circuit according to the present invention. FIG. 5 is a circuit diagram showing the configuration of a conventional semiconductor device. Note that the same reference numerals in the figures indicate the same or equivalent parts. 11, 12 ・ 21, 22 ・ Memory cell equalize transistor data line load circuit resistance N-channel transistor P-channel transistor N-channel transistor or higher

Claims (1)

[Scope of Claims] A semiconductor device having at least one pair of data lines for outputting complementary data, and an equalization transistor for equalizing the data on each data line pair, wherein the gate potential of the equalization transistor is What is claimed is: 1. A semiconductor device comprising: an equalization control circuit for controlling an output voltage of the equalization transistor;