JPH04137434A - Manufacture of field emission type cathode and vacuum transistor - Google Patents
Manufacture of field emission type cathode and vacuum transistorInfo
- Publication number
- JPH04137434A JPH04137434A JP2257260A JP25726090A JPH04137434A JP H04137434 A JPH04137434 A JP H04137434A JP 2257260 A JP2257260 A JP 2257260A JP 25726090 A JP25726090 A JP 25726090A JP H04137434 A JPH04137434 A JP H04137434A
- Authority
- JP
- Japan
- Prior art keywords
- field emission
- substrate crystal
- emission type
- cathode
- type cathode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 claims description 14
- 239000002994 raw material Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 abstract description 2
- 125000002524 organometallic group Chemical group 0.000 abstract description 2
- 239000012528 membrane Substances 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 11
- 239000007789 gas Substances 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009388 chemical precipitation Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 150000002902 organometallic compounds Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Cold Cathode And The Manufacture (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、超高速のマイクロ真空管、あるいは超小型の
ブラウン管、平面デイスプレィ等に用いられる電界放射
型陰極の製造方法およびその陰極を用いた真空トランジ
スタの製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a field emission cathode used in ultra-high-speed micro vacuum tubes, ultra-small cathode ray tubes, flat displays, etc., and a method for producing a vacuum using the cathode. The present invention relates to a method for manufacturing a transistor.
[従来の技術1
ミクロンサイズの微小陰極を利用して、微細で集積可能
な真空トランジスタや、フラットパネルデイスプレィを
作る試みは、半導体の微細加工技術を用いておこなわれ
ている。伊藤、「応用物理」59巻第2号(1990)
p、164〜169に、この分野の動向が述べられて
いる。従来の真空トランジスタを作製する試みでは、電
界放射冷陰極の作製にピンホールマスクを用いた真空蒸
着法、あるいはSiの異方性エツチングによる方法が用
いられてきた。[Prior Art 1] Attempts have been made to use micron-sized cathodes to create minute vacuum transistors and flat panel displays that can be integrated using semiconductor microfabrication techniques. Ito, Applied Physics, Vol. 59, No. 2 (1990)
Trends in this field are described in pages 164-169. In conventional attempts to fabricate vacuum transistors, a vacuum evaporation method using a pinhole mask or an anisotropic etching method of Si has been used to fabricate a field emission cold cathode.
[発明が解決しようとする課題1
電子の放出効率は電界が集中する冷陰極の曲率半径に大
きく依存する。しかし、従来の方法で作製できる冷陰極
の曲率半径は0.05μm程度であって電子の放出効率
は十分でない。さらに従来法では陰極先端の形状の制御
が難しく、そのため均一な特性が得られないという問題
があった。[Problem to be Solved by the Invention 1 Electron emission efficiency largely depends on the radius of curvature of the cold cathode where the electric field is concentrated. However, the radius of curvature of a cold cathode that can be produced by the conventional method is about 0.05 μm, and the electron emission efficiency is not sufficient. Furthermore, in the conventional method, it is difficult to control the shape of the cathode tip, and as a result, there is a problem in that uniform characteristics cannot be obtained.
本発明はこのような従来の問題を解決し、電子の放出効
率が高く、しかも均一な形状で、従って均一な特性の電
界放射型陰極の製造方法を提供することを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve these conventional problems and provide a method for manufacturing a field emission cathode that has high electron emission efficiency, a uniform shape, and therefore uniform characteristics.
さらに、本発明は上述した陰極を用い、電子の走行時間
が短く、相互コンダクタンスの大きな真空トランジスタ
の製造方法を提供することを目的とする。A further object of the present invention is to provide a method for manufacturing a vacuum transistor that uses the above-mentioned cathode, has a short electron transit time, and has a large mutual conductance.
[課題を解決するための手段]
かかる目的を達成するために、本発明による電界放射型
陰極の製造方法は所定の指数面をもつ基板結晶表面上に
絶縁体薄膜を形成する工程と、形成すべき電界放射型陰
極に応じた形状に前記絶縁膜を部分的に除去する工程と
、前記基板結晶表面に原料原子または原料化合物を導き
、前記原料に応じた半導体を前記基板結晶上に析出させ
て電界放射型陰極を形成する工程とを有することを特徴
とする。[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a field emission cathode according to the present invention includes a step of forming an insulating thin film on a substrate crystal surface having a predetermined index plane, and a step of forming an insulating thin film on a substrate crystal surface having a predetermined index plane. a step of partially removing the insulating film into a shape corresponding to the desired field emission type cathode, and introducing raw material atoms or raw material compounds onto the surface of the substrate crystal to precipitate a semiconductor corresponding to the raw material on the substrate crystal. The method is characterized by comprising a step of forming a field emission type cathode.
本発明による真空トランジスタの製造方法は所定の指数
面をもつ基板結晶表面上に絶縁体薄膜を形成する工程と
、形成すべき立体構造に応じた形状に前記絶縁膜を部分
的に除去する工程と、前記基板結晶表面に原料原子また
は原料化合物を導き、前記原料に応じた半導体を前記基
板結晶上に析出させて立体構造の電界放射型陰極を形成
する工程と、さらに絶縁層の上に金属層を形成してゲー
トおよびコレンクターを形成する工程とを有することを
特徴とする。The method for manufacturing a vacuum transistor according to the present invention includes a step of forming an insulating thin film on a substrate crystal surface having a predetermined index plane, and a step of partially removing the insulating film into a shape corresponding to a three-dimensional structure to be formed. , a step of introducing a raw material atom or a raw material compound onto the surface of the substrate crystal and depositing a semiconductor corresponding to the raw material on the substrate crystal to form a field emission type cathode having a three-dimensional structure; and further comprising a metal layer on an insulating layer. forming a gate and a collector.
[作 用1
本発明の電界放射冷陰極は、所定の基板結晶表面上に有
機金属化合物原料ガスを導き、有機金属化合物ガスに応
じた半導体を前記基板結晶表面上に析出する有機金属気
相成長法(MOCVD法)を用い、有機金属化合物ガス
に応じて、加工基板上に形成される半導体を立体形状に
付着させることにより形成するものである。この方法を
用いれば、冷陰極の先端の曲率半径はlO止以下になり
、しかも均一な形状が再現性良くできる。[Function 1] The field emission cold cathode of the present invention is capable of conducting organometallic vapor phase epitaxy in which an organometallic compound raw material gas is introduced onto a predetermined substrate crystal surface, and a semiconductor corresponding to the organometallic compound gas is deposited on the substrate crystal surface. It is formed by attaching a semiconductor to be formed on a processed substrate in a three-dimensional shape using a method (MOCVD method) according to an organic metal compound gas. If this method is used, the radius of curvature of the tip of the cold cathode will be less than 10 0, and a uniform shape can be achieved with good reproducibility.
本発明による真空トランジスタの製造方法はこのような
冷陰極を用いているので、相互コンダクタンスが大きく
、しかも特性の安定した真空トランスタを作製すること
ができる。Since the method for manufacturing a vacuum transistor according to the present invention uses such a cold cathode, a vacuum transistor with high mutual conductance and stable characteristics can be manufactured.
[実施例1 以下、実施例によって本発明の詳細な説明する。[Example 1 Hereinafter, the present invention will be explained in detail with reference to Examples.
第1図は、本発明の一実施例を示す模式図である。基板
1上にエミッタ(陰極)2を有し、さらに絶縁膜3上に
コレクタ(陽極)4およびゲート(グリッド)5を有す
る。この構造はエミッタ(陰極)部分を除けば公知の構
造である。FIG. 1 is a schematic diagram showing an embodiment of the present invention. It has an emitter (cathode) 2 on a substrate 1, and further has a collector (anode) 4 and a gate (grid) 5 on an insulating film 3. This structure is a known structure except for the emitter (cathode) portion.
まず始めにGaAs(111)Bを基板結晶として用い
、その上に有機金属気相成長法によりGaAsの冷陰極
を作製する手順を順を追って説明する。First, the procedure for manufacturing a GaAs cold cathode using GaAs(111)B as a substrate crystal by metal organic vapor phase epitaxy will be explained step by step.
(111)8面上にできるファセット面の面方位を第2
図に示す。(111) The plane orientation of the facet plane formed on the 8th plane is
As shown in the figure.
最初に基板作製条件を示す。GaAs(111)B基板
面上にスパッタ法、または気相化学沈殿法により酸化シ
リコン、窒化シリコン等の絶縁膜を10〜1100n堆
積した後、公知のフォトリングラフィまたは電子ビーム
リソグラフィとエツチング技術を用いて、第2図に示す
四面体の底辺部に相当する三角形状に絶縁薄膜を除去す
る。この絶縁膜が除去された部分のみに結晶を成長する
が、そのとき側面として第2図に示すようなファセット
面を出しながら成長する条件を使う。First, the substrate fabrication conditions will be shown. After depositing 10 to 1100 nm of an insulating film of silicon oxide, silicon nitride, etc. on the GaAs(111)B substrate surface by sputtering or vapor phase chemical precipitation, known photolithography or electron beam lithography and etching techniques are used. Then, the insulating thin film is removed in a triangular shape corresponding to the bottom of the tetrahedron shown in FIG. A crystal is grown only on the portion where the insulating film has been removed, using conditions that allow the crystal to grow while exposing the facet side as shown in FIG. 2.
次に結晶成長条件の詳細を示す。高周波加熱の横型路を
用い、0.1気圧の減圧下で成長を行った。原料として
トリメチルガリウムおよびアルシンを用いた。反応管内
の分圧は、それぞれ2.6×10−’atmおよび4.
7x 10−’atmであり、水素キャリアガスも含め
全ガス流量は4リツタ一/分である。GaAs層を絶縁
膜が除去された三角形状のGaAs(111)8面上に
のみ成長させる。成長温度は800℃とした。(111
)8面上ではGaAsは750℃以上で鏡面の層状成長
が得られ、側面に(110)面が現れ、また絶縁膜上に
は成長が起こらない。このようにして成長させたGaA
sの四面体の頂点を陰極として用いる。本発明によるエ
ミッタ先端の曲率半径は10nII+以下である。Next, details of crystal growth conditions will be shown. Growth was performed under a reduced pressure of 0.1 atm using a horizontal high-frequency heating path. Trimethylgallium and arsine were used as raw materials. The partial pressures inside the reaction tube were 2.6 x 10-' atm and 4.
7 x 10-'atm, and the total gas flow rate, including the hydrogen carrier gas, was 4 liters/min. A GaAs layer is grown only on the triangular GaAs (111) 8 plane from which the insulating film has been removed. The growth temperature was 800°C. (111
) On GaAs, mirror-like layered growth is obtained at temperatures above 750° C., a (110) plane appears on the side surfaces, and no growth occurs on the insulating film. GaA grown in this way
The apex of the s tetrahedron is used as a cathode. The radius of curvature of the emitter tip according to the invention is less than 10 nII+.
次に真空トランジスタの作製例を示す。第1図に示した
例では、前述した結晶成長法でn型エミッタ(陰極)2
を形成後、絶縁膜3 (SiO□)を堆積した。絶縁層
の厚さは、エミッタの高さより僅かに薄い程度とした。Next, an example of manufacturing a vacuum transistor will be shown. In the example shown in Figure 1, the n-type emitter (cathode) 2 is
After forming, an insulating film 3 (SiO□) was deposited. The thickness of the insulating layer was set to be slightly thinner than the height of the emitter.
ついで、エミッタ部分だけ絶縁膜を除去した。次にエミ
ッタの周りに順次金またはアルミニウムからなるゲート
(グリッド)5およびコレクタ電極(陽極)4を蒸着ま
たはスパッタによって形成した。Then, the insulating film was removed only from the emitter portion. Next, a gate (grid) 5 and a collector electrode (anode) 4 made of gold or aluminum were sequentially formed around the emitter by vapor deposition or sputtering.
コレクタにプラス、エミッタにマイナスの電圧をかける
とエミッタの先端では電界が集中するため電子の放出が
おこる。先端の曲率半径が小さいほど高電界となり電子
が出易くなる。電子はエミッタからコレクタに流れるが
ゲートにマイナスの電圧をかけると電子は流れにく(な
り電流が下がる。このような原理にもとづいてトランジ
スタ動作をする。When a positive voltage is applied to the collector and a negative voltage is applied to the emitter, the electric field concentrates at the tip of the emitter, causing electron emission. The smaller the radius of curvature of the tip, the higher the electric field and the easier it is for electrons to come out. Electrons flow from the emitter to the collector, but when a negative voltage is applied to the gate, the electrons do not flow (and the current decreases).A transistor operates based on this principle.
作製したGaAs真空トランジスタの特性は、エミッタ
の高さ0.1μm、エミッタ先端とゲートとの距離1μ
m、エミッタ先端とコレクタの距離2μmの時、相互コ
ンダクタンスioms、電子の走行時間0.1psであ
った。これは従来の真空トランジスタの特性より3桁以
上改善されている。理由は本発明による作製方法を用い
ることにより、エミッタ先端部が鋭利になり、その結果
、低電圧でも大量の電子が放出されることによる。The characteristics of the fabricated GaAs vacuum transistor are that the emitter height is 0.1 μm and the distance between the emitter tip and the gate is 1 μm.
m, the distance between the emitter tip and the collector was 2 μm, the mutual conductance was ioms, and the electron transit time was 0.1 ps. This is an improvement of more than three orders of magnitude over the characteristics of conventional vacuum transistors. The reason is that by using the manufacturing method according to the present invention, the emitter tip becomes sharp, and as a result, a large amount of electrons are emitted even at a low voltage.
基板としてGaAs(ill)Aを用いる場合は、Ga
Asのファセット成長を650℃でおこなうことによっ
て、上述した実施例と同様に先端の鋭い電界放射型陰極
を作ることができる。When using GaAs(ill)A as the substrate, GaAs(ill)A is used as the substrate.
By performing facet growth of As at 650° C., a field emission type cathode with a sharp tip can be produced as in the above embodiment.
GaAs以外の作製例として、5i(111)基板上に
絶縁膜を付け、フォトリソグラフィとエツチングにより
三角形状に絶縁膜を除去し、その上に気相化学沈殿法(
CVD法)によりSiの四面体構造を作製し電界放射型
陰極とした。この陰極の先端の曲率半径も10nm以下
であった。この陰極をエミッタとし、上述した実施例と
同様にして真空トランジスタを作製した。得られた特性
はGaAs真空トランジスタと同程度であった。As an example of manufacturing materials other than GaAs, an insulating film is attached on a 5i (111) substrate, the insulating film is removed in a triangular shape by photolithography and etching, and then vapor phase chemical precipitation method (
A Si tetrahedral structure was fabricated using a CVD method (CVD method) to form a field emission type cathode. The radius of curvature of the tip of this cathode was also 10 nm or less. Using this cathode as an emitter, a vacuum transistor was fabricated in the same manner as in the example described above. The obtained characteristics were comparable to those of a GaAs vacuum transistor.
[発明の効果1
以上説明したように、本発明によれば、先端の曲率半径
が小さ(、しかも形状がよく制御された電界放射型陰極
を作製することができ、この陰極を使用した真空トラン
ジスタの相互インダクタンスは高く、電子走行時間は短
い。[Advantageous Effects of the Invention 1] As explained above, according to the present invention, a field emission type cathode having a small radius of curvature at the tip (and a well-controlled shape) can be manufactured, and a vacuum transistor using this cathode can be manufactured. The mutual inductance of is high and the electron transit time is short.
本発明による電界放射型冷陰極は、ブラウン管の陰極、
平面デイスプレィ等に適用することができる。The field emission type cold cathode according to the present invention is a cathode of a cathode ray tube,
It can be applied to flat displays, etc.
第1図は本発明の一実施例を示す模式的断面図、 第2図は四面体構造の模型を示す斜視図である。 1・・・基板、 2・・・エミッタ、 3・・・絶縁膜、 4・・・コレクタ、 5・・・ゲート。 FIG. 1 is a schematic cross-sectional view showing one embodiment of the present invention; FIG. 2 is a perspective view showing a model of a tetrahedral structure. 1... board, 2...emitter, 3... Insulating film, 4...Collector, 5...Gate.
Claims (1)
形成する工程と、 形成すべき電界放射型陰極に応じた形状に前記絶縁膜を
部分的に除去する工程と、 前記基板結晶表面に原料原子または原料化合物を導き、
前記原料に応じた半導体を前記基板結晶上に析出させて
電界放射型陰極を形成する工程と を有することを特徴とする電界放射型陰極の製造方法。 2)所定の指数面をもつ基板結晶表面上に絶縁体薄膜を
形成する工程と、 形成すべき立体構造に応じた形状に前記絶縁膜を部分的
に除去する工程と、 前記基板結晶表面に原料原子または原料化合物を導き、
前記原料に応じた半導体を前記基板結晶上に析出させて
立体構造の電界放射型陰極を形成する工程と、 さらに絶縁層の上に金属層を形成してゲートおよびコレ
ンクターを形成する工程と を有することを特徴とする真空トランジスタの製造方法
。[Claims] 1) A step of forming an insulating thin film on a substrate crystal surface having a predetermined index plane, and a step of partially removing the insulating film into a shape corresponding to a field emission cathode to be formed. and introducing raw material atoms or raw material compounds onto the substrate crystal surface,
A method for manufacturing a field emission cathode, comprising the step of depositing a semiconductor corresponding to the raw material on the substrate crystal to form a field emission cathode. 2) A step of forming an insulating thin film on a substrate crystal surface having a predetermined index plane, a step of partially removing the insulating film in a shape corresponding to a three-dimensional structure to be formed, and a step of forming a raw material on the substrate crystal surface. guide atoms or raw material compounds,
A step of depositing a semiconductor according to the raw material on the substrate crystal to form a three-dimensional field emission type cathode, and a step of further forming a metal layer on the insulating layer to form a gate and a collector. A method for manufacturing a vacuum transistor characterized by the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2257260A JPH04137434A (en) | 1990-09-28 | 1990-09-28 | Manufacture of field emission type cathode and vacuum transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2257260A JPH04137434A (en) | 1990-09-28 | 1990-09-28 | Manufacture of field emission type cathode and vacuum transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04137434A true JPH04137434A (en) | 1992-05-12 |
Family
ID=17303916
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2257260A Pending JPH04137434A (en) | 1990-09-28 | 1990-09-28 | Manufacture of field emission type cathode and vacuum transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04137434A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9431205B1 (en) | 2015-04-13 | 2016-08-30 | International Business Machines Corporation | Fold over emitter and collector field emission transistor |
-
1990
- 1990-09-28 JP JP2257260A patent/JPH04137434A/en active Pending
Cited By (4)
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US9431205B1 (en) | 2015-04-13 | 2016-08-30 | International Business Machines Corporation | Fold over emitter and collector field emission transistor |
US9941088B2 (en) | 2015-04-13 | 2018-04-10 | International Business Machines Corporation | Fold over emitter and collector field emission transistor |
US10424456B2 (en) | 2015-04-13 | 2019-09-24 | International Business Machines Corporation | Fold over emitter and collector field emission transistor |
US10593506B2 (en) | 2015-04-13 | 2020-03-17 | International Business Machines Corporation | Fold over emitter and collector field emission transistor |
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