JPH04137188A - Generating circuit for address in polygon - Google Patents

Abstract

PURPOSE:To generate picture element addresses in the polygon by generating integral coordinates since there are maximum and minimum coordinates present among integral coordinates of intersections of a scanning line and its approximate integral coordinate group without fail when the scanning crosses the polygon. CONSTITUTION:A maximum and minimum discrimination circuit 16 finds the minimum value MIN and maximum value MAX among six horizontal coordinates from linear approximate coordinate generating circuits 13 - 15 and supplies those minimum value MIN and maximum value MAX to an interpolating circuit 17. When all the supplied horizontal coordinates become codes NULL showing no intersection, the maximum and minimum discrimination circuit 16 supplies the codes NULL to the interpolating circuit 17. The interpolating circuit 17 generates a series of horizontal coordinates (X coordinate) between the minimum value MIN and maximum value MAX. The series of horizontal coordinates can be regarded as horizontal addresses XA and Y coordinates of a horizontal line outputted by a horizontal scanning circuit 9 can be regarded as vertical addresses YA.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to two-dimensional image processing technology, and more specifically, for example, in a graphics display device, the present invention relates to a two-dimensional image processing technology, and more specifically, for example, in a graphics display device, three or more points given on the coordinate system of the display device are The present invention relates to an address generation circuit inside a polygon that is extremely effective when applied to display the inside of a polygon whose vertices are filled with a predetermined color using parallel processing.

[Summary of the Invention] The present invention provides, for example, in a graphics display device, a predetermined process that uses parallel processing to process the inside of a polygon whose vertices are three or more points given on the coordinate system of the display device. Regarding the address generation circuit inside a polygon, which is extremely effective when applied to a display that is filled with color, there is a holding circuit that holds the coordinates of each vertex of the polygon, and a holding circuit that is approximated to each side connecting each of these vertices. An approximation circuit that generates a group of approximate integer coordinates, a minimum-maximum circuit that calculates the minimum and maximum coordinates of the integer coordinates of a predetermined scanning line and the intersection of the group of approximate integer coordinates, and the distance between the minimum and maximum coordinates. and an interpolation circuit that generates integer coordinates of the polygon, and when the entire surface of the polygon is scanned with the scanning line, the integer coordinates sequentially output from the interpolation circuit are regarded as the addresses of the pixels inside the polygon. This makes it possible to generate addresses for pixels inside a polygon with a common circuit configuration and simple processing regardless of the shape and placement of the polygon.

[Prior Art] In a graphics display device, integer coordinates are set in the horizontal and vertical directions on the display screen of the display device, and one pixel can be specified with each pair of integer coordinates. There is.

In general, a frame buffer (F
B) A memory is provided, and by periodically reading image data from this frame buffer memory and supplying it to the display device, an image corresponding to the image data is displayed, and the contents of this frame buffer memory are rewritten. This allows the displayed image to be changed. Also, the position of the image data for each pixel within the frame buffer memory is specified by a multi-bit address.
Each of these addresses corresponds to a pair of integer coordinates on the display screen of the display device.

On the display screen of such a graphics display device, for example, in order to fill the inside of a triangle whose vertices are three points specified by given integer coordinates with a predetermined color, the frame buffer of the pixels to be filled with this predetermined color is It is necessary to write the image data of that color to the address in memory.

Conventionally, when determining the integer coordinates of a pixel to be filled with a predetermined color on the display device, and hence its address in the frame buffer memory, computer software is used to calculate, for example, a horizontal scanning line to the two-dimensional integer coordinates of the display device. While moving from top to bottom, focus on the two sides of the triangle and calculate those two sides on the scan line.
Find the horizontal coordinates of two sides. In this case, since the intersection between the scanning line and each side may be a plurality of pixels, it is necessary to decide in advance which pixel on the left side and the right side will be considered as the pixel at the intersection. become. and,
The integer coordinates of the pixel between the two pixels regarded as the pixels at the intersection are the integer coordinates to be determined when the scanning line exists at that position.

If you move the horizontal scan line to a certain extent, either the left side or the right side will reach the apex, so by excluding the side that reached this apex and adding the remaining side, you can change the scan of the horizontal scan line to that point. Continue to the lowest endpoint of the triangle.

[Problems to be Solved by the Invention] However, when performing such processing, the processing method must be changed little by little depending on the shape and placement of the triangle, which complicates the processing and increases the processing circuitry. has the disadvantage that it cannot be used commonly. specifically,
For example, there are the following cases (a) to (e) depending on the shape and placement of the triangle.

(a) The vertices of the left side and the right side are above, the other vertex of the right side is located above the other vertex of the left side, and a third side is added to the right side.

(b) There is a vertex at the top, and a third edge is added to the left.

(1) The top is the base of the triangle.

(1) All triangles are reduced to one point.

(e) The three vertices of a triangle lie on the same straight line.

In order to deal with these cases-based processing, it is necessary to control the processing procedure more than in the conventional →microcode, which has the disadvantage of making the processing more complicated and slowing down the processing speed.

Regarding this, Japanese Patent Application Laid-Open No. 62-221781 states:
A method of filling the entire surface of a rectangle with one side parallel to the horizontal direction on the display screen has been disclosed, but this method has the disadvantage that it can only be applied in the special case where one side is parallel to the horizontal direction and the shape is a rectangle. .

In view of this, it is an object of the present invention to make it possible to generate addresses for pixels inside a polygon by common and simple processing, regardless of the shape and placement of the polygon.

[Means for Solving the Problems] The address generation circuit inside a polygon according to the present invention includes a holding circuit (5, 6, 6, 7), an approximation circuit (13, 14, 15) that generates a group of approximate integer coordinates approximated to each side connecting each of these vertices, and a predetermined scanning line (25).
) and its approximate integer coordinate group (a2.
a minimum-maximum circuit (16) that calculates the minimum coordinate a2 and maximum coordinate C5 of (al, cl-c5), and an interpolation circuit (17) that generates integer coordinates between the minimum and maximum coordinates.
When the entire surface of the polygon is scanned with the scanning line, the integer coordinates sequentially output from the interpolation circuit (17) are regarded as the addresses of the pixels inside the polygon. be.

[Operation] According to the present invention, no matter what kind of polygon the target polygon is, if the scanning line (25) is used to scan the approximate integer coordinate group of each side of the polygon, the scanning line (25)
The number of intersections between and its approximate integer coordinate group is 0 when the scan line is located outside the polygon, and is 1 or more when the scan line crosses inside the polygon. Therefore, when the scanning line crosses the polygon, the minimum and maximum coordinates of the integer coordinates of the intersection of the scanning line (25) and its approximate integer coordinate group (even if these coincide with the minimum coordinates) ) exists, so
By generating integer coordinates between the minimum and maximum coordinates, addresses of pixels inside the polygon can be generated.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this example, the present invention is applied to a graphics display device having a circuit for generating addresses of pixels inside a triangle.

FIG. 1 shows the graphics display device of this example. In FIG. 1, (1) is a central processing unit (hereinafter referred to as rCP UJ) that controls the overall operation,
) is the system bus, and (3) is a memo that stores various image data! J, (4) is an input/output circuit, and its CPU (1
) sequentially supplies the two-dimensional integer coordinates of the three vertices A, B, and C of the triangle read from its memory (3) to its input/output circuit (4) via the system bus (2). In this example, as shown in Figure 2, the origin O is set at the top left of the display device, the X coordinate is set as an integer whose value gradually increases from left to right in the horizontal direction, and the value is set from top to bottom in the vertical direction. Set the Y coordinate of an integer that gradually increases.

(5) to (7) each indicate a register whose input section is connected to the output section of the input/output circuit (4), and A register (5).
holds the integer coordinates (Xl, Yl) to the vertex, and the B register (6) holds the integer coordinates (X2. Y2) of vertex B.
is held, and the integer coordinates (X3. Y3) of vertex C are held in the C register (7). These registers (5
) to (7) Y coordinates Yl, Y2 and Y
3 are respectively supplied to a Y direction minimum value discriminating circuit (8), and this discriminating circuit (8) supplies the coordinate of the minimum value among these Y coordinates to a horizontal direction scanning circuit (9). This horizontal scanning circuit (9) scans a horizontal scanning line (25) (see FIG. 4) downward from the Y coordinate of the minimum value as a starting point.

(10) to (12) respectively indicate Y-direction array circuits, and the integer coordinates of vertex A held in A register (5) and the integer coordinates of vertex B held in B register (6) are is supplied to the Y-direction array circuit (10), and its vertex A
The integer coordinates of the vertex B and the integer coordinates of the vertex C held in the C register (7) are supplied to the second Y-direction array circuit (11), and the integer coordinates of the vertex B and the integer coordinates of the vertex C are supplied to the third Y-direction array circuit (11).
is supplied to the Y-direction array circuit (12). (13)～(1
5) shows linear approximation coordinate generation circuits connected to the output parts of the Y-direction array circuits (10) to (12), respectively, and the first Y-direction array circuit (10) corresponds to the vertex of side AB of the triangle in this example. The coordinates of A and B are arranged in order of decreasing Y coordinate and are supplied to the first linear approximation coordinate generation circuit (13). Similarly, the second Y
The direction array circuit (11) is the vertex C of the side CA of the triangle in this example.
The coordinates of and A are arranged in ascending order of Y coordinates and supplied to the second linear approximation coordinate generation circuit (14), and the third Y-direction arrangement circuit (12) arranges the coordinates of A and A in ascending order of Y coordinates, and the third Y-direction arrangement circuit (12) arranges the coordinates of and C
The coordinates are arranged in ascending order of Y coordinates and supplied to the third linear approximate coordinate generation circuit (15).

These linear approximation coordinate generating circuits (13) to (15) each generate a series of integer coordinates that are approximated to the edge between two input vertices, as will be described later. Furthermore, these linear approximation coordinate generation circuits (13) to (15) include a horizontal scanning circuit (
9) Vertical coordinate (Y coordinate) of horizontal scanning line (25)
, and these linear approximation coordinate generation circuits (13) to
(15) are the minimum and maximum values (which may coincide with the minimum value) of the horizontal coordinates (X coordinates) of the intersection of the horizontal scanning line (25) and a series of integer coordinates approximated to the above sides, respectively. ) is supplied to the minimum/maximum discrimination circuit (16). In this case, when there is no intersection with the horizontal scanning line (25), two codes NU indicating that there is no intersection are displayed.
Supply LL. That is, this minimum/maximum discrimination circuit (16)
is supplied with six horizontal coordinates including two NULL codes.

The minimum/maximum discrimination circuit (16) determines the minimum value M, IN, and maximum value MAX from among the six horizontal coordinates, and supplies these minimum value MIN and maximum value MAX to the interpolation circuit (17). Then, when all of the supplied horizontal coordinates become the code NULL, the minimum/maximum discrimination circuit (16) supplies the code NULL to its interpolation circuit (17). This interpolator (17) generates a series of horizontal coordinates (X-coordinate F) between its minimum value MIN and maximum value MAX. These series of horizontal coordinates can be considered as a horizontal address XA, and the horizontal scanning line (25) YIIa output from the horizontal scanning circuit (9) can be considered as a vertical address YA. Furthermore, when the code NULL is supplied from the minimum/maximum discrimination circuit (16), this interpolation circuit (17) supplies a ladle control signal to the horizontal direction scanning circuit (9) to stop scanning in the horizontal direction. .

(18) is a memory controller, (19) is a palette register, (20) is a frame buffer (FB) memory, and (21) is a display device, and the memory controller (18) includes a horizontal scanning circuit (9) and Interpolation circuit (1
7) respectively supply a vertical address YA and a horizontal address χA. Further, the CPU (1) sets predetermined R, G, and B color data CD in the palette register (19) via the input/output circuit (4), and the interpolation circuit (17) sets the color data CD in the palette register (19). A control signal for outputting color data CD is supplied to the controller.

The interpolation circuit (17) further includes the memory controller (
18) The minimum value MIN and maximum value MAX are sign NULL.
During the period when the memory controller (18)
For example, during the horizontal blanking period, the vertical address Y
The color data CD is written in the storage area of the frame buffer memo IJ (20') determined by the horizontal address XA and the frame buffer memo! J (20)
The image data read out more periodically is displayed on the display device (21).
supply to.

Regarding the operation of the linear approximation coordinate generation circuit (13) of this example, the second
This will be explained in detail with reference to the figures and FIG.

FIG. 2 shows an example of a triangle ABC to be approximated, and the linear approximation coordinate generation circuit (13) calculates a series of integer coordinates to be approximated to the side AB. In this case, vertex A(X
i, Yl) (7) Y coordinate YH2 vertex B (X2. Y2
) is smaller than the Y coordinate Y2 of ), and the following equation holds true.

Xl-X2 > Yl-Y2 -...(1
) In this case, the linear approximation coordinate generation circuit (13) takes in the coordinates of the two vertices A and B (step (
101)), coordinates of vertex A (XI, Yl) wo1l
Set to the initial position of llIF (step (102)
). Subsequently, in step (103), the horizontal distance ΔX (=ΔXi = l Xl
-X21 ) and vertical distance ΔY (=ΔYl =
l Yl−Y21 ) is determined and step (104
), the interval ΔX and the book interval ΔY are compared.

In this example, ΔX>ΔY holds true from equation (1), so
The horizontal direction (X direction) is the long axis direction, and the vertical direction (Y direction) is the short axis direction. The operation of the linear approximation coordinate generation circuit (13) proceeds to step (105), where movement from the initial position by 1 is performed in the X direction, which is the long axis direction, toward the coordinate x2. As a result, when the horizontal coordinate exceeds x2, the approximation operation ends (step (106))
, when the horizontal coordinates do not exceed x2, the operation moves to step (107), and integer coordinates in the vertical direction (Y direction) close to the original straight line (ie, side AB) are determined. The obtained integer coordinates (X, Y) of the linear approximation are stored in the internal memory (step (10g)), and the operation then shifts to step (105) again to move by 1 in the major axis direction. will be held.

Specifically, as shown in Figure 2, the current integer coordinate in the X direction corresponds to the vertical line (22^), and the Y of side AB
The position of the direction is horizontal line (23A) and line (2
3B) exists between. In this case, the side AB is closer to the line (23A> than the line (23B), so the approximated integer coordinates in the Y direction are the coordinates corresponding to the line (23^). Therefore, the vertical line (22
A) The integer coordinates approximated to the side AB above are pixel P1
are the integer coordinates of Further, when the side AB exists in the center of two horizontal lines, for example, integer coordinates corresponding to the upper line are selected.

Similarly, when moving further in the long axis direction in the direction of coordinate X2, the vertical lines are (22B), (22C),
It changes as... Then, on line (22B), side AB is closest to the horizontal line (23B), so the integer coordinates of pixel P2 are selected as the approximated integer coordinates, and on line (22C), side AB is closest to the horizontal line (23B). Since it is closer to line (23B) than line (23C), the integer coordinates of pixel P3 are selected as the approximated integer coordinates,
Below, a series of integer coordinates approximated to side AB are determined.

Next, in the linear approximation coordinate generation circuit (14), integer coordinates approximated to the side CA are obtained, but the side CA is
: Y-locus IYI of vertex A(XI, Yl)
is smaller than the Y coordinate Y3 of vertex C (X3. Y3),
It is assumed that the following formula holds.

Xl−X3 l < l Yl−Y3 l −−・−
(2) In this case, the horizontal distance ΔX(
= ΔX3= l
The major axis direction of A is the Y direction, and the minor axis direction is the X direction.

Therefore, the operation of the linear approximation coordinate generation circuit (14) is
Moving from step (104) to step (109) in the figure, movement is performed by 1 in the Y direction, which is the major axis direction, in the direction of coordinate Y3. As a result, when the vertical coordinate exceeds Y2, the approximation operation ends (step (110))
, when the vertical coordinate does not exceed Y2, the operation moves to step (111), and an integer coordinate in the horizontal direction (X direction) close to the original straight line (ie, side CA) is determined. The obtained integer coordinates (X, Y) of the linear approximation are stored in the internal memory (step (112)), and the operation then shifts to step (109) again to move by 1 in the major axis direction. Sequence takes place.

Specifically, as shown in Figure 2, the current integer coordinate in the Y direction corresponds to the horizontal line (23B), and the side CA
Since the position in the X direction of is closer to the line (24B) than to the vertical line (24A), the approximated integer coordinate in the X direction is the coordinate corresponding to the line (24B). Therefore, the integer coordinates approximated to the side CA on the horizontal line (23B) are the integer coordinates of the pixel P4. Similarly, in the horizontal line (23C) that is further moved downward by 1, the side CA is closer to the line (24B) than the vertical line (24C), so The integer coordinates approximated to side CA are the integer coordinates of pixel P5.

Furthermore, in the linear approximation coordinate generation circuit (15), a series of integer coordinates approximated to the side BC are obtained, but the side B in the example in FIG.
C has the long axis direction in the X direction like side AB, so side AB
Approximate integer coordinates can be obtained in the same manner as .

To explain in detail the subsequent operations of the linear approximation coordinate generation circuits (13) to (15), for convenience of explanation, the sides AC and CA of the triangle to be approximated are set as shown in FIG. Pixels with integer coordinates approximated to sides AB and CA are indicated by circles. In the example in Figure 4, the horizontal scanning circuit (
9) starts scanning the horizontal scanning line (25) downward from the vertex A whose Y coordinate is Yl, and then scans the horizontal scanning line (25) downward.
5) Y coordinate is generated by linear approximation coordinate generation circuits (13) to 15
).

In FIG. 4, the horizontal scanning line (25) is on side A.
Pixels Q1 and C2 among pixels with integer coordinates approximated to B
, and the X coordinates of pixels Q1 and C2 are respectively a1
and C2 (al<C2), the minimum value of the X coordinate of the intersection of the approximate integer coordinates of side AC and the horizontal scanning line (25) is C2, and the maximum value is al. Also, the X coordinate of the intersection of the approximate integer coordinates of side CA and the horizontal scanning line (25) is cl
~c5 (CI<C2<C3<C4<C5), so the minimum value of the X coordinate of these intersections is C1 corresponding to pixel R1, and the maximum value of the X coordinate is C1 corresponding to pixel R2.
It is 5. Also, side BC and its horizontal scanning line (25)
Since there is no intersection with
Both the minimum value and the maximum value of the coordinates have the sign NULL.

Therefore, the linear approximation coordinate generation circuit (13) supplies the X coordinates C2 and al to the minimum/maximum discrimination circuit (16), and the linear approximation coordinate generation circuit (14) supplies the X coordinates c1 and C5 to the minimum/maximum discrimination circuit (16). and the linear approximation coordinate generation circuit (1
5) supplies the two codes NULL as the X coordinate to the minimum/maximum discrimination circuit (16).

This minimum/maximum discrimination circuit (16) determines the overall minimum value MIN and maximum value MAX among the six X coordinates (ignoring the NULL sign) and supplies it to the interpolation circuit (17), as shown in FIG. In the example, the overall minimum value MIN is C2, and the overall maximum value MAX is C5. Depending on this, the interpolation circuit (
17) has its horizontal scanning line (25) as shown in FIG.
) of a series of pixels indicated by black circles whose X coordinates exist between the minimum value a2 and the maximum value C5 (address in the X direction
A) is supplied to the memory controller (18). However, as shown in the example in Figure 5, the pixel whose X coordinate is C2 and the pixel whose X coordinate is C
For example, instead of including 5 pixels, the X coordinate is the maximum value C
The portion excluding the pixels with a value of 5 may be considered to be the pixels inside the triangle.

In FIG. 4, as the horizontal scanning line (25) is scanned gradually downward, the interpolation circuit (17) detects pixels existing on the horizontal scanning line (25) and inside the triangle. The address of the memory controller (1
8). When the Y coordinate of the horizontal scanning line (25) becomes larger than the Y coordinate Y2 of the vertex B, there are no intersections between the horizontal scanning line (25) and each side of the triangle ABC, so the horizontal scanning line (25) is completed, and the addresses of all pixels inside the triangle are obtained.

As mentioned above, in this example, the horizontal scanning line (25) is scanned over the entire surface of the triangle ABC, and the horizontal scanning line (25) is scanned over the entire surface of the triangle ABC.
5) and the approximate integer coordinates of each side of the triangle ABC in parallel, the address of the pixel inside the triangle ABC can be obtained, so it is always accurate regardless of the shape or placement of the triangle. has the advantage of being able to obtain the addresses of pixels inside the triangle.

Note that the above embodiment shows a circuit that generates the address of a pixel inside a triangle, but for example, in FIG.
Registers (5) to (7), Y-direction array circuit (10) to
(12) By providing N linear approximation coordinate generating circuits (13) to (15), respectively (N = 3.4', 5...), addresses of pixels inside an N-gon are easily determined. , can generate a problem.

Further, instead of scanning the horizontal scanning line (25) over the entire surface of the triangle, for example, a vertically extending scanning line may be scanned horizontally over the entire surface of the triangle.

As described above, it goes without saying that the present invention is not limited to the above-described embodiments, and can take various configurations without departing from the gist of the present invention.

[Effects of the Invention] According to the present invention, there is an advantage that addresses of pixels inside a polygon can be generated by a common circuit configuration and simple processing regardless of the shape and placement of the polygon.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2' is a diagram showing integer coordinates approximated to each side of a triangle, and Fig. 3 is a diagram showing integer coordinates approximated to a straight line. FIG. 4 is a flowchart showing the operation, FIG. 4 is a diagram showing the minimum and maximum values of integer coordinates on the horizontal scanning line, and FIG. 5 is a diagram for explaining the interpolation operation. (5) to (7) are registers, (8) is a Y direction minimum value discrimination circuit, (9) is a horizontal direction scanning circuit, (1o) to (
12) are Y-direction array circuits, (13) to (15) are linear approximation coordinate generation circuits, (16) is a minimum/maximum discrimination circuit, (17) is an interpolation circuit, and (20) is a frame buffer memory. Agent Hidemori Matsukuma

Claims (1)

[Scope of Claims] A holding circuit that holds the coordinates of each vertex of a polygon, an approximation circuit that generates a group of approximate integer coordinates that are respectively approximated to each side connecting each of the vertices, and a predetermined scanning line and the approximation circuit. It has a minimum-maximum circuit that calculates the minimum and maximum coordinates of the integer coordinates of the intersection with the integer coordinate group, and an interpolation circuit that generates the integer coordinates between the minimum coordinate and the maximum coordinate, An address generation circuit inside a polygon, characterized in that integer coordinates successively output from the interpolation circuit when scanning the entire surface of the polygon are respectively regarded as addresses of pixels inside the polygon.