JPH04137052A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve bus traffic and also system performance by fetching data by performing steal by each cache memory. CONSTITUTION:Target areas for a write request from arithmetic units CPU1, CPU2 are registered on the cache memory M1, M2, and write data is written on the cache memory M1, M2 when sharing remains unchanged, and also, it is written on shared memory CM. Also, when access to another cache memory or the shared memory of an I/O device shows write and the area targeted to write is registered on its own cache memory and also, it is unchanged area, the write data included in a write command is stored in its own cache memory by stealing. Thereby, the bus traffic is improved, and the system performance is also improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a cache memory control method in a system having multiple copy-back cache memories and a small amount (at least one shared memory), and which improves bus traffic and improves copy-back cache memory. The purpose is to improve system performance by making full use of the characteristics of memory, and includes a plurality of copy-back type cache memories, a shared memory, and a system bus that connects the plurality of cache memories and the shared memory, Each cache memory has a valid display flag and a valid display flag in each internal entry.
A cache memory control method in a system having an address and a changed display flag, a shared display flag, or a flag indicating four states of invalid, exclusive unchanged, exclusive changed and shared unchanged, the method comprising: If the target area of the write request from the arithmetic unit is registered in the cache memory and is shared and unchanged, a means for writing the write data into the cache memory and also into the shared memory, and another device on the system bus. means for monitoring access to the cache memory of the other cache memory or the shared memory of the I10 device, the access to the other cache memory or the shared memory of the I10 device is writing, and the write target area is within the own cache memory. If the area is registered in the area and is an unchanged area, the write data included in the write command is still stored in the cache memory of the write command.

[Industrial application field]

The present invention relates to a cache memory control method, and particularly to a cache memory control method in a system including a plurality of copy-back type cache memories and at least one shared memory.

In recent years, with the demand for faster computers, arithmetic devices (
As the performance of processors (processors) has improved, multiprocessor systems that use multiple processors have come into use. In order to further improve the performance of the entire system, it has been considered that data is captured by each cache memory performing a steal. At this time, it is desired to avoid data mismatch between cache memories.

[Prior Art] In recent years, the copy-back method, which requires fewer bus accesses than the store-through method, has become mainstream for cache memories. This copy-back type cache memory is a type of cache memory that does not perform bus access even if there is a "hit" when writing cache data, unless there is another memory to share the data, and each time the cache data is rewritten, the shared memory This reduces the frequency of bus access and improves overall system performance compared to a copy-back cache memory that invalidates data in other cache memories.

FIG. 5 is a diagram for explaining the conventional cache memory control method, and a system to which the cache memory control method is applied consists of a plurality of copy-back type cache memories M1 and M2, a shared memory side, and a system to which the cache memory control method is applied. Cache memory M1. M2 and a system bus SB connecting the shared memory port. Each cache memory MLM
2 has a valid display flag ■, a changed display flag M, a shared display flag S, and an address in each internal entry. Here, cache memories M1 and M2
are controlled by arithmetic units CPUI and CPU2, respectively. In addition, cache memories M1 and M2 are used for arithmetic units CPUI and Cache, respectively.
It can also be configured as an internal cache memory provided in the PU2.

As shown in FIG. 5, in the conventional cache memory control method, for example, when CPU 2 makes a write request to cache memory lJM2 (see The target area is registered in cache memory M2 and shared unchanged (V=1
．． S=1. When M=0), the write data is written into the cache memory M2 and also written into the shared memory CM (see "■" in FIG. 5).

[Problem to be solved by the invention]

In the system shown in FIG. 5 described above, conventionally the following (A)
The following methods have been proposed.

(A) Using the above write processing as a buffer invalidation command, all the same areas in other cache memories M1 are cleared. However, with this method, the performance of the system will deteriorate.

(B) The same area in the cache memory Ml is cleared by the above write command ■'. This method also causes a decrease in system performance.

(C) The cache memory M1 steals the data of the above write command. However, in the conventional method, since the state of the cache memory M2 changes to the exclusive area, new write data from the CPU2 is transferred to the CPUUI (
It is not transmitted to the cache memory M1).

(D) After issuing the above write command (■), in the conventional method, the cache memory M2 remained in a shared unaltered state. Therefore, even if the other cache memory (M1) of cache memory M2 is of the type that invalidates written data instead of stealing it, there is no identical area in the other cache memory (M1). However, a write request from the CPU 2 is always reflected in the shared memory CM, which has a slow access time, and the characteristics of the copy-back type cache memory cannot be utilized.

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the prior art, it is an object of the present invention to improve bus trough ink and to improve system performance by fully utilizing the characteristics of a copy-back type cache memory.

[Means for Solving the Problems] According to the present invention, a plurality of copy pack type cache memories M1 and M2, a shared memory side, and a system bus SB connecting the plurality of cache memories and the shared memory are connected. Each cache memory has a valid display flag V, a changed display flag, an empty shared display flag S, or a shared display flag S in each internal entry.

A cache memory control method in a system that has addresses and flags indicating four states: invalid, proprietary not changed, proprietary changed, and shared not changed, and is subject to write requests from arithmetic units CPU1 and CPU2. means for writing write data in the cache memory and also in the shared memory when the area is registered in the cache memory and shared and unchanged (V=1.S・1.M=0); means for monitoring access to the shared memory by another cache memory or I10 device on the system bus, the access to the other cache memory or the shared memory of the I10 device is writing, and the write target area is A cache memory control method is provided that steals the write data included in the write command and stores it in the own cache memory if it is registered in the own cache memory and is an unmodified area. .

[For production]

According to the cache memory control method of the present invention, the arithmetic unit CPU1. The target area of the write request from CPU2 is registered in the cache memory and shared and unchanged (V=
1. S.1, S=1, M=0), the write data is written into the cache memory and also written into the shared memory. In addition, accesses to other cache memories or the shared memory of I10 devices on the system bus are monitored, and accesses to other cache memories or the shared memory of I10 devices are writes, and the area to be written is the own cache memory. If it is registered in memory and is an unmodified area,
The write data included in the write command is stolen and stored in its own cache memory.

This can improve bus traffic and improve system performance.

〔Example〕

Hereinafter, the cache memory control method according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram for explaining the principle of the cache memory control method according to the present invention, and FIG. 2 is a diagram showing an example of a system in which the cache memory control method of the present invention is applied. As shown in FIGS. 1 and 2, the system to which the cache memory control method of the present invention is applied is as follows:
A plurality of copy-back type cache memories MLM2, shared memory CM, and these cache memories M1,
System bus SB connecting M2 and shared memory CM
It is equipped with

Each cache memory M1. M2 has a valid display flag ■, a changed display flag M, a shared display flag S, and an address in each internal entry. Further, the system bus SB includes an address bus, a data bus, and a command bus, and further includes a steal report signal line L, which will be described later.
1 and a reception response signal line L2. Here, cache memories M1 and M2 are each arithmetic unit c.
It is controlled by PU1 and CPt12. Further, the cache memory space and M2 can also be configured as internal cache memories provided in the arithmetic units CPUI and CPU2, respectively.

As shown in FIG. 1(a), for example, when the CPU 2 makes a write request to the cache memory (
(see ■ in FIG. 1(a)), if the target area of the write request from the CPU 2 is registered in the cache memory M2 and shared and unchanged (v=i, s・1.M=0). , the write data is written into the cache memory M2 and also written into the shared memory CM (see (2) in FIG. 1(a)). That is, the written data is reflected in the shared memory CM.

At this time, since the writing target (■) is registered in the cache memory M1, the shared memory C? The write data for I is stolen and the data is stored in the cache memory 1.
(Refer to (1) in the first axis). That is, C
The target area of the write request from PU2 is registered in the cache memory M2 and shared and unchanged (V.1.S
=1. M=0), so when the write data is written in the cache memory M2 and also in the shared memory, the write target area is registered in its own cache memory M1 and the unmodified area ( V・1+S=LM=O; On the left, "X" indicates that it can be either 0 or 1), steals the write data included in the write command and reflects it inside its own cache memory Ml. do.

Then, the cache memory Ml notifies that the write data has been stolen through a signal line on the system bus B (see (2) in FIG. 1(a)). Here, as shown in FIG. 2, the signal line for reporting that a write command has been stolen is constituted by a dedicated steal report signal line L1 provided on the system bus SB.
The level 1 is set so that the assertion of the steal report signal becomes a low level "L". That is, the steal report signal line L1 is set to be at a low level "L" when notifying that a steal has been performed.

Next, assertion of the steal report signal (indicating that a steal has been performed: low level "L") is detected in the cache memory M2 via the steal report signal ILI (in FIG. 1(b), ), the cache memory M2 recognizes that the write data has been stolen by another cache memory (M1), and does not clear the flag indicating sharing (see ■ in FIG. 1(b)). Make it.

That is, the shared display flag S is kept at "1". If the steal report signal is not asserted (that is, the same area does not exist in any other cache memory or the steal report signal line L1 is disconnected), the shared display flag is cleared. Here, the CPU to the area (exclusive area) where the shared flag is cleared
Writing from the system will complete at maximum speed without issuing any commands on the system bus.

Furthermore, as shown in FIG. 1(b) and FIG.
The cache memory M2 that detects the assertion of the steal report signal asserts the dedicated reception response signal line L2 provided on the system bus SB (see (2) in FIG. 1(b)). Here, as shown in FIG. 2, the level of the reception response signal line L2 is set to a low level when the reception response signal is asserted.
It is set to be L″″. In other words, the reception response signal line L2 is at a low level “L” when making a reception response.
It is set so that

Then, when the assertion of the reception response signal is detected between the cache memories that stole the write data via the reception response signal line L2 (see ■ in FIG. 1(b)), the cache memory M1 steals the write data. Recognizing that the report signal has been detected in the cache memory (M2) where the data was written, the line in which the stolen data is stored is made valid and shared (see Figure 1(b)). middle, see ■). That is, the valid display flag (■) is set to "1" and the shared display flag S is set to "1". If the reception response signal is not asserted (that is, the cache memory Ml that issued the write command in ① does not wait for the function to assert the reception response signal, or the reception response signal 1jlL2 is cut off), the steal This will invalidate the line that stored the data.

In the above, the steal report signal line L1 is set to a low level "L'" when a steal is performed,
Furthermore, since the reception response signal line L2 is set to be at a low level "Ln" when a steal report is received, even if the steal report signal line L1 or the reception response signal line L2 is disconnected, Although it cannot improve path traffic, it avoids data mismatch between cache memories.

By the way, in the above-mentioned system, for example, a plurality of copy-back type cache memories (Ml.

If at least one store-through type cache memory exists in addition to M2), the store-through type cache memory is configured to reflect write requests from the processing unit (CPU) on the system bus. will be done. Further, the store-through type cache memory is configured to output, as a reception response, a notification that the report has been received when it receives a report indicating that the cache memory has been stolen from another cache memory in response to a write command. Further, the cache memory (M2) for writing to the shared memory may be an I10 device in addition to the cache memory. In this case, the cache memory (M1) that steals the write data to the shared memory will steal the write data to the shared memory from the I10 device.

FIG. 3 is a state transition diagram of an example of a cache memory to which the present invention is applied. In the figure, state I indicates that the data held in the cache memory (target area) is invalid (V.0), and state EU indicates that the data held in the cache memory is proprietary and unmodified ( V・1.
M=O, S・0), and state EM indicates that the data held in the cache memory has been changed to exclusive use (V・
1. M=1. S.0), and state SU indicates that the data held in the cache memory is shared and unmodified (V.1.M.0°5=1).

In Figure 3, (1) is 1 in response to a read request from the CPU.
When a block is read (transition from state I to state EU), (2) is a read access (maintains state EU)
, (3) is when another cache reads one block from the same area or steals write data from another cache memory, and a response to the steal notification is returned (transition from state EU to state SU). (4) is when a steal notification is asserted (state SU is maintained) when a read access or a write request from the CPU is reflected in the shared memory, and (5) is when another cache memory is accessed to the shared memory. When copying back to shared memory triggered by access (from state fiEM to state M
transition to SU). Also, (6) is for write/read access (maintaining state EM), (7) is for copying back to shared memory to register a new block (transition from state EM to state I), (8) (9) shows the case where one block is read due to a write request from the CPU (transition from state I to state EM), and (9) shows the case of write from the CPU (transition from state EU to state EM).
At this time, no commands are output to the system. Furthermore, if 00) is replaced to register a new block or steals write data from another cache memory and sends a steal notification but no response is returned (transition from state SU to state ), (1
0 is 02 if it is notified from another cache memory that it is a shared area when reading one block due to a read request from the CPU (transition from state I to state SU).
), when the write request from the CPU is reflected in the shared memory, if the steal notification is not asserted (state S
03) indicates a case where a block is replaced for new block registration (transition from state El to state ■).

In the above, the characteristic state transition according to the present invention is (3
), and when a response is returned to the steal notification, the private unchanged state EU (V・1.M・0.S・0) is changed from the shared unchanged state SU (V・1.M=O, S・Work), and if the steal notification is asserted when the write request from the CPU in (4) is reflected in the shared memory, the shared unmodified state 5U (V = 1. M = 0, 5 = 1), steal write data from other cache memories of aω, and if a steal notification is sent but no response is returned, the shared unmodified state 5U (V, 1
．． M = 0, 5 = 1) to the invalid state (V = 0), and when a write request from the CPU on the side is reflected to the shared memory, if the steal notification is not asserted, the shared state remains unchanged. State SO(V・1+n=O+5−
1) to the exclusive unchanged state El (M, M, 0, 5=0). As a result, it is possible to improve the bus trough ink and improve system performance by fully utilizing the characteristics of the copy-back type cache memory.

FIG. 4 is a diagram showing an example of the configuration of a cache memory that implements the present invention. In the figure, reference numeral 41 denotes a tag section (tag memory), which includes an address section for storing the physical address of access data, an entry section, and three status flags ν, M, and S. These three status flags V and S are a valid display flag ■ that indicates whether the pair of address and data is valid, a modified display flag M that indicates whether or not the data has been rewritten, and the cache It consists of a shared display flag S that indicates whether the data in the memory is shared with others.

Reference numeral 42 indicates a data section (cache data memory), and the data section 42 includes a read circuit, a merge circuit, and a write circuit. Here, the flags V, M, and S in the tag section 41 are invalid and proprietary unchanged.

It can be configured as a 2-bit flag indicating four states: proprietary change method and shared unchanged state.

First, the cache memory that issued the store command (
The circuit that realizes the function of the cache memory M2) in FIG. 1 will be explained (FIG. 1 (a) and (b)).
(See ■～■). First, the address of the write request from the CPU and the address held in the tag section 41 are compared by the comparison circuit 431, and if they match, the AND gate 441 performs a logical product with the valid display flag (■). Furthermore, the AND gate 442 performs a logical product of the read/write signal from the CPU supplied via the inverter 451, the output of the AND gate 441, and the shared display flag S. Then, the target area of the write request from the CPU is registered in the cache memory (the output of the comparison circuit 431 is high level 2), and the valid display flag v=1. In the case of the shared display flag S-1, a store cycle is activated to write the write data into the cache memory and also into the shared memory. At this time, since the read/write signal from the CPU is a write, the inverter 45
The output of 1 is high level. Also, the changed display flag M
may be either "0" or "1".

The output of AND gate 442 is supplied to one input of AND gate 443 via delay circuit 461, and the steal notification (steal report signal supplied via steal report signal line L1) is supplied via inverter 454. AN
It is applied to the other input of D gate 443 and logically ANDed by AND gate 443 to define shared display flag S. In other words, the cache memory (cache memory IM in Figure 1) that steals write data
When the steal report signal from the cache memory (first cache memory) that issued the store command is asserted (low level)
The shared display flag S of the tag section 41 in the cache memory 2M) in the figure is maintained at "1". here,
When the steal report signal is not asserted, the shared display flag will be cleared (S=0).

In addition, a response to the steal notification (reception response signal line L2
The reception response signal outputted via the AND gate 4
The output of 43 is processed by an AND gate (buffer) 444 and a transistor 471 and supplied to the reception response signal line L1.

Next, a circuit that realizes the function of a cache memory (cache memory M1 in FIG. 1) that steals write data will be explained ((1) and (b) in FIG.
)). First, the external address of the system bus and the address held in the tag unit 41 are compared by the comparison circuit 432, and if they match, the AND gate 445 performs a logical product with the valid display flag (■). Additionally, the external read/write signal from the system bus provided via inverter 453 and the output of AND gate 445 are ANDed by AND gate 446 . Then, the output of the AND gate 446 is the data section 4.
steals the data that is supplied to the merge circuit of 2 and written to the shared memory from the system bus (data bus),
For example, four words are merged into one block and written into the data section 42 by a write circuit.

Further, the output of the AND gate 446 is processed by an AND gate (buffer) 448 and a transistor 472, and is supplied to the steal report signal line L1 as a steal report signal (steal notification). That is, the access to the shared memory of another cache memory (M2) is a write, and the write target area is registered in its own cache memory (M1) (the output of the comparison circuit 432 is a high level 2 match), and , if the valid indication flag v=1, the steal report signal is asserted (low level).

Furthermore, the output of the AND gate 446 is supplied to one input of an AND gate 447 via a delay circuit 462, and the AND gate 446 is logically ANDed with the reception response signal supplied to the other input of the AND gate 447 via an inverter 452. Be taken.

Then, the reception response signal (from between the cache memories) supplied via the reception response signal line L2 is asserted, and the output of the AND game 446 (delay circuit 462) is at a high level (write data has been stolen). At the time of A
The output of the ND gate 447 is at a high level and the valid display flag V is set to "1". At this time, the changed display flag M may be either "0" or "1".

〔Effect of the invention〕

As described above, according to the present invention, it is possible to improve bus trough ink and improve system performance by fully utilizing the characteristics of a copy-back type cache memory.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the principle of the cache memory control method according to the present invention, FIG. 2 is a diagram showing an example of a system to which the cache memory control method according to the present invention is applied, and FIG. 3 is a diagram for explaining the principle of the cache memory control method according to the present invention. FIG. 4 is a state transition diagram of an example of a cache memory to which the present invention is applied; FIG. 4 is a diagram showing an example of the configuration of a cache memory that implements the present invention; FIG. 5 is a diagram for explaining a conventional cache memory control method. . (Explanation of symbols) CPU1. CPU2...Arithmetic unit, Ml, M2...Cache memory, Side...Shared memory, SB...System bus, ■...Valid display flag, M...Changed display flag, S... -Shared display flag.

Claims (1)

[Claims] 1. Multiple copy-back cache memories (M1
, M2), a shared memory (CM), and a system bus (CM) that connects the plurality of cache memories and the shared memory.
SB), and each cache memory has a valid display flag (V), a changed display flag (M), a shared display flag (S), or invalid, exclusive not changed, exclusive changed, in each internal entry. A cache memory control method in a system that has four flags and addresses indicating four shared and unchanged states, in which an area subject to a write request from an arithmetic unit (CPU1, CPU2) is registered in the cache memory. means for writing write data into the cache memory and also writing the write data into the shared memory when the shared memory is unchanged (V=1, S=1, M=0); and another cache on the system bus. Memory or I/
and means for monitoring access of an O device to the shared memory, the other cache memory or the I/O
Access to the device's shared memory is a write;
A cache memory control method that steals the write data included in the write command and stores it in the own cache memory when the write target area is registered in the own cache memory and is an unmodified area. . 2. The cache memory control method according to claim 1, wherein the cache memory that has stolen the write data of the other cache memory or I/O device is provided with means for reporting that the stolen write command has been stolen. 3. The target area of the write request from the arithmetic unit is registered in the cache memory and shared and unchanged (V=1
, S=1, M=0), a cache memory that is provided with a means for writing write data into the cache memory and also writing to the shared memory sends the steal report in response to the write command. When the write data is stolen, the state of the write target area is changed to shared and unchanged, and when the write data is not stolen, the state of the target area is changed to exclusive or exclusive. 3. The cache memory control method according to claim 2, wherein the cache memory control method is left unchanged. 4. The cache memory according to claim 3, wherein when a write request from the arithmetic unit to the area in the exclusive-change state is performed, the write data is stored only in the cache memory, and no command is output on the system bus. control method. 5. The target area of the write request from the arithmetic unit is registered in the cache memory and shared and unchanged (V=1
, S=1, M=0), a cache memory having means for writing write data into the cache memory and also writing to the shared memory receives the report that the write command has been stolen. and means for outputting a reception response in response to the steal report, and when it is reported that the write command has been stolen, a response is made to the effect that the report has been received. cache memory control method. 6. The cache memory that has stolen the written data has means for receiving a reception response to the steal report, and when the reception response to the steal report indicates that the steal report has been received, the cache memory is subject to the steal. The data consistency is improved by setting the state of the area that has been stolen as shared and unchanged, and invalidating the area that was the subject of the steal when the reception response indicates that no steal report has been received. The cache memory control method according to claim 5. 7. The system further includes at least one store-through type cache memory, and the store-through type cache memory reflects a write request from an arithmetic unit on a system bus, and responds to the write command to another cache memory. 7. The cache memory control system according to claim 6, wherein when receiving a report to the effect that the report has been stolen from the memory, a notification to the effect that the report has been received is outputted as a reception response. 8. The cache memory control method according to claim 1, wherein each of the plurality of cache memories is configured as an internal cache memory provided in an arithmetic unit. 9. Multiple copy-back cache memory (M1
, M2) and a shared memory (CM) are connected by an address bus, a data bus, and a command bus, and access to the shared memory of another cache memory or I/O device is a write, and the write target area is its own. Registered and unmodified area in cache memory (V=
1, S=1, M=0), the system bus (SB) used in a system that steals write data included in a write command and stores it in its own cache memory, A system further comprising: a steal report signal line (L1) that reports the stealing in response to a write command; and a reception response signal line (L2) that outputs a reception response in response to the steal report. bus. 10. The steal report signal line is set to a low level "L" when the steal is performed, and
10. The system bus according to claim 9, wherein the reception response signal line is set to a low level "L" when a steal report is received.