KR0145454B1 - Multi-processor having distributed shared memory - Google Patents

Abstract

The present invention relates to a distributed shared memory multiprocessor having a shared system bus and at least one system module coupled to the system bus. The system module of s includes a local memory module and a local processor module, the local processor module includes a processor and a cache, and the local processor module specifies whether the block is valid for each block stored in the local memory module. And a state information storage device having state information. With this distributed shared memory multiprocessor, access bottlenecks on shared system buses are alleviated, and fast memory access increases processor throughput per unit time and speeds up memory access.

Description

Multiple processors with distributed shared memory

1 illustrates an exemplary shared memory multiprocessor.

Figure 2 illustrates a typical shared memory multiprocessor with a cache included in each processor module.

3 illustrates a distributed shared memory multiprocessor.

4 illustrates a distributed shared memory multiprocessor including an improved write-invalidate cache system of the present invention.

FIG. 5 illustrates the contents of the directory cache included in the improved write invalidation cache system of FIG.

Figure 6 illustrates in block diagram form an improved write-invalidate cache system of the present invention.

FIG. 7 illustrates another embodiment of a distributed shared memory multiprocessor including an improved write-invalidate cache system of the present invention in which a cyste module may be configured to include only local memory modules.

FIG. 8 illustrates another embodiment of a distributed shared memory multiple processor comprising a write-invalidate cache system of the present invention in which the system module may comprise only local processor modules.

9 illustrates another embodiment of a distributed shared memory multiprocessor including an improved write-invalidate cache system of the present invention in which the system module may comprise only a local memory module or a local processor module.

* Explanation of symbols for main parts of the drawings

100,100 ': Local memory module 200,200': Regional processor module

300,300 ': cyste module 400: shared bus

500,500 ': Processor 600,600': Cache

610: processor tag cache 611: comparator

620: Bus monitor tag cache 621: Comparator

630: state information cache 640: data cache

650: processor directory cache 660: cache controller

670: processor-bus interface

TECHNICAL FIELD The present invention relates to multiprocessors and, more particularly, to a new cache system for distributed shared memory multiple processors.

Shared memory multiprocessors are a very economical way to increase system computing power and speed, largely due to the fact that high performance microprocessors can be economically interconnected via shared memory modules and a common bus. Figure 1 illustrates the structure of a typical shared memory multiprocessor in which a plurality of processor modules are coupled with a plurality of shared memory modules by a shared bus.

However, two fundamental problems are inherent in such a system configuration. In other words, bus contention occurs when multiple processor modules attempt to access a shared bus at the same time, and memory contention occurs when multiple processor modules attempt to access a memory module at the same time. This is it. These problems increase memory access time, which in turn reduces the execution time of multiple processors.

Therefore, in order to reduce the number of shared bus access collisions and memory access collisions, it is important to reduce the traffic between the processor module and the memory module as much as possible, and the processor module is a block of memory modules that the processor is expected to use frequently. Blocks can reduce the number of access requests to the shared bus and memory module by storing it in its own cache, which has a smaller capacity than the memory module but provides much faster access times. 2 illustrates a configuration of a shared memory multiprocessor including a cache in all processor modules.

However, in the case of such shared memory multiprocessors, each processor module uses its own cache, so if one processor module writes to a block stored in its own cache, the result of the write operation is different for all other processor modules. There is a so-called cache coherence problem that must be reflected in the corresponding blocks stored in its own cache. Various cache coherence methods have been proposed to solve the cache coherency problem and to reduce the number of bus and memory access requests of the processor module. Among these schemes, one of the most widely used schemes for shared memory multiprocessors is, for example, a write-invalidate cache coherence scheme.

In this write-invalidate cache coherence scheme, the cache within the processor module maintains state information for each block stored therein, which state information is stored in at least three possible cache block states (i.e., MODIFIED, INVALID, and SHARED). Express one. The MODIFIED state means that the block was most recently changed in the cache but not yet updated in the memory module. When a block in the MODIFIED state is replaced with a new block according to a block replacement procedure described later, the block must be copied back to the corresponding memory module. The INVALID state means that the block has been updated and invalidated by another processor module. The SHARED state means that the block has not changed in the cache, has not been invalidated by another processor module, and is consistent in content with the block stored in that memory module. This cache coherency scheme generally works for block access requests from processors in a processor module as follows.

Read-hit-A cache in a processor module holds a block that has been requested to be read, either in the SHARED or MODIFIED state, in which case the processor module reads the block.

Read-miss-The cache in a processor module does not hold a block that has been requested to read, or holds a block that has been read in an INVALID state, in which case the processor module is attached to a processor module other than the memory module. Send a broadcast read request for the block. If one of the other processor modules holds the requested block in the MODIFIED state, the processor module provides the block for the broadcast read request. If another processor module does not hold the requested block in the MODIFIED state, the memory module holding the requested block provides the block for the broadcast read request. Accordingly, the processor module receives the requested block, stores it in its own cache in the SHARED state, and performs a read operation.

Write-hit-The cache in a processor module holds a block for which a write request has been made in the SHARED or MODIFIED state. If the cache is held in the MODIFIED state, the processor module immediately performs a write operation on the block. If a cache in a processor module holds a requested block in the SHARED state, the processor module sends an invalidation request for that block to all other processor modules so that all other processor modules can access the requested block stored in their cache. After the copy is invalidated, a write operation is performed on the requested block stored in its own cache, and the state of the cache block is changed to MODIFIED.

Write-miss-If the cache in the processor module does not hold a block that has been requested to write, or holds a block that has been requested to be written in the INVALID state, the processor module may send a broadcast containing an invalidation request for that block. Sends a broadcast read with invalidation request to memory modules and other processor modules, allowing all other processor modules to invalidate a copy of the requested block stored in their cache, while one of the other processor modules requests If the block is held in the MODIFIED state, the processor module provides the block for the broadcast read request including the invalidation request. Alternatively, if neither processor module holds the request or block in the MODIFIED state, the memory module holding the requested block provides the block for the broadcast read request containing the invalidation request. Accordingly, the processor module receives the requested block, stores it in its cache in the MODIFIED state, and performs a write operation.

Various variations of the write-invalidate cache coherence protocol described above are described, for example, in Per Stenstrom's A Survey of Cache Coherence Schemes for Multprocessors (IEEE Computer, June 1990, pp. 12-24), J. Archibald and JL Baer. Cache Coherence Protocols: Evaluation Using A Multiprocessor Simulation Model (ACM Transactions on Computer Systems, Nov. 1986, pp. 273-298).

However, a typical shared memory multiprocessor, such as in FIG. 2 employing the various write-invalid cache coherence protocols described above, may also request a broadcast read or invalidate request for a block if a cache fails for that block. Embedded broadcast read requests must be sent over the shared bus to memory modules and other processor modules. Thus, bottlenecks can occur in shared memory and shared buses.

The shared memory multiprocessor illustrated in FIG. 3 is known to mitigate bottlenecks in shared memory and shared buses created by the cache failure described above while retaining the advantages of the shared memory multiprocessor. As shown in FIG. 3, in the distributed shared memory multiprocessor, each system module is a form in which the above-described processor module and the shared memory module are integrated into one system module (hereinafter, each processor module and memory in the system module). Each module is referred to as a local processor module and a local memory module, and the same typical shared memory multiprocessor in FIG. 2 is referred to as a centralized shared memory multiprocessor.)

This distributed shared memory multiprocessor, in contrast to a centralized shared memory multiprocessor, provides uniform memory access time for any block stored in any memory module, the system module is stored in its own local memory module. It is possible to provide non-uniform memory access time that takes less time to access a block stored in a local memory module of another system module than the time of accessing the block. Memory Bottlenecks in shared memory and on shared buses can be mitigated.

First, a processor module with a cache failure in a centralized shared memory multiprocessor must send a request for access to the block to a memory module and another processor module through a shared bus. If the block is stored in a local memory module in its own system module, the processor module can reduce the access bottleneck on the shared bus by sending the request to its local memory module without using the shared bus. In addition, since the local memory module can transmit a block requested by the local processor module in its system module to the local processor module without using the shared bus, the access bottleneck on the shared bus can be reduced.

Second, as described above, when a cache failure occurs, the local processor module transmits a request for access to the block to the local memory module without using the shared bus when the block is stored in the local memory module of the system module. The time spent waiting for the block requested by the local memory module is reduced compared to the centralized shared memory multiprocessor, which can increase the processor's hourly throughput.

However, even though the distributed shared memory multiprocessor is a structure capable of providing the above advantages, when the conventional write-invalidate cache coherence protocols are adopted, the above-described advantages are not sufficiently provided.

In other words, if the conventional write-invalidate cache coherency maintaining scheme is adopted for distributed shared memory multiprocessors, the local processor module in which the cache failure occurs is updated with a cache in another local processor module (for example, the MODIFIED state). Is not known in advance, so it is possible to send a broadcast read request for the block or a broadcast read request containing an invalidation request to the local processor module and local memory module in other system modules via the shared bus. must do it. That is, if a local processor module having a cache failure can know in advance that the block is stored in its own memory module and not updated in the cache in the local processor module of other system modules, the local processor module does not use the shared bus. Although you can send a request for that block directly to your local memory module, you can use the shared bus to send a broadcast read request for that block, including a broadcast read request or an invalidation request. It must be transferred to the memory module. Thus, if conventional write-invalidate cache coherence schemes are adopted and used in a distributed shared memory multiprocessor, the advantages of the distributed shared memory multiprocessor described above may not be fully exploited.

However, if the local processor module where the cache failure occurred can determine that the block is stored in its own local memory module and not updated in the cache in the local processor module of other system modules, the local processor module Since it is not necessary to send a broadcast read request for a corresponding block or a broadcast read request including an invalidation request to a local processor module and a memory module of another system module, the read request is transmitted only to its own system module local memory module. Can provide advantages.

Accordingly, a primary object of the present invention is to provide an improved write-invalidate cache system for a distributed shared memory multiprocessor with a shared bus, while maintaining cache coherency and at the same time the shared bus, which is an advantage of the distributed shared memory multiprocessor described above. The goal is to alleviate access bottlenecks on shared memory and provide faster memory access times.

A multiprocessor having a distributed shared memory according to the present invention for achieving the above object is a distributed system comprising a shared system bus, at least two system modules each having a local processor module and a local memory module coupled to the system bus. In the shared memory multiprocessor, the local processor module maintains, for each block included in the local memory module, state information indicating whether the block is stored in a valid state in the local memory module. It further comprises a directory cache.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 4, an exemplary block diagram of a distributed shared memory multiple processor in accordance with an embodiment of the present invention, using the improved write-invalidate cache system of the present invention, is shown schematically. As shown, in a distributed shared memory multiprocessor, at least two or more system modules 300, 300 'are coupled by a shared bus 400, as in conventional distributed shared memory multiprocessors, each system module. May include a local processor module 200 or 200 'and a local memory module 100 or 100', and the local processor module 200 or 200 'may include a processor (500 or 500') and a cache (600 or 600 '). ). In the local memory module 100 or 100 'and the cache 600 or 600', data is divided into blocks of the same size and stored. Access to a block stored in the cache 600 or 600 'is initiated by passing the block's physical address along with a request for access to the block from the processor 500 or 500'. Since the cache 600 or 600 'has the same structure and function, only the cache 600 will be described in detail below. In addition, in the following description of an embodiment of the present invention, a case in which the cache 600 uses a direct mapping method as described below will be described. However, the present invention provides a mapping method in which the cache 600 is different. It is understood that the same applies to the use of, for example, n-way set-associative mapping (Mano.MM Computer System Architecture, Prentice Hall, 193). shall.)

When the physical address of a block is given n bits, double, eg, lower k bits, are used to access the block in cache 600. This lower k-bit part is called a block address, and the remaining upper n-k bit parts are called a tag address. Each block in cache 600 consists of data and tag addresses associated with it. Thus, when one block is newly stored in the cache 600, the data and the tag address are stored together. In this case, when the physical address of the block arrives at the cache 600 with a request for access to one block from the processor 500, the block address portion of the physical address is used to access the block in the cache 600. The tag address portion of the physical address is used to compare the tag address bits of the block in the cache 600 accessed by the block address portion. If the tag address portion of the physical address matches the tag address bits from the cache, then the cache 600 holds the block.

In addition, the cache 600 maintains cache block state information indicating the current state (for example, MODIFIED, SHARED, INVALID state, etc.) of the block for each cache block stored, and thus, It solves the problem of maintaining cache coherency.

As described above, if a distributed shared memory multiprocessor simply adopts a conventional write-invalidate cache coherence scheme, if a cache failure for one block occurs in a local processor module, the block is stored in its own local memory module. Even if the block is not updated and stored in the cache in another local processor module, a broadcast read request for that block must be sent to the local memory module and the local processor module in the other system module via the shared bus. Therefore, such a distributed shared memory multiprocessor cannot improve performance. However, in the distributed shared memory multiprocessor of the present invention, when a cache failure occurs in a local processor module, the block is stored in a local memory module in a system module in which the local processor module includes the module and the other local processor. You can determine when the module is not storing the block in an updated state (for example, in the MODIFIED state), and if so, a broadcast read request that contains a broadcast read request or an invalidation request. By sending requests for the block to its own local memory module instead of sending it to local memory modules and local processor modules in other system modules, it alleviates access bottlenecks on shared buses. Increased throughput and distributed shared notes It may well demonstrate the advantage of multiple processors.

When a cache failure occurs in a local processor module, the block is stored in a local memory module within the system module that the local processor module implies, and another local processor module has updated the block (for example, In order to provide the ability to determine whether it is being stored in a MODIFIED state, the cache system 600 of the present invention, as shown in FIG. 5, stores all memory blocks stored in its local memory module 100 in the processor directory cache 650. For at least two memory block state information indicating whether each block is valid, i.e. not stored in the cache 600,600 'in another local processor module 200,200', e.g. Keep the CLEAN status distinct.

In the DIRTY state, the corresponding memory block stored in the local memory module 100 is not valid, and the block is updated in the cache 600 'in the local processor module 200 and 200' (for example, the MODIFIED state). Means. In the CLEAN state, the corresponding memory block stored in the local memory module 100 is valid, and the block is not stored in the cache 600 'in the local processor module 200 or 200' as an updated state (for example, the MODIFIED state). Means.

Of course, the cache system 600 of the present invention corresponds to the area within the local memory 100 module, the block requested to access from the processor 500 or from the other processor 500 'through the system bus 400. Have the ability to judge whether or not

6, an embodiment of the cache 600 according to the present invention is shown in block diagram form. As shown, the cache 600 includes a processor tag cache 610 and a bus monitor tag cache 620 that hold tag addresses of blocks stored in each cache 600; Two comparators 611 and 621 coupled to the processor tag cache 610 and the bus monitor tag cache 620 respectively; For each cache block stored, a state information cache 630 for storing the state of the block; A data cache 640 that stores a cache block; For each memory block stored in local memory module 100, a processor directory cache 650 for storing one of at least two memory block states as described above; Cache controller 660; A processor-bus interface 670 that connects the processor 500 and cache 600 to the system bus 400.

When the processor 500 transmits an access request for one block and the physical address of the block to the cache 600, the portion of the physical address represented by the block address is the processor tag cache 610 and the status information cache 630. ) And the data cache 640, and the entire physical address is used to access the processor directory cache 650. The comparator 611 receives a tag address from the processor tag cache 610 and another part of the physical address expressed as a tag address as input and performs a comparison operation. If these two inputs match in comparator 611, then cache 600 holds the requested block. If the physical address of the block corresponds to its own local memory area, the status information from the processor directory cache 650 specifies whether the block stored in its local memory module 100 is in the DIRTY state or the CLEAN state. do.

The cache controller 660 is provided with information on whether the above-described inputs from the comparator 611 match the state information from the state information cache 630 and the processor directory cache 650, and the processor 500. In response to a request from and / or an instruction from the system bus 400, the state information cache 630 and the state information of the processor directory cache 650 for that block are checked / changed, as shown below. Check / change COMMAND, MODIFY lines, etc., and control and synchronize the overall operation of cache 600.

Referring back to FIG. 4, communication between major elements of the distributed shared memory multiprocessor is accomplished on system bus 400. As shown in FIG. The system bus 400 includes three buses, an address bus, a data bus and a control bus. The control bus may also include COMMAND and MODIFY lines.

The COMMAND line is a broadcast read request between a local memory module 100, 100 'and a local processor module 200, 200', an invalidation request that will be described in more detail later, and a broadcast read containing an invalidation request. Send commands that include a broadcast read with invalidation request.

The MODIFY line is a state in which the block is updated by another local processor module that stores the block in its cache for a broadcast read request sent by one processor module or a broadcast read request that contains an invalidation request. For example, it is used to inform the local processor module that sent the request and the local memory module that stores the block if the data is stored in the MODIFIED state. For example, if a local processor module sends a broadcast read request to a local memory module and another local processor module due to a cache failure for a block, the other local processor module may cache the state of that block in its cache. According to the information, the corresponding signal is asserted on the MODIFY line. The local processor module sending the request can then examine the MODIFY line to determine whether the block against the other local processor module is in an updated state (eg, MODIFIED state). In addition, the local memory module storing the block may stop the processing of the broadcast read request including the broadcast read request or the invalidation request when the MODIFY signal is applied by checking the MODIFY line.

Hereinafter, exemplary operations of system modules 300 and 300 'including caches 600 and 600' in accordance with one embodiment of the present invention are described for each case of read hits, read failures, write hits, and write failures. Will be. In the following description, it is assumed that the processor 500 included in the local processor module 200 in the system module 300 generates a read and write request for one block to the cache 600. Also, in this description, block replacement selects a block to be replaced in the cache 600 included in the local processor module 200, and if the selected block is in the updated state, that is, the MODIFIED state, the block is replaced. (I.e., an updated copy of that block) to the local memory module 100 or 100 '. At this time, if the block is stored in its own local memory module 100, the local processor module 200 evicts the block into its own local memory module 100 without using the shared bus 400, and the processor directory. Change the state of that block in cache 650 to CLEAN. If the block is not stored in its local memory module 100, the local processor module 200 uses the shared bus 400 to transfer the block to the local memory module 100 in the corresponding system module 300 ′. Local processor module 200 'in the system module 300' changes the state of the block in the processor directory cache 650 to CLEAN.

In the case where the cache 600 in the read hit-local processor module 200 holds a block in which the read request is valid, that is, in a MODIFIED or SHARED state, the cache 600 stores the block in the processor ( 500).

If the cache 600 in the read failure-local processor module 200 does not hold a block that has been requested to be read or is in the INVALID state, and does not hold the block in the cache 600, the local processor module ( 200) performs block replacement first and then performs an operation, and if it is held in an INVALID state, the following operation is performed immediately.

The block requested by the processor 500 is not stored in its own local memory module 100, or the block requested by the processor 500 is stored in its own local memory module 100, and its block from the processor directory cache 650. If the state of the block is DIRTY, the local processor module 200 requests a broadcast read for that block to the local processor modules 200 'and the local memory modules 100' in other system modules 300 '. Send it. If any one of the other local processor modules 200 'holds the requested block in the MODIFIED state, the local processor module 200' applies a MODIFY signal to the MODIFY signal line and, in response to the broadcast read request, It responds by providing a copy of the block stored in its own cache 600 'and changes the state of that block stored in its own cache 600' to the SHARED state. At this time, the local memory module 100 ′ storing the requested block examines the MODIFY line during this transaction, and provides a copy of the block for the read request if the MODIFY signal is not applied. Otherwise, the local memory module 100 'receives a valid copy of the block transmitted by the local processor module 200' that has applied the MODIFY signal and updates the memory. In addition, through the above-described process, the local processor module 200 requests the system bus 400 for a valid copy of the requested block from any one of the other local memory modules 100 'or the other local processor modules 200'. It transmits to its own local processor module 200 without the need. The processor module 200 sends a valid copy of the requested block to its local processor module 200 without having to request the system bus 400. When the processor module 200 receives a valid copy of the requested block, the processor module 200 stores the received block in its own cache 600 in the SHARED state, performs a corresponding read operation, and stores the block in its local memory module 100 '. The retaining local processor module 200 'converts / maintains the state of the memory block stored in the processor directory cache 650' to the CLEAN state.

On the other hand, if the block requested by the processor 500 is stored in its own local memory module 100 and the state of the corresponding memory block from the processor directory cache 650 is CLEAN, the local processor module 200 is configured as a system bus ( The read request for the block is transmitted to the local memory module 100 without the need for requesting 400). Accordingly, the own local memory module 100 also transmits a copy of the block to its own local processor module 200 without having to request the system bus 400. When the processor module 200 receives a valid copy of the requested block, the processor module 200 stores the received block in its own cache 600 in the SHARED state and performs a corresponding read operation.

The cache 600 in the write hit-local processor module 200 holds a block in which the write request is in a valid state, that is, in a MODIFIED or SHARED state, and holds the requested block in the MODIFIED state. If so, the local processor module 200 immediately performs the write operation.

If the cache 600 in the local processor module 200 holds the requested block in the SHARED state, the local processor module 200 tells the local processor modules 200 'of all other system modules 300'. Sends an invalidation request for the block, causing the local processor modules 200 'of the other system modules 300' to change the state of the copy of the requested block they have to the INVALID state, and the local memory module (100 or 100). The local processor module 200 or 200 holding the block at ") converts / maintains the state of the memory block stored in the processor directory cache 650 or 650 'to the DIRTY state. After all of these copies have been invalidated, the local processor module 200 which sent the invalidation request performs a write operation on the corresponding block and changes the state of the block to the MODIFIED state.

If the cache 600 in the write failure-local processor module 200 does not hold the block that has been requested to be written or holds the INVALID state, and does not hold the block in the cache 600, the local processor module ( 200) performs block replacement first and then performs the operation, and if it is held in the INVALID state, performs the following operation immediately.

If the block requested by the processor 500 is not stored in its own local memory module 100, the local processor module 200 may be configured to include the local local processor module 200 ′ and the local memory module ( 100 ') sends a broadcast read request containing an invalidation request for that block. If any one of the other local processor modules 200 'holds the requested block in the MODIFIED state, the local processor module 200' applies a MODIFY signal to the MODIFY signal line and broadcasts the invalidation request. Respond to the cast read request by providing a copy of the block stored in its own cache 600 'and change the state of the block stored in its own cache 600' to the INVALID state. The local processor module 200 'of the system module 300' that holds the block in the local memory module 100 'also converts the state of the memory block stored in its processor directory cache 650' to the DIRTY state. Local memory module 100 'examines the MODIFY line during this transaction and, if the MODIFY signal is not present, provides a copy of the block for the broadcast read request containing the invalidation request. . When the local processor module 200 receives a valid copy of the requested block from one of the other local memory modules 100 'or the other local processor modules 200' through the above-described process, the received processor blocks the MODIFIED state. The cache is stored in its own cache 600 and the read operation is performed.

If the block requested by the processor 500 is stored in its own local memory module 100 and the state of the memory block from the processor directory cache 650 is DIRTY, then the local processor module 200 (the conventional In the cache coherence scheme, a broadcast read request including an invalidation request may include local memory modules 100 'and local processor modules 200' in its own local memory module 100 and other system modules 300 '. Broadcast read requests, including invalidation requests for the block, to the local memory module 100 'and the local processor module 200' of its own local memory module 200 and other system modules 300 '. Send cache-caches read request containing the invalidation request for that block only to local processor modules 200 'in other system modules 300'. Accordingly, the local processor module 200 'which holds the requested block in the MODIFIED state transmits a copy of the block stored in its own cache 600' to the local processor module 200 to include the invalidation request. Respond to a cache read request and convert the state of the block stored in its cache 600 'to the INVALID state. When the local processor module 200 receives a valid copy of the requested block, the local processor module 200 stores the received block in its cache 600 in the MODIFIED state and performs a corresponding write operation.

On the other hand, if the block requested by the processor 500 is stored in its own local memory module 100 and the state of the memory block from the processor directory cache 650 is CLEAN, the local processor module 200 is configured for all other systems. Sends an invalidation request for the block to the local processor modules 200 'of the modules 300' so that other local processor modules 200 'change the state of the copy of the requested block they have to the INVALID state, The local memory module 100 transmits a read request for the block.

Accordingly, the local memory module 100 transmits a copy of the block to its own local processor module 200 without having to request the system bus 400. When the local processor module 200 receives a valid copy of the requested block, it stores the received block in its cache 600 in the MODIFIED state and simultaneously converts the state of the block in the processor directory cache 650 into the DIRTY state. , The corresponding write operation is performed.

As an improved embodiment of the present invention described above, the cache system 600 may include the following four cache block states for each cache block. That is, the MODIFIED state, MODIFIED-SHARED state, SHARED state, and INVALID state are them, and the MODIFIED state, MODIFIED-SHARED state, and SHARED state are all valid cache block states.

The MODIFIED state and the MODIFIED-SHARED state indicate that the block was most recently updated in cache 600 (that is, cache 600 holds an updated copy of that block) and the area in which the block is stored. It does not match that in the memory module 100 or 100 '. The MODIFIED state also means that the block does not exist in a valid state in another cache 600 ', respectively. The SHARED state indicates that the state of the block is only valid. In this case, the local processor module 200 having the block in the MODIFIED state or the MODIFIED-SHARED state becomes the owner of the block, and thus, upon receiving an access request for the block from other local processor modules 200 ', Responsible for the response.

Hereinafter, exemplary operations of system modules 300 and 300 'comprising caches 600 and 600' in accordance with an improved embodiment of the present invention are described in each case of read hits, read failures, write hits and write failures. Will be described. In the following description, it is assumed that the processor 500 included in the local processor module 200 in the system module 300 generates a read and write request for one block to the cache 600. Also, in this description, block replacement selects a block to be replaced in the cache 600 when the cache 600 included in the local processor module 200 does not hold the requested block, and if selected, When a block is updated, that is, in a MODIFIED-SHARED state or in a MODIFIED state, the block (i.e., an updated copy of the block) is evicted to the local memory module 100 or 100 '. At this time, if the block is stored in its own local memory module 100, the local processor module 200 evicts the block into its own local memory module 100 without using the shared bus 400, and the processor directory. Change the state of that block in cache 650 to CLEAN. If the block is not stored in its local memory module 100, the local processor module 200 uses the shared bus 400 to transfer the block to the local memory module 100 in the corresponding system module 300 ′. Local processor module 200 'in system module 300' changes the state of the block in processor directory cache 650 'to CLEAN.

If the cache 600 in the read hit-local processor module 200 holds a block that has been requested to be read, that is, in any of the states MODIFIED, MODIFIED-SHARED, or SHARED, the cache 600 is Deliver the block to the processor 500.

If the cache 600 in the read failure-local processor module 200 does not hold a block that has been requested to be read or is in the INVALID state, and does not hold the block in the cache 600, the local processor module ( 200) performs block replacement first and then performs the operation, and if it is held in the INVALID state, performs the following operation immediately.

If the block requested by the processor 500 is not stored in its own local memory module 100, the local processor module 200 may be configured as the local processor module 200 ′ and the local memory module (s) of all other system modules 300 ′. 100 ') to send a broadcast read request for that block. If any one of the other local processor modules 200 'holds the requested block in the MODIFIED or MODIFIED-SHARED state, the local processor module 200' applies a MODIFY signal to the MODIFY signal line and broadcasts the broadcast. Responds by providing a copy of the block stored in its own cache 600 'for a read request, and changes / maintains the state of the block stored in its own cache 600' to a MODIFIED-SHARED state. At this time, the local memory module 100 ′ storing the requested block examines the MODIFY line during this transaction, and provides a copy of the block for the read request if the MODIFY signal is not applied. Otherwise, the local memory module 100 'receives the valid copy of the block transmitted by the local processor module 200' which has applied the MODIFY signal and updates the memory. When the local processor module 200 receives a valid copy of the requested block from any one of the other local memory modules 100 'or the other local processor modules 200' through the above-described process, the received block is in the SHARED state. The local processor module 200 ', which stores the data in its own cache 600 and performs the read operation, and holds the block in its own local memory module 100', has its memory stored in the processor directory cache 650 '. Convert / maintain block state to CLEAN state.

If the block requested by the processor 500 is stored in its own local memory module 100 and the state of the memory block from the processor directory cache 650 is DIRTY, then the local processor module 200 (the conventional In the cache coherence scheme, instead of sending a broadcast read request to local processor modules 200 'and local memory modules 100' of its own local memory module 100 and other system modules 300 ') A cache-caches read request for the block is sent to the local processor modules 200 'of all other system modules 300'. Accordingly, the local processor module 200 'holding the requested block in the MODIFIED state or the MODIFIED-SHARED state transmits a copy of the block stored in its cache 600' to the local processor module 200 '. Responds to a cache-caches read request and converts / maintains the state of the block stored in its cache 600 'to the MODIFIED-SHARED state. When the local processor module 200 receives a valid copy of the requested block, the local processor module 200 stores the received block in its cache 600 in the SHARED state and performs a corresponding read operation.

On the other hand, if the block requested by the processor 500 is stored in its own local memory module 100, and the state of the memory block from the processor directory cache 650 is CLEAN, the local processor module 200 is a system bus ( The read request for the block is transmitted to the local memory module 100 without the need for requesting 400). Accordingly, the local memory module 100 also transmits a copy of the block to its own local processor module 200 without having to request the system bus 400. When the processor module 200 receives a valid copy of the requested block, the processor module 200 stores the received block in its cache 600 in the SHARED state and performs a corresponding read operation.

When the cache 600 in the write hit-local processor module 200 holds a block in which the write request is valid, that is, MODIFIED, MODIFIED-SHARED, or SHARED state, the requested block is MODIFIED. If so, the local processor module 200 immediately performs a write operation.

If the cache 600 in the local processor module 200 holds the requested block in either MODIFIED-SHARED or SHARE state, the local processor module 200 is the local processor of all other system modules 300 '. Send the invalidation request for the block to the modules 200 'so that the local processor modules 200' in the other system modules 300 'change the state of the copy of the requested block they hold to the INVALID state. The local processor module 200 or 200 ', which holds the block in its own local memory module 100 or 100', converts the state of the memory block stored in the processor directory cache 650 or 650 'to the DIRTY state. Keep it. After all of these copies have been invalidated, the local processor module 200 which sent the invalidation request performs a write operation on the corresponding block and changes the state of the block to the MODIFIED state.

If the cache 600 in the write failure-local processor module 200 does not hold the block that has been requested to be written or holds the INVALID state, and does not hold the block in the cache 600, the local processor module ( 200) performs block replacement first and then performs the operation, and if it is held in the INVALID state, performs the following operation immediately.

If the block requested by the processor 500 is not stored in its own local memory module 100, the local processor module 200 may be configured to include the local local processor module 200 ′ and the local memory module ( 100 ') sends a broadcast read request containing an invalidation request for that block. If any of the other local processor modules 200 'holds the requested block in the MODIFIED or MODIFIED-SHARED state, the local processor module 200' applies a MODIFY signal to the MODIFY signal line and requests the invalidation. Responds by providing a copy of the block stored in its own cache 600 'for a broadcast read request containing a, and changes the state of that block stored in its own cache 600' to an INVALID state. The local processor module 200 'of the system module 300' that holds the block in the local memory module 100 'also converts the state of the memory block stored in its processor directory cache 650' to the DIRTY state. / Maintain, the local memory module 100 'examines the MODIFY line during this transaction and, if the MODIFY signal is not authorized, provides a copy of the block for the read request containing the invalidation request. When the local processor module 200 receives a valid copy of the requested block from one of the other local memory modules 100 'or the other local processor modules 200' through the above-described process, the received processor blocks the MODIFIED state. The cache is stored in its own cache 600 and the corresponding write operation is performed.

If the block requested by the processor 500 is stored in its own local memory module 100 and the state of the corresponding memory block from the processor directory cache 650 is DIRTY, the local processor module 200 (the conventional In the cache coherence scheme, a broadcast read request including an invalidation request is transferred to local memory modules 100 'and local processor modules 200' of its own local memory module 100 and other system modules 300 '. Instead of sending), a cache-caches read request containing an invalidation request for that block is sent only to the local processor module 200 'in all other system modules 300'. Accordingly, the local processor module 200 'holding the requested block in the MODIFIED or MODIFIED-SHARED state transmits a copy of the block stored in its own cache 600' to the local processor module 200 to request the invalidation. Responds to a cache-cache read request, which converts the state of the block stored in its cache 600 'to the INVALID state. When the local processor module 200 receives a valid copy of the requested block, the local processor module 200 stores the received block in its cache 600 in the MODIFIED state and performs a corresponding write operation.

On the other hand, if the block requested by the processor 500 is stored in its own local memory module 100 and the state of the memory block from the processor directory cache 650 is CLEAN, the local processor module 200 is configured for all other systems. Sends an invalidation request for the block to the local processor modules 200 'of the modules 300' so that other local processor modules 200 'change the state of the copy of the requested block they have to the INVALID state, The local memory module 100 transmits a read request for the block.

Accordingly, the local memory module 100 transmits a copy of the block to its own local processor module 200 without having to request the system bus 400. When the local processor module 200 receives a valid copy of the requested block, it stores the received block in its cache 600 in the MODIFIED state and simultaneously converts the state of the block in the processor directory cache 650 into the DIRTY state. , The corresponding write operation is performed.

In the embodiment of the present invention, the case in which the system modules 300 and 300 'are composed of the local memory modules 100 and 100' and the local processor modules 200 and 200 'has been described. However, the present invention is different from the system modules 300 and 300'. Scheme, for example, when some of the system modules include only memory modules, i.e., local memory modules, as shown in FIG. 7, and some of the system modules, as shown in FIG. It should be understood that the same applies to the case of including only the local processor module.

In this case, a system module consisting only of local memory modules operates only as a shared memory module. Since a system module configured only with a local processor module does not include a local memory module, a processor directory cache is not needed, and if a cache failure occurs, in the above-described embodiments, a corresponding block is not stored in the local memory module. Yes.

FIG. 9 is a block diagram illustrating another example of a distributed shared memory multiprocessor using the improved write-invalidate cache system of the present invention, a system consisting of a local processor module and a local memory module and a system consisting of only a local processor module. A case where a system module composed of only modules and local memory modules is mixed is illustrated.

As described above, the novel write-invalidate cache system of the present invention alleviates the bottleneck of access to the shared bus in the distributed shared memory multiprocessor, and increases the processor's throughput per unit time and speeds up the memory due to the fast memory access. Can be planned. In addition, when a cache failure occurs, if the block is stored in its own local memory module and the state of the memory block is DIRTY, a cache-cache read request including a cache-cache read or invalidation request for the block. Can only be sent to other local processor modules (ie other local memory modules ignore the request), thus reducing unnecessary memory access conflicts.

Claims (15)

12. A distributed shared memory multiprocessor comprising a shared system bus and at least two system modules each having a local processor module and a local memory module coupled to the system bus, wherein the local processor module is contained within the local memory module. For each of the blocks that are included, further comprising a directory cache that holds information indicating whether the block is stored in a valid state within the local memory module. The local processor module of claim 1, wherein the local processor module has its own processor and a cache, and when the cache read failure for each block occurs, the state information in the directory cache is set to be valid in the local memory module. A distributed processor with shared memory accessing the block by directly communicating with the local memory module without indicating the need to use the system bus. The local processor module of claim 1, wherein the local processor module has its own processor and a cache, and when a cache write failure for each block occurs, status information in the directory cache is valid for each block in the local memory module. Distributed to access each block by communicating with the local memory module via the system bus to transmit an invalidation request for each block to the other local processor modules in the at least two system modules. Multiple processors with shared memory. The local processor module of claim 1, wherein the local processor module has its own processor and a cache, and when a cache read or write failure for each block occurs, status information in the directory cache is stored in the local memory module. Indicates that it is stored in a valid state, the multiple having distributed shared memory accessing each block by communicating with other processor modules in the at least two system modules via the system bus without communicating with the local memory module. Processor. 5. The method according to any one of claims 2 and 4, wherein the state information in the directory cache implies an invalidation request or invalidation for each block from the one processor module in the at least two system modules via the system bus. And, upon receiving a broadcast read request, having distributed shared memory indicating that each block is not stored in a valid state within the local memory module. 2. The local processor module of claim 1, wherein the local processor module has its own processor and cache, and when a cache read failure or a cache write failure occurs in each of its own caches, one block in the own cache has to be replaced. Distributed shared memory which evicts the block to be replaced to the local memory module without using the system bus when the block to be stored is stored in the updated state in the own cache and belongs to the area of the local memory module With multiple processors. 7. The multiprocessor of claim 6, wherein the state information in the directory cache indicates that the evicted block is stored in a valid state in the local memory module. 2. The local processor module of claim 1, wherein the local processor module has its own processor and cache and should be replaced when a cache read failure or cache write failure occurs in the own cache so that a block within the own cache has to be replaced. If a block is stored in an updated state in its own cache and does not belong to the area of the local memory module, the block to be replaced is transferred to another local memory module in the at least two system modules using the system bus. Multiple processors with distributed shared memory to evict. 2. The system of claim 1, wherein status information in a directory cache in a local processor module associated with the other local memory module in the at least two system modules indicates that the evicted block is stored in a valid state within the other local memory module. Multiple processors with distributed shared memory. The multiprocessor of claim 1, wherein the processor has a distributed shared memory including an internal cache. 2. The multiple processor of claim 1, wherein each local processor module has a distributed shared memory comprising a predetermined number of hierarchical caches. The multiprocessor of claim 1, wherein some of the at least two system modules have distributed shared memory comprising only local memory modules. The multiprocessor of claim 1, wherein some of the at least two system modules comprise distributed shared memory that includes only local processor modules. The multiprocessor of claim 1, wherein some of the at least two system modules include only local memory modules and other portions of the at least two system modules include only local processor modules. 2. The multiprocessor of claim 1 wherein the at least one system module comprises distributed shared memory comprising only a local memory module consisting solely of a processor and a cache.