JPH04134856A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a margin between a contact and a cell plate bar opening a contact of a data line without patterning a cell plate and by forming the cell plate by self-alignment. CONSTITUTION:After an insulating film 10 of a capacitor is formed, a cell plate 11 is formed and impurities are diffused. After an oxide film 12 is formed, a photo resist 13 is applied and a contact 14 of a data line is opened. Thereafter, the cell plate 11 is etched isotropically and a recess 15 is formed. The contact 14 is etched again to form a contact 16. Thereafter, heat oxidation is carried out to form an oxide film 17. When it is etched anisotropically, a contact hole is formed while leaving the oxide film 17, and the cell plate is also insulated from a contact part by self-alignment. Thereafter, a data line 18 is formed. Thereby, it is possible to form a space between a contact and the cell plate by self-alignment and to reduce a margin therebetween.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention provides a method for forming a cell plate after forming a contact hole for a data line when manufacturing a DRAM memory cell, particularly a stacked memory cell. The present invention relates to a method of manufacturing a semiconductor device in which the space between the cell plate and the cell plate can be formed in a self-aligned manner.

(Prior Art) FIG. 2 is a cross-sectional view showing the structure of a conventional stacked memory cell. A method for manufacturing a stacked memory cell having such a structure includes forming a field oxide film 2 on a silicon substrate 1, a gate oxide film 3, and a gate electrode 4 made of polysilicon or polycide.

Thereafter, a side wall 5 of an oxide film is formed and ions are implanted to form a transfer gate of a memory cell with 0 or more layers forming a source/drain region 6.

Further, an oxide film 7 is formed by CVD, and a capacitor contact 8 is formed by photolithography/etching.

Thereafter, polysilicon is grown, impurities are diffused by ion implantation or phosphorous diffusion, and storage electrode 9 is formed by photolithography/etching.

After that, a nitride film that will become the capacitor insulating film 10 is grown,
Polysilicon is grown again, impurities are diffused, and cell plate 11 is formed by photolithography/etching.

Next, an insulating film of oxide film 12 is formed by CVD, and contacts 13a for data lines are formed by photolithography/etching. Thereafter, a data line 14a is formed using polysilicon/polycide or the like, thereby forming a stacked memory cell.

(Problem B to be Solved by the Invention) However, according to the conventional stacked memory cell manufacturing method described above, the contact 13a of the data line 1.4a is opened to the cell plate formed by photolithography/etching. There was a problem in that it was necessary to provide an alignment margin (shown by a in FIG. 2) between the contact and the cell plate during photolithography in order to form the holes.

The present invention provides a method for manufacturing a semiconductor device that solves the problem of the above-mentioned prior art, that an alignment margin is required between the data line contact and the cell plate.

(Problem W1 to be Solved by the Invention) In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device in which data line contacts are opened without patterning the cell plate 1, and then the cell plate is removed. This method introduces a process of forming using Selfa Line.

(Function) According to the present invention, since the above steps are introduced in the method for manufacturing a semiconductor device, by forming a cell plate after forming a contact hole for a data line, a self-alignment line is formed between the contact and the cell plate. Therefore, the margin between the contact and the cell plate can be reduced, and the above-mentioned problem can therefore be eliminated.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
6) is a process sectional view for explaining one example. In FIGS. 1(a) to 1(80), the same parts as those in FIG. 2 will be described with the same reference numerals.

First, as shown in FIG. 1(a), field oxidation 112 is applied to the silicon substrate 1 by selective oxidation at a temperature of 2000 to 2000.
It grows to a thickness of about 8,000 people.

After this, a gate oxide film 3 is grown to a thickness of about 50 to 300 layers using a thermal oxidation method.Next, a polysilicon film is grown to a thickness of about 500 to 5000 layers using an LPCVD method.
After impurities are diffused by ion implantation or phosphorus diffusion, the gate electrode 4 is formed.

Further, in this case, the sidewall 5 is formed by growing an oxide film of about 1,000 to 8,000 layers using a zero-order CVD method, which may be a polycide such as WSiz, and performing etching.

Next, in the case of N channel by ion implantation, As or P
In the case of P channel, B or BFI is 1 to 10 x 1
0.015 (c1-'') is implanted to form a diffusion layer 6. In this way, the isolation region and transfer gate of the memory cell are formed as shown in FIG. 1(a).

Next, as shown in FIG. 1(g), an oxide film 7 of about 1,000 to 10,000 layers is grown using the CVD method, and a hole for a capacitor contact 8 is formed in this oxide film 7 using a photo-growth/etching method. Next, approximately 500 to 5,000 polysilicon layers are grown using the LPCVD method, impurities are diffused using the growth implantation method or the phosphorous diffusion method, and then the storage electrode 9 is formed by photolithography/etching.

Next, SiN, which will become the insulating film 10 of the capacitor, is coated with LPCV.
After growing by about 30 to 100 λ using the D method, 1000 to 3000 cells of the cell plate 11 of Borin Recon are grown, and impurities are diffused using the ion implantation method or the phosphorus diffusion method.

Next, the oxide film 12 is formed to a thickness of 3,000 to 100 by CVD.
It grows to about 0.00 people, and when it flattens out due to thermal growth, the first
The result will be as shown in figure (b).

After that, as shown in FIG. 1(c), the photoresist 13
After coating the data line contacts 14, photolithography/
An anisotropic contact as shown in FIG. 1(d) can be formed by using a six-step RIE method or the like in which holes are opened by an etching method.

Here, since the cell plate is made of polysilicon or the like, it is convenient to finish the etching at this portion. Thereafter, the cell plate 11 is isotropically etched by plasma etching. When the cell plate 11 is isotropically etched, recesses 15 for data line contacts 14 are formed as shown in FIG. 1(d).

The data line contact 14 is anisotropically etched again by RIE or the like and the photoresist 13 is removed, thereby forming the data line contact 16 as shown in FIG. 1(e).

After that, thermal oxidation is performed at 900°C in a 0□ atmosphere for about 30 minutes, so that the bottom of the data line contact 16 and the cell plate 11 have a 20% oxide film 17 as shown in FIG. 1(f).
When the growth layer, which has grown from 0 to 1000 layers, is anisotropically etched again using the RIE method, a contact hole is formed while leaving the oxide film 17 grown on the cell plate 11, and the cell plate is also contacted like a cell line. isolated from other parts.

After this, about 1,000 to 4,000 polysilicon or polycide are grown using the LPCVD method (Figure 1).
), data lines 18 are formed and the device is completed.

In this way, by forming the cell plate at the same time as forming the data line contact hole, the space between the contact and the cell plate can be formed in a self-aligned manner, and as shown in Table 1 below, the margin can be reduced. can.

<Table 1> Table 1 compares the margins for design rules (typical devices), and according to the present invention, it is possible to reduce the margins regardless of the design rules.

(Effects of the Invention) As described above in detail, according to the manufacturing method of the present invention, the cell plate is formed after contact holes for the data line are formed, so that the space between the contact and the cell plate is similar to that of a cell line. This margin can be reduced.

In addition, the manufacturing process can be simplified since the photolithography process when forming the cell plate is not required.

[Brief explanation of the drawing]

1(a) to 1(80 is a process cross-sectional view of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 2 is a cross-sectional view showing the structure of a conventional stacked memory cell. 1 ...Silicon substrate, 2...Field oxide film, 3
... Gate oxide film, 4-gate gate electrode, 5... Side wall, 6... Diffusion layer, 7.12.17... Oxide film, 8... Capacitor contact, 9... Storage electrode , 10... Capacitor insulating film, 11... Cell plate, 13... Photoresist, 14.16...
Contact of data line, 15... Recess of contact, 18... Data line. The main θth knee! 1-cut 0-cut main cleaning process '1 AIT surface drawing Figure 1

Claims (1)

[Scope of Claims] (a) After forming a gate electrode on a semiconductor substrate via a gate oxide film, forming a sidewall on this gate electrode and forming a diffusion layer on the semiconductor substrate, a memory cell is formed. (b) forming an oxide film and forming a storage electrode after opening a capacitor contact, and sequentially forming an insulating film and a cell plate of the capacitor; (c) After forming an oxide film on the cell plate, applying photoresist and forming data line contacts by photoetching, and isotropically etching the cell plate; (2) heating after removing the photoresist; After performing oxidation to grow an oxide film on the bottom of the contact of the data line and the cell plate, anisotropic etching is performed to form the contact of the data line. A method of manufacturing a semiconductor device, comprising: a step of insulating the cell plate from the contact;