JPH04134268A - Trigger circuit - Google Patents

Abstract

PURPOSE:To accomplish a trigger circuit having a function to continue the waveform display even after launching into the condition where the complicated trigger conditions are not fully met, by decreasing the reqisite number of trigger demand signals when trigger remains out of generation because a plurality of trigger demand signals are not met within a specified time-out limit. CONSTITUTION:Input signals are converted into digital data by an AD converter 11 and written one after another in a memory 12 in a row, and the data previously written according to the flow of input signals is pushed out one by one. A trigger sensing circuit 13 senses whether the input signal has passed the level set previously, and at this point of time eventually the trigger is emitted. It shall be capable of writing 1000 words in the memory 12, and if writing is stopped where 800 word data is entered after trigger was input, so the trigger was entered at the point with 200th word reckoned from the beginning of the memory 12. Therein an acquisition end signal rq shall be issued at the point with 800th word reckoned from the trigger entering.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in trigger circuits used in digital oscilloscopes and logic analyzers.

(Prior art) The auto trigger mode conventionally used in analog oscilloscopes uses a trigger to generate a synchronization signal and displays waveforms, but even if the trigger is no longer present, the waveforms are forced to display on timeout. Therefore, some kind of waveform display continues.

FIG. 5 shows a state transition diagram of auto trigger mode operation.

In the figure, W is in a standby state in which a trigger is input and a waveform is displayed, waiting for its completion. STI is displaying the waveform in the W state, and when the waveform display is finished,
This is a state that is transitioned from W, and if a timeout time is set in this state and a trigger does not occur within the timeout time, the state moves to STO. ST
When the state shifts to O, a trigger is forcibly generated and the state shifts to W.

(Problem to be Solved by the Invention) By the way, in a digital oscilloscope or logic analyzer, for example, if the voltage level exceeds the voltage level after passing through a parallel pattern trigger or multiple gates expressed as a multi-bit binary number. If you set a trigger to be output based on multiple AND conditions, such as a multi-gate trigger that outputs a trigger, the waveform display will disappear if all conditions are not met, especially in the case of a multi-gate trigger. In some cases, it becomes difficult to set the position of the cage, that is, the trigger force conditions.

The present invention has been made in view of the above points, and its purpose is to display waveforms in digital waveform storage devices such as digital oscilloscopes and logic analyzers even when all complex input conditions are not satisfied. The object of the present invention is to realize a tri-power circuit that has a continuous function.

(Means for Solving the Problems) The present invention for solving the above problems provides a logic circuit group into which a plurality of trigger request signals are input and the number of trigger force requirement condition inputs for generating a trigger force is determined by a selection signal. , a D flip-flop that outputs a trigger signal when the output of the logic circuit group is input to the clock terminal or a preset signal is input to the preset terminal, and a D flip-flop that starts with the start signal or trigger signal input and measures time. an acquisition end signal input terminal, an input terminal to which the timeout signal from the timer is input, and a selection signal output terminal to output a selection signal to the logic circuit group. , an enable signal output terminal that outputs an enable signal to the D flip-flop, a preset signal output terminal that outputs a preset signal, a reset signal output terminal that outputs a reset signal, and a start signal output that outputs a start signal to the timer. and a controller having a terminal.

(Function) In the trigger wait state where a trigger is generated when multiple trigger request signals are input, if a trigger is not generated because multiple trigger request signals are not satisfied within the timeout period, the required number of trigger request signals is reduced. If a trigger occurs at each stage, the system waits for the acquisition to end.
The acquisition end signal waits for a trigger request signal based on the previous trigger wait condition. If the trigger does not occur, the trigger will be generated unconditionally in the end.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is an AND gate to which the first tri-power request signal sig#1 is input to one terminal, and the output of the OR gate 2 is input to the other terminal. The second tri-force request signal sig#2 is input to one terminal of the OR gate 2, and the selection signal sep is input to the other terminal. Selection signal 5eJ
7 or 1, "1" is input to one terminal of the AND gate 1 regardless of whether or not the second trigger request signal sig#2 is input, and when the selection signal sep is 0, the second trigger request signal sig#2 is input. i g#2 is input to the ANDKATE 1 terminal. 3 is an input terminal for receiving an acquisition end signal rq.
It has an RQ terminal to which the signal is input, a TOUT terminal to which the timeout signal Of is input, and a selection signal 5e as an output terminal.
SEL terminal to which fl is output, PR terminal to which preset pulse i is output.

ENB terminal to which enable signal enb is output RES terminal start pulse s to which reset pulse res is output
The controller is equipped with an output/output terminal STO that outputs a start signal.

4 is a D flip-flop having a preset terminal PR and a center terminal RES, which outputs an enable signal enb inputted to the D terminal by a clock input as a tri-power signal trg to the acquisition system; The trigger signal trg is output unconditionally by the preset pulse I. 5 is the start pulse s
When t is input to the start signal input terminal STI from the controller 3, it is set to 0 and starts measuring time.
When a preset time elapses, a timeout signal o
When f becomes 1 and the timer outputs from the timeout signal output terminal OF, the timer 5 is set to 0 when the trigger signal trg or the trigger signal trg is input to the TRG terminal. When the timer 5 is set to 0, the timeout signal Of also becomes 0.

Next, the operation of the embodiment configured as described above will be explained. First, the background of the operation to be performed in this embodiment will be explained. FIG. 2 is an explanatory diagram showing the relationship between the input force and the output data in the digital oscilloscope. The input signal is converted into digital data by the AD converter 11, and sequentially written in one column in the memory 12, and the previously written data is sequentially pushed out according to the flow of the input signal.

On the other hand, the tri-force detection circuit 13 detects whether the input signal exceeds a preset level and outputs a tri-force at that point. Assume that 1,000 words are written to the memory 12, and after a trigger is input, if writing is stopped when 800 words of data have been written, the trigger will have been input at a point 200 words from the beginning of the memory 12.

In this case, the acquisition end signal rq is output at 800 words after the trigger is input. FIG. 3 is a state transition diagram of the operation of the apparatus implemented in this embodiment. In the figure, Sr1 has a plurality of trigger signal inputs, for example, two first trigger request signals sig#1. When the second trigger request signal sig#2 is input within a preset timeout period, the trigger is in a state where it generates the signal trg.

When the trigger signal trg is output, the waveform is displayed and the state shifts to state W2. After the acquisition ends in state W2, that is, when the acquisition end signal rq is input,
Return to Sr1. When the trigger signal trg is not generated within the timeout period in Sr1, the state shifts to state STI. S
TI is in a state where it generates the tri-force signal trg only in response to the first tri-force request signal sig#1. If the trigger signal trg is generated before the timeout signal Of is generated, the process returns to W2. If the trigger signal trg is not generated within the timeout period, a transition is made to the state STO. STO receives the first and second trigger request signals sig#1. This is a state in which the trigger signal trg is unconditionally generated even if sig #2 is not input, and the state shifts to state W1. State W1 waits for an acquisition end signal rq and then shifts to state ST1. If the trigger signal trg is generated within the timeout period, the process moves to state W2 and waits for the end of acquisition, and returns to state ST2 when the acquisition ends. The circuit of this embodiment is for executing the above state transition.

Next, the operation of the embodiment will be explained with reference to time chart I in FIG. When the device is powered on, the device will
The state becomes r1. In Sr1, the output of the controller 3 is the selection signal se, l) or 0, and the enable signal enb is also 0.
1. Therefore, the input signal at the D terminal of the D flip-flop 4 is 0. After that, a start pulse st is generated, the enable signal enb is set to 1, and the D flip-flop 4
Set the D terminal to 1 and enter the state of waiting for a power supply. Since the selection signals se and Q are 0, the OR gate 2 receives the second trigger signal s.
When ig#2 is input, it outputs 1, and the AND gate 1 outputs the output from the D flip-flop 4 according to the AND condition of the second trigger request signal sig#2 and the first trigger request signal sig#1. input to the clock pin as the clock. D when a clock is input to the clock terminal
Terminal 1 is output to the Q terminal, and signal trg is output from the terminal. trg in FIG. 4 is a rectangular pulse, but only its rising waveform acts as a trigger. Tori is signal trg
When is output, the state becomes W2 in FIGS. 3 and 4.

Here, when the acquisition end signal rq is input,
The state becomes ST2. When the state of ST2 is reached, the controller 3 first sets the signal qenb to O, outputs the O-level reset pulse res, and resets the D flip-flop 4. Thereafter, a start pulse st is generated, the enable signal enb is set to 1, and D of the D flip-flop 4 is set to 1. Selection signal s (9 is 0, so the first
．． A trigger wait state is entered by both the second trigger request signal sig#151g#2.

Also, the start pulse st is input to the timer 5 and becomes 0, and time measurement begins. The first one within a predetermined time measured by the timer 5. Second trigger request signal sig#
1. When sig #2 is input and a clock is input from AND gate 1 to the D flip-flop, D is transferred to Q and a trigger signal trg is output. The trigger signal trg sets the timer 5 to 0 and starts time measurement again. If the first trigger request signal sig#1 and the second trigger request signal sig#2 are not input within the timeout period and the trigger signal trg is not generated, the timer 5 outputs the timeout signal o.
f is output to the T OUT terminal r of the controller 3, and S
Enters state T1. When the STI state is reached, the controller 3 sets the enable signal er+b to 0, and accordingly sets the selection signal sel to 1, sets the input of one terminal of the OR gate 2 to 1, inputs 1 to one terminal of the Antoket, and waits for a trigger. The condition is only the first trigger signal sig#. Furthermore, a reset pulse res is output, and the D flip-flop 4
Reset the D terminal to 0. Next, a start pulse st is output and the timer 5 is set to 0. The timeout signal of becomes 0. Also, by outputting the start pulse st, the enable signal enb is set to 1 and D
D of the flip-flop 4 is set to 1 to enter a state of waiting for a clock by inputting the first trigger request signal sig#1. The timer 5 starts measuring time, and when the time is appropriate and a timeout signal Of is input to the TOUT terminal of the controller 3, the controller 3 enters the STO state.

When the STO state is reached, the controller 3 sets the enable signal enb to O, outputs the reset pulse rei, resets the D flip-flop 4, and sets the D terminal input to 0. Next, a start pulse St is generated, the enable signal enb is set to 1, the timer 5 is set to 0, and the timeout signal Of is set to 0. After that, a preset pulse I is output. When the preset pulse is input, the D flip-flop 4 forcibly outputs 1 from the Q terminal regardless of the presence or absence of the clock pulse, and the trigger pulse trg is output, resulting in the state of Wl. Trigger pulse trg is timer 5
When input to the TRG terminal of the timer, the timer is set to 0. Further, in state W1, the device is in a state of waiting for an acquisition end signal rq. When the acquisition end signal rq is input, the state shifts to ST1.

Here, the controller 3 first sets the enable signal enb to O, outputs the reset pulse res, and resets the D flip-flop 4. Then, the start signal st
is output, and the enable signal enb is set to 1. The start signal st sets the timeout signal of to 0 and sets the timer 5 to 0. Since the selection signal sep remains in the state of 1, the trigger input signal waits only for the first trigger request signal sig#. 1st within the timeout period
When the trigger force request signal sig#1 is input, a trigger signal trg is output from the Q@ terminal of the D flip-flop 4.
Move to state W2.

As explained above, according to this embodiment, when multiple trigger conditions are set, if multiple trigger conditions are not satisfied within a certain time, the conditions are relaxed one after another and the waveform display is performed. This makes the settings easier.

Note that the present invention is not limited to the above embodiments. In the above embodiment, an example of a two-channel parallel pattern trigger is shown, but the same can be realized by adding more states to a parallel pattern of three or more channels.

(Effects of the Invention) As described in detail above, according to the present invention, it is possible to continue displaying waveforms even when a complex bird enters a state where all conditions are not satisfied, and it has practical effects. is big.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between the trigger force and output data from the memory, FIG. 3 is a state transition diagram of the embodiment of FIG. 1, and FIG. The figure is a time chart of the operation of the embodiment, and FIG. 5 is a state transition diagram of a conventional circuit. 1...anchor gate 2...or gate 3...controller 4...D flip-flop 5...timer enb...enable signal of...timeout signal pr...preset signal res...reset signal st ...Start signal 5e (1...Selection signal r
q... Acquisition end signal Time out signal

Claims (1)

[Claims] A plurality of trigger request signals are input, and a selection signal (sel) is input.
A logic circuit group (1, 2) whose number of trigger requirement inputs for generating a trigger is determined by A D flip-flop (4) that outputs a trigger signal (trg) when @) is input to the preset terminal, and a D flip-flop (4) that outputs a trigger signal (trg) when the start signal (st) or trigger signal (trg) is input. a timer (5) that outputs a timeout signal (of) after the elapse of time; an acquisition end signal input terminal (RQ); an input terminal (TOUT) to which the timeout signal (of) from the timer (5) is input; A selection signal output terminal (SE) outputs a selection signal (sel) to the logic circuit group (1, 2).
L) and an enable signal output terminal (ENB) that outputs an enable signal (enb) to the D flip-flop (4).
B), a preset signal output terminal (PR) that outputs a preset signal (@pr@), and a reset signal (@res
A controller (3) having a reset signal output terminal (RES) that outputs @) and a start signal output terminal (STO) that outputs a start signal (st) to the timer (5).
A trigger circuit comprising: