JPH04132243A - Semiconductor integrated circuit device and its type expansion method - Google Patents

Abstract

PURPOSE:To make it possible to carry out type expansion of a semiconductor integrated circuit device in accordance with performance or the like of the semiconductor chip of the device by putting a visually identifiable mark to the chip on the semiconductor wafer of the device when writing a non-volatile memory for defect remedy or function change. CONSTITUTION:The EPROM for defect remedy comprises an address buffer ADX, memory array consisting of non-volatile memory element, and output buffer DOX, and the writing circuit of memory array E-ROM, various control circuits, or address conversion circuit are contained an address buffer ADX and output buffer DOX. Further, in order to make it possible to visually identify the semiconductor device when carrying out defect remedy using the EPROM, a fuse F is used. Or, an attempt is made to apply a relatively large current in to the fuse F from high voltage Vpp to make the current flow in the fuse F to blow it. Then, to the gate of switch transistor TSW, a write control signal WE is supplied.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device and its product development system, and relates to a semiconductor integrated circuit device that uses non-volatile memory for defect relief or function modification, for example. It is about effective techniques.

[Conventional technology]

Volatile memory devices such as dynamic RAM (random access memory) and static RAM, or EPROM to which data can be written electrically
(Erasable and programmable REIT only)
In non-volatile memories such as memory devices, a fuse made of the same layer as the gate electrode is used to repair defective bits. This defect relief technique involves cutting the fuse by energizing it or irradiating it with an energy beam, and converting the address of the defective focus to a spare memory. Furthermore, an example has been announced in which the above-mentioned fuse is used to repair defects in mask ROMs into which data is written during the manufacturing process. Regarding such defect remediation techniques, for example, I. Nis.C., Technical Digest, 1989, pp. 128-129 (ISSCCT
electrical digest 1989, pp.
128-129).

Additionally, U.S. Patent No.
, No. 393, 474, which describes EPROM defect relief.
There is Japanese Patent Laid-Open No. 58-56469 regarding a defective technique using FROM.

[Problem to be solved by the invention]

Conventional defect relief techniques are discussed from the viewpoint that it is sufficient to simply relieve defects. When a defect is repaired, memory access becomes slow because the defective bit address is switched to a spare memory. Furthermore, when defect relief is performed using an EPROM, the data retention characteristics of the EPROM are temperature dependent, so if the EPROM is used at high temperatures, the data for defect relief will be erased and a defect will occur. Therefore, the operating temperature range of devices that have undergone defect relief becomes narrower.

In semiconductor integrated circuit devices with conventional defect relief technology, the performance of the product is determined based on the worst case scenario in which a defective bit occurs. The product will be shipped as a product that is less than capable in terms of memory access, operating temperature range, etc. Therefore, the inventors of the present application,
Focusing on the above-mentioned difference in performance between products that use programmable ROM for defect relief or function changes and products that do not, we considered developing product types based on each performance. In this case, in the case of defect relief using fuses, it is possible to determine from the appearance whether or not the fuse is broken, so we considered utilizing this fact. However, when an EPROM is used for defect relief or function change, it is not possible to tell from the outside whether defect relief or function change has occurred, so we came up with the idea of attaching an identification mark.

An object of the present invention is to provide a semiconductor integrated circuit device having an additional function of identifying whether or not an EFROM is used.

Another object of the present invention is to provide a system for expanding the types of semiconductor integrated circuit devices, which makes it possible to expand the types according to the performance, etc. of semiconductor integrated circuit devices incorporating a programmable ROM.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, when writing is performed on a non-volatile memory for defect relief or function modification, a mark that can be visually identified is attached to a chip on a semiconductor wafer. Furthermore, by identifying such marks, chips formed from the same semiconductor wafer can be assembled as semiconductor integrated circuit devices of different types.

[For production]

With the identification mark, it is possible to easily identify whether or not writing has been performed on the nonvolatile memory, and based on this, it is possible to develop product types according to the performance of the semiconductor chip.

[Embodiment] FIG. 1 shows a block diagram of an embodiment of a mask ROM to which the present invention is applied.

In this embodiment, EP is used to repair defects in the mask ROM.
ROM is used. In mask ROM defect relief, the defective address is switched to the spare memory, and
It is convenient to use an EPROM because it is necessary to write data at a defective address into a spare memory.

The mask ROM includes an address terminal A1-Am, an address buffer ADB, an address decoder DCR (the address buffer ADB and the address decoder DCR are shown as the same block in the figure), and a memory array M-R.
It is composed of OM, an output buffer DOB, and output terminals D1 to Dn.

In this embodiment, since the sense amplifier and various control circuits are not directly related to the present invention, the above-mentioned output sofa D
Please understand that it is included in OB.

In the figure, each circuit block constituting the EPROM surrounded by a dashed line is used as a defect relief circuit. EPROM for defect relief uses address buffer ADX.
, a memory array E-R composed of nonvolatile memory elements.
It consists of OM and outcover sofa DOX. The write circuit of the memory array E-ROM, various control circuits, or address conversion circuits are included in the address buffer ABX and output sofa DOX.

In this embodiment, a fuse F is used to enable visual identification when defect repair is performed using the EPROM as described above.

That is, the fuse F is disconnected by allowing a relatively large current from the high voltage V1) to flow through the switch transistor (insulated gate field effect transistor) TSW. The above switch transistor TSW
A write control signal WE is supplied to the gate of .

If a defect occurs in a part of the mask ROM, an address and data corresponding to the defect are written into the repair EFROM. That is, the address buffer A of the mask ROM
The address to be repaired via DH is EPR for defect repair.
It is transmitted to the address buffer ABX of OM. This address buffer ABX stores the relief address using the high voltage VpI) and the write control signal WE. Also,
The memory array E-ROM corresponding to the rescue address is selected, and the data input from the output terminals D1 to Dn is taken in through the output buffers DOB and DOX of the mask ROM and EPROM, and written into the selected memory cell. Therefore, the above outputs, 7hua DOB and DO
X is controlled by the control signals Vl)I) and WE as described above.
Captures signals from external terminals. Therefore, the above-described output sofas DOB and DOX operate as two-way sofas, outputting signals during normal read operations, and capturing input data during write operations for defect relief.

During the write operation as described above, the write control signal WE is kept at a low level. Therefore, since the switch transistor TSW remains off, no current from the high voltage ρp flows through the identification fuse F. Then, at the end of the write operation as described above, the control signal WE is set to a high level, the switch transistor TSW is turned on, and a relatively large current flows from the high voltage vpp. As a result, fuse F is cut. Wait for the fuse F to disconnect as described above, and then turn on the high voltage vp.
p is set to a low level like the ground potential of the circuit.

Due to the cutting of the fuse F as described above, a trace that can be visually identified due to the cutting of the fuse F is generated in a chip constituting the mask ROM as described above formed on a semi-integrated wafer.

On the other hand, in a chip in which no defects occur on the mask ROM side, the fuse F is not cut off even if the control signal WE is at a high level because the high voltage Vl)l) as described above is not supplied. This prevents the cutting traces described above from occurring.

In this embodiment, both ends of the fuse F are set at the ground potential of the same circuit after being disconnected or in the normal state as described above. Therefore, even if the fuse F is partially cut off, current will not constantly flow.

Therefore, the fuse F does not need to be completely electrically disconnected, as long as traces of the disconnection can be discerned visually. Therefore, when using the fuse F for visual identification as described above, it is easier to set the conditions compared to when the fuse F is completely disconnected, such as when using the fuse F as a programmable ROM.
There is no problem even if the upper part is covered with an insulating film.

In the above embodiment, when the high voltage vpp is set to the power supply voltage Vcc such as about 5 V in the normal state, the ground potential side of the fuse F may be switched to the power supply voltage Vcc side. After cutting this fuse F, set the high voltage terminal vpp to the power supply voltage Vcc or ground potential,
The control voltage supplied to the gate may be switched so that the switch transistor TSW is in the off state in a normal state in which the write control signal WE is at a high level. In other words, a control signal may be generated that temporarily turns on the switch transistor TSW when the fuse is cut. Further, in the above embodiment, the fuse means is disconnected when writing is performed on the EFROM, but conversely, when writing is not performed on the EPROM, in other words, when no defective bits occur in the mask ROM. The fuse means may be disconnected.

FIG. 2 shows a circuit diagram of another embodiment of the fuse circuit for performing the above-mentioned external identification.

In this embodiment, it is possible to identify not only whether a defect has been repaired but also the position of a repaired defective word line, defective data line, or both. That is, when repairing only a word line, a fuse necessary to indicate the position of the word line is prepared. For example, if 10 fuses are prepared, 1024 word lines can be specified. When repairing only the data line, prepare the necessary number of fuses to indicate the position of the data line. To rescue both the word line and data line, prepare a fuse that combines them.

In this embodiment, m fuses F1 to Fm are provided,
One of each of the fuses F1 to Fm is connected to a ground potential point, and the other is connected to a switch transistor TSWI to TS.
A high voltage Vl)I) is supplied via Wm. The gates of the switch transistors TSWI to TSWm are connected to a high voltage Vpρ, a write control signal WE, and an address terminal A1.
~Am is supplied with a control signal formed by a control circuit C0NT. The control circuit C0NT has a high voltage Vpp
When the address terminal A is set to a high voltage for writing and the write signal WE is set to a low level to instruct writing, the address terminal A
Each of the switch transistors TSWI to TSWm is controlled to be in an on state in response to an address signal supplied from 1 to Am. As a result, address signals A1 to Am
fuse F in response to the defective address specified by
l-Fm is cut. As a result, fuses F1 to F
2. Set the fuse with a cut trace among the m fuses consisting of m to logic "1". It is possible to identify a defective address by associating a fuse with no trace of disconnection with a logic "0".

After the fuse is selectively disconnected as described above, the control circuit C0NT switches the switch transistors TSW1 to TSWm.
to the off state. As a result, under normal conditions, when the high voltage terminal vpp is set to the power supply voltage VCC, a steady current will not flow through the fuse circuit even if fuses that should be cut are not completely cut or there are fuses that are not cut. .

3A to 3D show cross-sectional views of a manufacturing process of an embodiment for explaining a method of manufacturing a semiconductor integrated circuit device according to the present invention. Note that in this specification, MOSFET is an insulated gate field effect transistor (
IGFET).

In FIGS. 3A to 3D, from the left side, a nonvolatile memory element QE with a single-layer polysilicon gate structure, an N-channel MO5FET QN as a switch transistor, and a fuse F are shown.

In addition to selectively disconnecting the fuse F, the N-channel MOSFET QN is also used for peripheral circuits such as the address selection circuit of the nonvolatile memory element QE, and for warping of a mask ROM formed on the same semiconductor substrate as the EPROM according to the present invention. Used to construct circuits and digital circuits. Also,
The cross-sectional view of the nonvolatile memory element QE is shown with the left side in the vertical direction and the right side in the parallel direction with respect to the source and drain.

In FIG. 1A, a P° type well 2 and an N type well 102 are formed on the negative surface of a P type semiconductor substrate 1 by known means. Next, a thick field insulating film 3 and a P-channel stripper 4 shown by dotted lines in the figure are formed under the thick field insulating film 3 by known means.

In FIG. 3B, an N-type diffusion layer 6 is formed to serve as a control gate of the nonvolatile memory element QE. This N
Although not particularly limited, the type diffusion layer 6 is formed by injecting phosphorus into nitrogen through the insulating film 5 to an extent of 1 x 10100 m-'' at an acceleration energy of 80 Kev, and then injecting phosphorus into nitrogen through the insulating film 5 by ion implantation.
It is formed by heat treatment at a temperature of 950° C. for about 30 minutes in an atmosphere containing oxygen of about 30%. Of course, only arsenic or both arsenic and phosphorus may be used as impurities. Furthermore, although it is basically not necessary to perform heat treatment, it is better to perform the above-described heat treatment to recover damage from semiconductor substrate 1 that has been damaged by ion implantation.

Next, the insulating film 5 damaged by the ion implantation is
After the gate insulating film 7 is removed, a clean gate insulating film 7 is formed by thermal oxidation.
is formed. At this time, the thickness of the gate insulating film 7 above the N-type diffusion layer 6 is as follows compared to the region without the N-type diffusion layer 6.
■It is formed about 20% thicker.

Then, a conductive layer 8 that becomes a conductive layer for the floating gate of the nonvolatile memory element QE, the gate electrode of the N-channel MOSFET QN, and the fuse F is formed. This conductive layer 8 is composed of a polycrystalline silicon film or a polycide film in which a silicide film is laminated on top of a polycrystalline silicon film.

As shown in FIG. 3C, N-type diffusion layers 9 and 10 and a P-type diffusion layer (not shown) are formed. The N-type diffusion layer 9 is formed by ion implantation, in which phosphorus is irradiated with 2
It is formed by implanting about 10" am-2. The N-type diffusion layer IO is formed by implanting phosphorus at about 5X IQ ISam-2 at an acceleration energy of 50 Kev using the ion implantation method. Not shown. The P-type diffusion layer is made by ion implantation, so that boron has an acceleration energy of 15
It is formed by implanting about 1X10''C1i -2 with Kev.

Next, after a CVD insulating film is formed on the entire surface, sidewalls 11 are formed by anisotropic etching. Then, an N-type diffusion layer 12 and a P-type diffusion layer (not shown) are formed. The N-type diffusion layer 12 is formed by implanting arsenic in an amount of approximately 5×10 ``cx-'' at an acceleration energy of 80 KeV using an ion implantation method. Boron is accelerated at an energy of 15K using a P-type diffusion layer ion implantation method (not shown).
It is formed by implanting approximately 2×IQ15an−” in ev.

In this embodiment, the N-type diffusion layer 1o is described as being formed before the sidewall 11 is formed, but it may be formed after the sidewall 11 is formed.

In FIG. 3D, nonvolatile memory element QE has control gates connected to diffusion layers 6 and 10. floating gate 8
, a gate insulating film 7, a glabellar insulating film 7 between the control gate and the floating gate, and a one-layer gate structure including an N-type diffusion layer 1o for the source and drain.

The reason why the source and drain are formed by the N-type diffusion layer IO is to improve the write characteristics. The N-type diffusion layer IO has the same structure as the source and drain of the N-channel MO3FETQN. N-channel MO3FETQN
has a so-called LDD structure in which the gate electrode 8, the gate insulating film 7, and the source and drain are composed of N-type diffusion layers 9 and 12. Although not shown, P channel MO
The 3FETQP is also made into a so-called LDD structure. Each element is separated by a field insulating film 3 and a P-type channel strainer 4. Each element has an insulating film 13
They are connected by wiring 15 made of aluminum through contact holes made in the . The N-type diffusion layer 6 and lO, which are the control gates of the nonvolatile element QE, are shunted by the wiring 15 to reduce parasitic resistance. That is, the wiring vA15 constitutes a word line and is connected to the control gate of each nonvolatile memory element. The N-type diffusion layer 10 is provided to make good ohmic contact with the wiring 15.

One end of the fuse F is supplied with a ground potential from the wiring, and the other is connected to the N-channel MO3FETQN as a switch transistor by the wiring I5. The surface thereof is covered with an insulating film 13.

In this embodiment, in order to improve the data retention characteristics of the non-volatile memory element QE having a single-layer gate structure as described above, an aluminum layer 15 covering the entire surface of the floating gate 8 with an insulating film 13 in between is used as a barrier layer. It is formed. The insulating film 13 is made of a PSG film or a BPSG film. Although not particularly limited, the aluminum layer 15 as a barrier layer formed to cover the entire surface of the floating gate via the insulating film 13 is integrally formed with the word line to which the control gate of the nonvolatile memory element QE is connected. configured.

When the nonvolatile memory element QE of this embodiment is used for repairing defects in a mask ROM as described below, the N-channel MO3FET QN has a structure similar to that of the memory element. However, in FIG. 3A, N-type impurities are introduced by ion implantation into the portion where the mask ROM is formed, and the N-channel MO5FET formed there is made into a depletion type.

When the EPROM thus formed on a semiconductor wafer is used for defect relief, the EPROM is
As the ROM is written, fuse F is cut off.

When each semiconductor chip is separated from the semiconductor wafer, it is possible to distinguish between those that use EPROM, or in other words, those that have undergone defect relief, and those that have not undergone defect relief, based on the traces of cutting of the fuse F. and then assembled. The memory cycle time is slow and the operating temperature range is E.
Considering PROM's data retention characteristics, it is shipped as a low-grade performance product that can be kept at a relatively low temperature. On the other hand, those that have not taken the above defect relief,
Short memory cycle time and EPR operating temperature range
It is shipped as a high-grade, high-performance product that can be used up to high temperatures that do not take into account the data retention characteristics of OM. In this way, different types of mask ROMs or semiconductor integrated circuit devices are sold depending on their performance, depending on the presence or absence of defect relief as described above, so users who are looking for them should check the usage conditions of each. It is possible to select a mask ROM with performance corresponding to the requirements.

For example, it is conceivable to electrically write the presence or absence of defect relief using an EPROM, but it is necessary to operate the completed semiconductor integrated circuit device and read out the presence or absence of defect relief one by one. On the other hand, by providing an externally distinguishable mark as described above, the above-mentioned devices and operations can be omitted, and semiconductor chips with different performances can be assembled separately.

The effects obtained from the above examples are as follows. In other words, (1) By attaching marks that can be visually identified to chips on a semiconductor wafer when writing is performed on non-volatile memory for defect relief or function modification, it is possible to easily separate the chips during assembly. This effect can be obtained.

(2) By using an electrically cut fuse means as the identification mark, it is possible to easily cut the fuse.

(3) By providing a plurality of the above-mentioned fuses and combining them, it is possible to visually identify a defective address.

(4) Programmable R for defect relief or functional change
When an OM is used, a mark that can be visually identified on the chip and board on a semiconductor wafer is attached, and by identifying this mark and assembling semiconductor integrated circuit devices of different types with different performances, it is possible to assemble them according to their performance. This has the effect of enabling rational product development.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above-mentioned Examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, when a fuse means is used as a programmable ROM such as a dynamic RAM, a static type RAM, or an EPROM to repair defects, the fuse means is used as a mark to identify the presence or absence of defect relief. It may be. In this case as well, it is only necessary to develop the types of high-performance memory with a fast memory cycle as described above and low-performance memory with a slow memory cycle. In addition to using a fuse, the above identification marks can be made by irradiating the surface with a high-energy beam or by pressing a probe onto a predetermined location on the semiconductor chip, making the mark visible (scratches).
You may also add .

In the above embodiment, the EPROM for defect relief is 1
Although we used a nonvolatile memory element with a layered gate structure, we also used a nonvolatile memory element with a two-layer gate structure, a FLOTOX (floating gate tunnel oxide) type, an MNOS type that uses a silicon nitride film and a silicon oxide film, etc. It can be anything.

The fuse means for defect relief and identification marks may be electrically cut or may be cut by irradiating a high energy beam such as a laser beam.

The programmable ROM including the fuse means may be used for changing functions in addition to repairing defects. In other words, the function may be changed by changing/setting the logic function depending on the presence or absence of disconnection or writing by injecting charge into the floating gate. In this case,
Since it is necessary to assemble semiconductor integrated circuit devices of different types, it is possible to easily distinguish between them using the identification mark.

The present invention can be widely used in semiconductor integrated circuit devices including programmable ROMs as described above, and in various product development systems thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by attaching marks that can be visually identified to chips on a semiconductor wafer when writing is performed in a nonvolatile memory for defect relief or function modification, it is possible to easily separate the chips during assembly. In addition, by identifying the above marks and assembling different types of semiconductor integrated circuit devices, it becomes possible to rationally develop products according to the performance, etc. of each type.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of a mask ROM to which the present invention is applied, FIG. 2 is a circuit diagram showing another embodiment of a fuse circuit used in the mask ROM, and FIGS. FIG. 3D is a sectional view of a manufacturing process of an embodiment for explaining a method of manufacturing a semiconductor integrated circuit device according to the present invention. ADB: address buffer, DCR: decoder, M
-ROM...Memory array for mask ROM, DOB...
Out cover sofa, ABX...Address Hasof 7, E-RO
M-・Memory array for EPROM, DOX・・Output sofa, C0NT・・Control circuit, F, F 1 =Fm
- Hughes, TSW. TSWI~TSWm...Switch transistor, QE...
・Non-volatile memory element, QN...N channel MO3FE
T (switch transistor)■...Semiconductor substrate, 2,
102... Well region, 3... Field insulating film, 4...
・Channel stopper 5.7, 11, 13.16・
・Insulating film (interlayer insulation layer), 8... Conductive layer, 15.17.
・Wiring layer, 6. 9. IO...Diffusion layer, 14...Contact hole, 18...Final passivation film.

Claims (1)

[Claims] 1. Equipped with non-volatile memory for defect relief or function change,
A semiconductor integrated circuit device characterized in that a mark that can be visually identified on a chip on a semiconductor wafer is attached to the chip on the semiconductor wafer when writing is performed on the nonvolatile memory. 2. The semiconductor integrated circuit device according to claim 1, wherein the identification mark is comprised of fuse means that is electrically disconnected. 3. Programmable RO for defect relief or function change
M, and when this programmable ROM is used, an externally distinguishable mark is attached to the chip on the semiconductor wafer, and the mark is identified to allow each semiconductor integrated circuit device to be assembled as a different type of semiconductor integrated circuit device. Features: Product development method for semiconductor integrated circuit devices. 4. The semiconductor integrated device according to claim 3, wherein the programmable ROM is comprised of a non-volatile memory, and the visually distinguishable mark is comprised of fuse means that is electrically disconnected. Type development method for circuit devices. 5. The semiconductor integrated circuit device according to claim 3, wherein the programmable ROM is a fuse means that is electrically disconnected, and the visually distinguishable mark is the fuse means itself. variety development method.