JPH04132084A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce consumption current of the entire device by preparing plural voltages with mutually different levels out of external supply power source voltage and dividingly supplying prepared each level voltage so as to be different in levels at least in the circuit part directly used at that time and in the circuit part of the other maintenance function. CONSTITUTION:A voltage conversion circuit 101 converting power supply voltage supplied from an external power supply terminal 71 into the voltage with two levels different each other to be outputted to power supply terminals 101a and 101b is provided. While the voltage with necessary level is supplied to the circuit part directly used in the access to the specific memory cell is supplied, and the extremely suppressed voltage within the range of without damaging a function to be maintained by the circuit part, for example, the holding of storage data is supplied to all the indirectly related circuit parts or at least one part of it. Thus, the consumption current in the latter circuit part is reduced and the consumption current of the entire device is also reduced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular, it does not always directly use all of its constituent circuits to achieve a desired function, but selectively uses them from time to time. The present invention relates to a semiconductor device having a structure including a circuit portion that was used in the present invention but was not used in the present invention.

[Conventional technology]

A typical example of this type of device is a semiconductor memory device. An example is shown in FIG. In the figure, 1 is a row address input terminal, 2 is a row address buffer for amplifying or inverting the row address data signal, 3 is a row address decoder for decoding the row address data signal, and 4 is a row address buffer for amplifying or inverting the row address data signal.
5 is a column address input terminal, 5 is a column address buffer for amplifying or inverting a column address data signal, and 6 is a column address decoder for decoding a column address data signal. 1 is a memory cell array in which memory cells for storing information are arranged in a matrix; 8 is a multiplexer; 9 is a sense amplifier that senses and amplifies a small amplitude read voltage; An output data buffer is used to amplify the signal to a level to be outputted to the outside. 1 is a reading ratio data output terminal, 12 is a write data input terminal, and 13 is an input data buffer for amplifying the write data signal. 14 is a chip selection input terminal, 15 is a read/write control input terminal, 16
Sense amplifier 9, output data buffer 1G,
This is a bladder output/write control circuit that controls the write data buffer 13 and the like.

FIG. 8 shows the peripheral portion of the memory cell of the semiconductor memory device of FIG. 7. Here, for simplicity, a configuration with two rows and two columns is shown. In FIG. 8, ZOa.

20b and 216, 21b are corresponding bit line pairs, 22 and 23 are word lines, 241 to 24d are memory cells, 25m, 25b, 2sa, and 26b.
is a bit line load having one end connected to the power supply terminal (voltage Vce) 1B and the other end connected to the bit line. 27m, 27b
, 28m and 28b are transformer 7 gates constituting the multiplexer 8, whose sources or drains are commonly connected to the input/output lines (hereinafter referred to as I10 lines) pair zsa and 29b, and the sense amplifier 9 is connected to these I10 lines. The potential difference between the pair 29m and 29b is detected.

The memory cell 24 includes, for example, a high resistance load type N-channel (hereinafter referred to as N-ch) MOS as shown in FIG. 9(a).
A memory cell or a complementary MO8 (Fig. 9) as shown in Fig.
A memory (hereinafter referred to as CMO8) is used. In FIGS. 9(&) and (b), 41m and 41b are N-Ch driver transistors 428, whose drains are connected to the storage nodes 45m and 45b, whose gates are connected to the other drain, and whose sources are connected to the ground terminal 19. 42b
are N-eh access transistors, 431, 43b
is a load resistance, 44m, 44b Id is a P-channel type (hereinafter referred to as P-Ch) MOSFET.

In FIG. 1θ, a sense amplifier and an I10 line drive circuit 50 are shown.
shows. In the sense amplifier 9, the -to-O differential input N-
The source terminals of e hMO8FETs 59 and 60 are each connected in common, and the drain terminals of P-ekMO8FETs 57 and 58 constituting a current mirror circuit are respectively connected to the other ends. These MO8FETS7,5
IIiMoSFl'l' 5 at the gate common connection point of 8.
The connection point between F and 59 is connected. And ss, so
Amplified output is obtained from the connection point. 61 is N for power down
-chMO8Fg Ding. In addition, a pair of I10 lines 29a and 29b connected to the respective sources of the MO8F mushrooms 27 and 211 for selection of the memory cell 24 are connected to the power supply via the sources and drains of the N-eh MO8FETs 55 and 5g, respectively, as a pair of active loads. Connected to terminal (Yec) 1g. 51.52 are connection terminals from transfer gates 27.28.

Next, the operation will be explained with reference to the operation timing diagram of FIG. 11. In the figure, M□ is the address data signal input to the address buffer, M(III? is the address buffer output, WL is the potential of the word line, Ilo is the potential of the I10 line, Sm., ? is the sense amplifier output, D, II? indicates data output.For example, when selecting memory cell 24&, a row address data signal corresponding to the row in which memory cell 24F to be selected is located is input from row address input terminal 1, and thereby The word line 22 to which 24m is connected is set to a selected (eg, high) level, and the other word lines 23 are set to a non-selected (eg, low) level.

Similarly, regarding the pit line selection, the memory cell 24 & to be selected from the column address input terminal 4 and its memory cell 2
A column address data signal corresponding to the column in which the bit line pair zoa and 20b to which 4 & are connected is input,
Since only the transfer gates (27m, 27b) connected to the bit line pair (zoa, 20b) are conductive, only the selected bit line pair (20m, 20b) is turned on.
10 line pairs 29m and 21bK are connected, other bit line pairs 21m and 21bti are unselected, and I10 line pair zs
a, separated from 29b.

The read operation of the selected memory cell 24m will now be described. Assume that the storage node 45a of the memory cell is now at a high level and the storage node 45b is at a low level.

At this time, one driver transistor 41 of the memory cell
m remains in a non-conducting state, and the other driver transistor 4
1b is in a conductive state.

Since the word line 22 is in a high level selected state,
Memory cell access transistor 42m.

42b are both in a conductive state. Therefore, the power terminal (
Wee) 18 → Bit line load 25b → Bit line 20b →
A direct current is generated in the path from access transistor 42b to drive transistor 41b to ground terminal 1!9.

On the other hand, the other path, power supply terminal (Wee) 18 → bit line load 258 → bit line 20a → access transistor 421 → driver transistor 41a → ground terminal 1
In path 9, since the driver transistor 41& is non-conductive, no direct current flows.

At this time, the potential of the bit line 20 through which no direct current flows is the bit line load transistor zsa, 25b.

If the threshold voltage of 26&, 2@b is vth, then [
The power supply potential becomes -Vth). Further, the potential of the bit line 20b through which the DC current flows is set to the driver transistor 4.
1b, access transistor 42b and bit line load 2
5 & is resistance-divided by the conduction resistance, (power supply potential -Vt
h), the potential decreases by no V, and becomes [power supply potential -Vth-
)V]. ζHere, ΔV is called the bit line amplitude,
Usually 50! The voltage ranges from about IIV to 500 mV, and is adjusted depending on the bit line load. This bit line amplitude is the transfer voltage (L?) through 27m and 27b. Ilo
Line 2! Im, 2! b.KILed. I10 line 2
88 and 211b are set in advance to [power supply potential -Vth) 0 potential, so that [power supply potential -Vth] and [
power supply potential -vth-)V] is input to the first stage sense amplifier 90 MOBFET 5s of the readout amplifier.

60 gates are fed. In this case, the chip enable (cg) signal supplied from the terminal 62 to the sense amplifier 9 is set to high level, and the MO8FET for power down!
1 is in the on state and 1k], and the sense amplifier 9 is in the operating state. The differential signal [)V] of the O input signal is amplified and sent to the output terminal 6 as an unbalanced output signal of the sense amplifier 9.
3 to the output buffer 10, where it is further amplified and read out from the data output terminal 11. In addition, jJI combination Ka input data buffer 713 expansion readout/
To the write control circuit 16! 10 wire pair zsa, 29
b is not driven.

In the case of writing, the potential of the bit line on which data corresponding to a low level is to be written is forcibly lowered to a low potential, and the potential of the other bit line is raised to a high potential. For example, to write inverted data to the memory cell 24m, the I/Q line 29& on the input data buffer 13 is set to a low level, the other Ilo line 2Sbt is set to a high level, and one bit II zoa is set to a low level. 1. Set the other bit line 20b to high level.

Although the above description has been made regarding a semiconductor memory device having a 4-bit configuration to simplify the explanation, the integration of more than one million memory cells has been realized in current semiconductor memory devices, for example, static memory cells. This type of integration has been achieved through the miniaturization of transistors due to advances in semiconductor processing technology, but as miniaturization progresses, it has become necessary to lower the operating voltage of transistors to ensure reliability. There is. On the other hand, the power supply voltage applied to the device itself is conventionally (
For example, it is convenient to leave the voltage as it is (5V) in terms of consistency with conventional products. For this purpose, for example, IIEK Journal on Solid State Circuits Volume 24, No. 5, page 1173 (IEEE JO-URNAL OF
80LID-5TATE CIRCUITS.

VOL, 24. No, 5. O@t, 1989. p117
3) K-described blood pressure system (Voltage −
A method has been proposed, such as the Dawn Conv*-rsiom System, in which the power supply voltage supplied to the device from the outside is reduced within the device.

FIG. 12 shows an example in which this technique is applied to the semiconductor memory device shown in FIG. 7. Voltage conversion circuit T2 that steps down the power supply voltage supplied from external power supply terminal 71 and its output line 7
2m, and its structure and operation are similar to that of the 7th block, except that the level of the power supply voltage applied to the row/column address buffers 2, 5, etc. and the memory cell array 1, etc. is different.
It is basically exactly the same as the one shown in the figure. Although the power supply system in FIG. 7 is omitted, it goes without saying that the power supply voltage is uniformly supplied to each component circuit from the power supply terminal 18.

[Problem to be solved by the invention]

In the semiconductor memory device described above, when a certain word line is selected and becomes high level, all access transistors of memory cells connected to that word line become conductive. For example, in FIG.
When accessing the memory cell 24a, assuming that the memory cells 24b and 24b store high-level data and low-level data, respectively, the word line 22 is selected, and the power supply terminal (Yec) 18 = bit line load. 25b → Bit! A direct current is generated in the path 20b→access transistor 42b→driver transistor 41b→ground block 19. Currently, only 24 m of memory cells are used directly, and 9 memory cells 24 b are unnecessary for the time being.

However, when the word line 22 is selected, this finally unselected memory cell 24bK is also inevitably connected to the power supply terminal (Vee) 18→bit line load 26a→bit line 211→access transistor 421→driver transistor. 41. A current flows through the path a→ground terminal 19. Conversely, when you want to access the memory cell 24b, the memory cell 24m, which is a circuit part that is not directly related to the function you ultimately want to achieve, which is accessing the memory cell 24b,
A current similar to that of the memory cell 24b flows through the memory cell 24b. This relationship is exactly the same even in the case where the power supply voltage level is kept low as shown in FIG.

An object of the present invention is to provide a semiconductor device having circuit parts, such as the above-mentioned memory cell array 1, in which not all of its constituent circuits are always directly used, but are selectively used from time to time. The purpose is to prevent the same current consumption from occurring when the device is used and when it is not used.

[Means to solve the problem]

This invention provides a voltage conversion circuit that converts a power supply voltage supplied to a device from the outside into voltages of different levels. A voltage conversion circuit comprising a circuit that divides and supplies the voltage to each component circuit of the device so that the level is different between the circuit part directly used at that time and at least a part of other circuit parts depending on the time. This is what I used.

[Effect]

While supplying the necessary level of voltage to circuit parts that are directly used to achieve the function desired at that time, for example to access a particular memory cell, all or at least some of the circuit parts that are not directly involved are supplied with that circuit part. By supplying a voltage that is kept as low as possible without impairing the functions to be maintained, such as retention of stored data, current consumption in the latter circuit portion is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a semiconductor memory device showing one embodiment of the present invention. In the figure, 101 is a voltage conversion circuit that converts the power supply voltage supplied from the external power supply terminal 11 into two different levels of voltage and outputs it to the power supply terminals 1018 and 101b, and 102m and 102b are the voltage converters of these two converted voltages. This is a selection signal line on which a signal for controlling which of them is outputted to the terminal 101a and which is outputted to the terminal 101b is carried. Reference numeral 103 indicates a memory cell array, and reference numeral 104 indicates a sense amplifier. Portions with the same reference numerals as in FIG. 7 indicate the same or equivalent portions.

FIG. 2 shows an example of the configuration of the voltage conversion circuit 101. Power supply terminal 101m, 101bti, each transistor 1
It is connected to voltage level conversion transistor groups 105m and 105b via the gates of 08m and 108b and switch transistors 106 & 106e. On the other hand, switch transistors 106m, 106 are connected to the gates of transistors 108&, 1◎8b.
Switch transistor 1G6b, 1ai in parallel with e
d is connected, switch transistor 1osa
, 106e gate is inverter tora, 1G
7b to the control signal lines 102m, 102b, whereas the switch transistors 106b, 10
6d is directly connected to control signal lines 1021 and 102b. Therefore, the control signals jlt102&, 102b
According to the signal, the switch transistor 106m and 106
b or tose and 10610 on/off can be controlled complementary.

In FIG. 3, the memory cell array 1030 bit line load transistors zsa, 25b, zsa, 26b
and the power supply terminal TO1m of the voltage conversion circuit 101, 101
An example of connection with b is shown. In FIG. 8, bit line pair 2o
A, 20b and 21m, 21b were both connected to the same power supply terminal 18, but in this embodiment, they are separated into power supply terminals 101a and 101b, which output complementary voltages at different levels. It is connected.

Next, the operation will be explained. 1 in memory cell array
Each read and write operation of memory cells is
This is exactly the same as the prior art described above, except for the method of applying power supply voltage to the bit line load transistor, which will be described below. Therefore, the method of applying the power supply voltage will be described here. As in the prior art, when selecting the memory cell 24&, the row address data signal corresponding to the row in which the memory cell 24m to be selected is located is input from the row address input terminal 1, and the word to which the memory cell 241 is connected is input. Line 22 is selected (e.g. high)
No level, other word lines 23 are not selected (for example, low)
be leveled. At the same time, the column address decoder 6
Generates a signal that controls the potential of the power supply terminal of the bit line load. Specifically, the selection signal line 102 & is set to high level,
102b is set to low level. Since the signal line 102m is at a high level, the switch transistor 10@b is on, to
sa is off, power supply terminal 1011 K is a certain potential from external power supply terminal 71 (external power supply voltage is vec,
The threshold voltages of the transistors 106b and 1011m are vth 1 .

When Vth2 is set, the potential (Wee vth 1 - Vth 2 ) fi is lowered by vth 1 + Vth2 ).
appear. On the other hand, Vth3 is the threshold voltage of one transistor in the level conversion transistor group 105b, and Vee 3
A potential of vth I Vth 2 is generated.

In this way, the potential of the bit line load connected to the unselected memory cell is set lower than the potential of the bit line load connected to the nine selected memory cells. Here, the voltage output to the power supply terminal 101 & is set to a power supply voltage value that realizes the desired operation, for example, VCC = 4V, which is near the lower limit of the power supply voltage in a MOS device.
The voltage output to 01b is set to the minimum necessary power supply voltage value that does not destroy the data stored in the memory cell, for example, the power supply voltage Vee = 2 V in a MOS device.

When the word line 22 is selected as a high level, one of the bit line pairs connected to the memory cell on the selected word line has a power terminal → bit line load → bit line → access transistor → driver transistor → ground terminal. Direct current is generated in the path. It is clear that the magnitude of this direct current depends on the potential of the power supply terminal. Therefore, reducing the potential of the power supply terminal is extremely effective in reducing the current consumed during operation of the semiconductor memory device.

In the case of writing, the power supply voltage of the bit line load transistor connected to the memory cell other than the memory cell finally selected among the memory cells uniformly selected by the word line is the same as in the read operation. By setting it lower than that of the cell, an equivalent effect in terms of current reduction can be obtained.

In this embodiment, the memory cells on the same word line, for example, 24& and 24b, are configured so that power supply voltages of different levels are applied independently to each memory cell, but as shown in FIG. In a memory cell array having a large number of connected memory cells, the memory cells are, for example, 24m, 24b, 24.

24f etc. may be divided into groups, and the same power supply voltage may be applied to the same group.

In addition, terminals 101m and 101 of the voltage conversion circuit 101
Although the case has been described in which the voltage of a different level outputted from the terminal b is used as the power supply voltage of the memory cell array 103, the present invention is not limited to this, and the same effect can be obtained by using it for the sense amplifier 104, for example. It will be done. Fifth
The figure shows an example. When using (selecting) the sense amplifier 1◎4A, the voltage output to the power terminal 101b of the sense amplifier 104B that is not used (selected) is kept lower than the voltage output to its power terminal 101m. , the current consumed in the sense amplifier can be reduced. Each sense amplifier itself is MO8F corresponding to MO8FET57 to 611C shown in Figure 10.
IT104a to 104 and 104q, 104r
Karana 9, its operation is the same. Note that the first
The symbols of corresponding parts in the θ diagram are listed together.

If there are a large number of sense amplifiers, they may be divided into groups and the same power supply voltage may be applied to each group. An example is shown in FIG. Each sense amplifier 104M, 104B, 104C.

1040 etc. consist of MOSFETs 104a to 104p and 104a to 104ma, etc., and like FIG. 5, the corresponding parts in FIG. 1θ are given the same reference numerals.

Although these sense amplifiers are of the current mirror type, it goes without saying that the present invention is not limited thereto.

Furthermore, the present invention is not limited to the above-mentioned storage device, but is similarly applicable to semiconductor devices having circuit parts that are not always directly used, but are used selectively from time to time. .

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a circuit that creates a plurality of mutually different voltages from an externally supplied power supply voltage, and a voltage at each level that is directly used at the time for each component circuit of the device. By using a voltage converter circuit that is equipped with a circuit that distributes the voltage so that the level is different between the circuit part of the circuit and at least part of the other circuit parts, it is possible to reduce the current consumption of the entire device. It has the following effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of a voltage conversion circuit, and FIGS. A circuit diagram showing a connection example, Figures 5 and 6 a circuit diagram showing an example of the configuration of a Hiro sense amplifier, Figure 7 a block diagram showing a conventional example, and Figures 8 to 1O each showing details of each part. FIG. 11 is a timing diagram showing its operation, and FIG. 12 is a block diagram showing another conventional example. 201~20d, 21a~21d---Bit line, 22°23・φ...Word line, 241~24h・
...Memory cell, 11...External power supply terminal, 1
01・Dispute・Voltage conversion circuit, tota, 101b・
...Power terminal, 102a, 102b...Selection signal line, 104m~104D---Sense amplifier, 105
m, 105b...Voltage conversion level transistor group, 1068-1064...O switch transistor, 1oya. 107b...Working inverter.

Claims (1)

[Claims] Instead of always directly using all of its component circuits to achieve the desired function, it has circuit parts that are used selectively from time to time, and it also converts the externally supplied power supply voltage to a different level of voltage. In a semiconductor device that has a built-in voltage conversion circuit that supplies voltage to each component circuit,
A voltage converter circuit consists of a circuit that creates multiple voltages with different levels from an externally supplied power supply voltage, and a circuit part that transfers the created voltages of each level to each component circuit, depending on the situation. 1. A semiconductor device comprising: a circuit that distributes and supplies supplies at different levels to at least part of other circuit portions at any time.