JPH04130592A - Threshold logic circuit - Google Patents

Threshold logic circuit

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Publication number
JPH04130592A
JPH04130592A JP2251493A JP25149390A JPH04130592A JP H04130592 A JPH04130592 A JP H04130592A JP 2251493 A JP2251493 A JP 2251493A JP 25149390 A JP25149390 A JP 25149390A JP H04130592 A JPH04130592 A JP H04130592A
Authority
JP
Japan
Prior art keywords
circuit
signal
logic circuit
threshold
threshold logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2251493A
Other languages
Japanese (ja)
Inventor
Yutaka Harada
豊 原田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Research Development Corp of Japan
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Filing date
Publication date
Application filed by Research Development Corp of Japan filed Critical Research Development Corp of Japan
Priority to JP2251493A priority Critical patent/JPH04130592A/en
Publication of JPH04130592A publication Critical patent/JPH04130592A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain a neuron element with a high learning efficiency capable of using an algorithm such as a back propagation method by averaging the plural times of output signals of Josephson elements under the same input signal condition, and constituting a threshold circuit in which a signal switching characteristic is differentiable. CONSTITUTION:When a signal current including a noise component is impressed to a quantum interference type Josephson element 100 with a signal switching characteristics indicating a step characteristic, the signal switching characteristic by the output signal average in an averaging circuit 200 turns to a differentiable continuous function. Therefore, using the output of the averaging circuit 200, a learning rule such as the back propagation method can be used. In this case, the average value output of a threshold circuit 500 is compared with an educator signal inputted through an educator signal terminal 302 in a weight control circuit 300, then the weight of a weight circuit 150 is updated through a weight control line 310 based on a compared result. Thus, it is possible to constitute a high speed threshold logic circuit enable to use the learning method with the good learning efficiency and convergency by a high speed Josephson switching circuit.

Description

【発明の詳細な説明】 (発明の利用分野) 本発明は超伝導回路を使ったニューロン素子、特にジョ
セフソン素子を使ったしきい回路の回路構成に係わる。
DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a circuit configuration of a neuron element using a superconducting circuit, particularly a threshold circuit using a Josephson element.

(発明の背景) 従来の計算機はANDまたはOR回路を組み合せた論理
回路システムで構築されている。これらの計算機は極め
て高速に動作し、人間の計算能力を遥かに上回る性能を
発揮し、社会に貢献していることは周知の事実である。
(Background of the Invention) Conventional computers are constructed with a logic circuit system that combines AND or OR circuits. It is a well-known fact that these computers operate at extremely high speeds, exhibit performance that far exceeds human computing ability, and contribute to society.

しかし、従来の計算機は、人間が日常行なっている認識
動作、判断動作には不適当であることも次第に明らかに
なってきた。このため、認識、判断に好適な計算機を構
築する目的で、人間の脳細胞にニューロン)を手本にし
たしきい値論理回路にニューロン素子)とそれを使った
計算機システム技術が例えば、せ利俊−「神経回路網の
数理」産業図書、昭和53年、L、 D、 Jackl
el、 R,E、 Hotward、 H,P、 Gr
af、 B。
However, it has become increasingly clear that conventional computers are unsuitable for the recognition and judgment operations that humans perform on a daily basis. For this reason, for the purpose of constructing computers suitable for recognition and judgment, threshold logic circuits modeled after human brain cells (neurons) and computer system technology using them have been developed. Shun - "Mathematics of Neural Networks" Sangyo Tosho, 1978, L, D, Jackl
el, R, E, Hotward, H, P, Gr
af, B.

Straughn、 and J、 D、Denker
、’Artificial neuralnetwor
ks for computing 、  Journ
al of VacuumScience Techn
ology B4(1)、  Jan/Feb、  1
986.  pp。
Straughn, and J.D., Denker.
, 'Artificial neural network
ks for computing, Journ
al of Vacuum Science Techn.
ology B4(1), Jan/Feb, 1
986. pp.

61−63に開示されている。61-63.

以下に、従来技術によるしきい値論理回路の動作説明を
行い、本発明の位置付けを明らかにする。
The operation of a threshold logic circuit according to the prior art will be explained below to clarify the positioning of the present invention.

第7図はしきい値論理回路の動作を示す図である。FIG. 7 is a diagram showing the operation of the threshold logic circuit.

しきい値論理回路は複数個の入力端子152)入力線1
51と少なくとも1個の出力線104)出力端子105
、重み回路150、しきい回路500から構成される回
路である。入力線151を介して入力された複数の入力
信号Xiは重み回路150で重み付られ、しきい回路5
00で予め定められたしきい値Tと比較される。しきい
回路500は比較結果を基に出力信号Fを出力線104
に出力する。しきい値論理回路では、複数の入力端子に
は“0″または“1”のデジタル信号Xiが印加され、
そのデジタル信号Xiの重み加算和ΣW i X iが
しきい値Tを超えれば出力は“1“に、それ以外は“0
”になる論理動作を行なう。ここで、Wiは重みを表わ
す。従って、第4図に示すしきい値論理回路の動作即ち
入力信号Xiと出力信号Fの関係は(1)式表わされる
The threshold logic circuit has a plurality of input terminals 152) input line 1
51 and at least one output line 104) output terminal 105
, a weighting circuit 150, and a threshold circuit 500. A plurality of input signals Xi inputted via an input line 151 are weighted by a weighting circuit 150, and then sent to a threshold circuit 5.
00 and is compared with a predetermined threshold T. The threshold circuit 500 sends the output signal F to the output line 104 based on the comparison result.
Output to. In the threshold logic circuit, a digital signal Xi of "0" or "1" is applied to a plurality of input terminals,
If the weighted sum ΣW i X i of the digital signal Xi exceeds the threshold T, the output is “1”, otherwise it is “0”.
Here, Wi represents the weight. Therefore, the operation of the threshold logic circuit shown in FIG. 4, that is, the relationship between the input signal Xi and the output signal F, is expressed by equation (1).

F=OΣW i X i < T F=1   ΣW i X i ≧T   ・ ・ ・
 (1)しきい値論理回路では学習により、重みWiを
変化させ、最終的に目的に適応した回路システムを構築
する。従って、しきい値論理回路を構成するには、重み
Wiを変化させる機能と、入力信号の重み加算を行ない
素子をスイッチさせる機能をもたなければならない。通
常、この重みを重み制御線310から入力する重み制御
信号で制御する。
F=OΣW i X i < T F=1 ΣW i X i ≧T ・ ・ ・
(1) In the threshold logic circuit, the weight Wi is changed through learning, and a circuit system that is finally adapted to the purpose is constructed. Therefore, in order to configure a threshold logic circuit, it is necessary to have a function of changing the weight Wi and a function of performing weight addition of input signals and switching elements. Normally, this weight is controlled by a weight control signal input from a weight control line 310.

ジョセフソン素子は高速動作を低消費電力で行うスイッ
チング素子である。ジョセフソン素子は磁束または電流
を信号担体として使っているため、信号値の加算は容易
であり、またジョセフソン素子自体がしきい回路として
の特性を持っているためしきい値論理回路にニューロン
素子)を実現するのに好適である。ジョセフソン素子を
使ってしきい値論理回路を実現する試みは例えば、特願
平01−196115原田「超伝導しきい値論理回路J
に開示されている。この従来技術によるしきい値論理回
路のしきい回路500は第2a図に示す構造からなる。
A Josephson device is a switching device that operates at high speed with low power consumption. Since the Josephson element uses magnetic flux or current as a signal carrier, it is easy to add signal values, and since the Josephson element itself has characteristics as a threshold circuit, a neuron element can be used in the threshold logic circuit. ). An attempt to realize a threshold logic circuit using a Josephson element is made, for example, in Japanese Patent Application No. 01-196115 Harada "Superconducting Threshold Logic Circuit J.
has been disclosed. A threshold circuit 500 of this prior art threshold logic circuit has the structure shown in FIG. 2a.

第2a図の回路は、量子干渉型ジョセフソン素子100
と負荷抵抗103の並列接続に電流源106からバイア
ス電流Igを供給する構成である。量子干渉型回路はジ
ョセフソン素子の分野では公知のデバイスであり、例え
ばT、R,Gheewala、  ”Josephso
n−Logic Devices andCircui
t”、  IEEE Trans、 Electron
 Devices、 vol。
The circuit of FIG. 2a consists of a quantum interference type Josephson device 100
The configuration is such that a bias current Ig is supplied from a current source 106 to a parallel connection of a load resistor 103 and a load resistor 103. Quantum interference circuits are well-known devices in the field of Josephson devices, such as those described by T. R. Gheewala, “Josephson
n-Logic Devices and Circuits
t", IEEE Trans, Electron
Devices, vol.

HD−27,no、  10. pp、 1857=1
869に詳しく記述されている。重み回路150から供
給される入力信号の重み加算和信号電流Icは該量子干
渉型ジョセフソン素子100の制御電流101を流れ、
該量子干渉型ジョセフソン素子の臨界電流(最大超伝導
電流)を制御する。第2b図は該量子干渉型ジョセフソ
ン素子100の電圧電流特性、該負荷抵抗103の負荷
直線と該しきい回路500の動作点を示している。入力
信号の重み加算和信号電流Icが予め定められたしきい
値より小さければ該量子干渉型ジョセフソン素子100
は超伝導状態にあり動作点Aに、しきい値電流よりも大
きいと超伝導状態Aから電圧状態に遷移する。この時、
しきい回路500の出力端子105に現れる出力信号は
、動作点Aの場合は零ボルトで“0”レベルとなり、動
作点Bの場合は有限の電圧値 (約1mV)が現れ″1
″レベルとなる。第3図は入力信号の重み加算和信号電
流1cと該しきい回路500の出力信号の関係、いわゆ
る信号切り換え特性を示している。従来技術による第2
図に示すしきい回路では、超伝導状態Aから段階状に電
圧状態Bに遷移するため、信号切り換え特性も第3図に
示す段階特性を示す。
HD-27, no, 10. pp, 1857=1
869 is described in detail. A weighted sum signal current Ic of input signals supplied from the weighting circuit 150 flows through the control current 101 of the quantum interference type Josephson element 100,
The critical current (maximum superconducting current) of the quantum interference Josephson device is controlled. FIG. 2b shows the voltage-current characteristics of the quantum interference type Josephson device 100, the load line of the load resistor 103, and the operating point of the threshold circuit 500. If the weighted sum signal current Ic of the input signals is smaller than a predetermined threshold, the quantum interference type Josephson element 100
is in a superconducting state and reaches the operating point A, and when the current is larger than the threshold current, it transitions from the superconducting state A to the voltage state. At this time,
The output signal appearing at the output terminal 105 of the threshold circuit 500 is zero volts at the operating point A, which is the "0" level, and at the operating point B, a finite voltage value (approximately 1 mV) appears, which is "1".
'' level. FIG. 3 shows the relationship between the weighted sum signal current 1c of the input signal and the output signal of the threshold circuit 500, that is, the so-called signal switching characteristic.
In the threshold circuit shown in the figure, since the superconducting state A transitions to the voltage state B in steps, the signal switching characteristics also exhibit the step characteristics shown in FIG.

ニューロン素子の学習方法としてパックプロパゲーショ
ン法が用いられる。このパックプロパゲーション法は、
例えば中野馨「ニューロンコンピュータの基礎」コロナ
社(1990年4月)他に開示されている。このパック
プロパゲーション法は、素子の学習効率を上げ収束性を
良くする目的で、信号切り換え特性を第4図に示す微分
可能な関数とし、連続な信号切り換え特性の微係数と出
力信号と教師信号の誤差から重みを更新する。
Pack propagation method is used as a learning method for neuron elements. This pack propagation method is
For example, it is disclosed in Kaoru Nakano, "Fundamentals of Neuron Computers," Corona Publishing (April 1990), and others. In this pack propagation method, in order to increase the learning efficiency of the element and improve the convergence, the signal switching characteristic is made into a differentiable function as shown in Fig. 4, and the differential coefficient of the continuous signal switching characteristic, the output signal, and the teacher signal are used. Update the weights from the error.

方、第3図に示す従来のしきい回路の信号切り換え特性
は段階特性であり、微係数は定義出来ないか、負連続で
ある。このため、第2a図に示すしきい回路500使っ
たしきい値論理回路ではこのままではパックプロパゲー
ション法による学習を実行できない欠点がある。一般に
、収束性を良くす(ためには、信号切り換え特性の微係
数を考慮した重みの更新方法を採用することが望ましい
ことは明かである。
On the other hand, the signal switching characteristic of the conventional threshold circuit shown in FIG. 3 is a stepwise characteristic, and the differential coefficient cannot be defined or is continuously negative. For this reason, the threshold logic circuit using the threshold circuit 500 shown in FIG. 2a has the drawback that learning by the pack propagation method cannot be performed as it is. In general, it is clear that in order to improve convergence, it is desirable to adopt a weight updating method that takes into account the differential coefficient of signal switching characteristics.

(発明の目的) 本発明の目的は、信号切り換え特性が微分可能なしきい
回路を提供し、パックプロパゲーション法等のアルゴリ
ズムが使える学習効率の高いニューロン素子を実現する
ことにある。
(Object of the Invention) An object of the present invention is to provide a threshold circuit whose signal switching characteristics can be differentiated, and to realize a neuron element with high learning efficiency that can use algorithms such as the pack propagation method.

(発明の概要) この目的の為に、本発明では同一人力信号条件下での複
数回のジョセフソン素子の出力信号を平均し、該平均出
力信号を使って素子の信号切り換え特性を定義する方法
を採用する。
(Summary of the Invention) For this purpose, the present invention provides a method of averaging the output signals of a Josephson element multiple times under the same human input signal condition, and using the average output signal to define the signal switching characteristics of the element. Adopt.

(発明の実施例) 以下に実施例を使って本発明によるしきい回路を説明す
る。
(Embodiments of the Invention) A threshold circuit according to the present invention will be described below using embodiments.

第1図は本発明によるしきい回路の実施例である。第1
図に示す実施例は、第2a図に示すしきい回路に平均化
回路200と平均化回路入力線202)平均値出力線2
01を付加した構成である。該平均化回路入力線202
は該しきい値論理回路の出力線104に接続されている
。平均化回路200は平均化回路入力線202から該量
子干渉型ジョセフソン素子100の出力信号を受は取り
、平均化してその値を平均値出力線201に出力する。
FIG. 1 shows an embodiment of a threshold circuit according to the invention. 1st
The embodiment shown in FIG.
This is a configuration with 01 added. The averaging circuit input line 202
is connected to the output line 104 of the threshold logic circuit. The averaging circuit 200 receives and takes the output signal of the quantum interference type Josephson element 100 from the averaging circuit input line 202, averages it, and outputs the value to the average value output line 201.

該量子干渉型ジョセフソン素子100の制御電流線10
1には入力信号の重み加算和信号電流Icが流れるが、
一般にこの信号には雑音が重畳する。更に故意に雑音を
重畳させることも出来る。第3図の段階特性を示す信号
切り換え特性を持つ該量子干渉型ジョセフソン素子10
0に雑音成分を含む信号電流を印加すると、該量子干渉
型ジョセフソン素子100の出力信号は雑音信号の振幅
確率に依存して“0”または “1″の値を示す。重畳
される雑音の平均値が零であれば、該平均化回路200
の平均値信号は入力信号の重み加算和電流Icがしきい
値Tに等しい時は“0”レベルと“1″レベルの中間値
となり、しきい値Tより離れれば離れるほど“0″レベ
ルまたは“1″レベルに漸近する特性を示す。即ち、該
平均化回路200で平均化された出力信号による信号切
り換え特性は第4図に示す微分可能な連続関数となる。
Control current line 10 of the quantum interference type Josephson device 100
1, a weighted summation signal current Ic of the input signal flows,
Generally, noise is superimposed on this signal. Furthermore, it is also possible to intentionally superimpose noise. The quantum interference type Josephson device 10 has a signal switching characteristic exhibiting the stepwise characteristic shown in FIG.
When a signal current containing a noise component at zero is applied, the output signal of the quantum interference type Josephson device 100 exhibits a value of "0" or "1" depending on the amplitude probability of the noise signal. If the average value of the superimposed noise is zero, the averaging circuit 200
When the weighted summation current Ic of the input signal is equal to the threshold value T, the average value signal becomes an intermediate value between the "0" level and the "1" level, and the further away from the threshold value T, the "0" level or It shows the characteristic of asymptotic approach to "1" level. That is, the signal switching characteristic based on the output signal averaged by the averaging circuit 200 becomes a differentiable continuous function shown in FIG.

従って、該平均化回路200の出力信号を使えば、パッ
クプロパゲーション法等の学習法則を使うことが出来る
。また、学習には該平均値を使うが、認識等の論理動作
には出力信号を直接該量子干渉型ジョセフソン素子10
0の出力端子105から平均化しないで取り出すことも
、該平均値出力線201から平均化信号を取り出すこと
もできる。
Therefore, by using the output signal of the averaging circuit 200, learning rules such as the pack propagation method can be used. In addition, although the average value is used for learning, the output signal is directly transmitted to the quantum interference type Josephson element 10 for logical operations such as recognition.
It is possible to take out the signal from the zero output terminal 105 without averaging, or to take out the averaged signal from the average value output line 201.

第5図に本発明による第1図に示したしきい回路500
を用いたしきい値論理回路と学習システムの構成を示す
。第5図の構成では、しきい値論理回路は重み回路15
0と本発明による第1図に示すしきい回路500から構
成される。該重み回路150は例えば、特願平01−1
96115原田「超伝導しきい値論理回路」に開示され
ている。
FIG. 5 shows a threshold circuit 500 shown in FIG. 1 according to the present invention.
The configuration of a threshold logic circuit and learning system using . In the configuration of FIG. 5, the threshold logic circuit is the weight circuit 15.
0 and a threshold circuit 500 shown in FIG. 1 according to the present invention. The weighting circuit 150 is, for example, disclosed in Japanese Patent Application No. 01-1
96115 Harada "Superconducting Threshold Logic Circuit".

該しきい回路500の平均値出力は重み制御回路300
で教師信号端子302)教師信号線301を介して入力
される教師信号と比較され、比較結果を基に重み制御線
310を介して重みが更新される。
The average value output of the threshold circuit 500 is the weight control circuit 300.
The teacher signal terminal 302) is compared with the teacher signal input via the teacher signal line 301, and the weight is updated via the weight control line 310 based on the comparison result.

平均化回路は積分回路またはカウンター回路で実現する
事が出来る。該量子干渉型ジョセフソン素子100は“
0”まけた“1”信号を出力するが、決まった回数の試
行中の“1”信号の数だけ計数すればその値が平均値に
相当することは明かである。従って、該平均化回路20
0は抵抗と静電容量からなるアナログ積分回路やジョセ
フソン素子のスイッチング素子で構成されたデジタル回
路で構成することもできる。また、平均化回路の機能を
重み制御回路300の中に含めることも可能である。平
均化回路は半導体等で構成することも可能である。第6
図はジョセフソン素子で構成された簡単なカウンタ回路
の構成を示している。
The averaging circuit can be implemented with an integrating circuit or a counter circuit. The quantum interference type Josephson device 100 is “
It outputs a "1" signal with a 0" difference, but if you count the number of "1" signals during a fixed number of trials, it is clear that the value corresponds to the average value. Therefore, the averaging circuit 20
0 can also be configured with an analog integration circuit consisting of a resistor and capacitance, or a digital circuit configured with a Josephson element switching element. It is also possible to include the function of the averaging circuit in the weight control circuit 300. The averaging circuit can also be constructed from a semiconductor or the like. 6th
The figure shows the configuration of a simple counter circuit made up of Josephson elements.

第6図の回路は、量子干渉型ジョセフソン素子400と
負荷インダクタ403からなる超伝導閉会路410に電
流源402からバイアス電流を供給する構成である。該
量子干渉型ジョセフソン素子400の制御線404の一
端は抵抗401を介して該平均化回路入力線202に接
続され、多端は接地されている。該超伝導閉会路410
には量子干渉型回路405が結合している。第6図に示
す回路では、平均化回路入力線202に“1”信号が印
加される度に制御電流が該量子干渉型ジョセフソン素子
400に流れ、該素子を一時的に電圧状態に遷移させ、
そのつど該バイアス電流の一部をインダクタ403に分
流させる。従って、インダクタ403に流れる電流は“
1”信号の回数に相当する。この分流電流は量子干渉型
回路405で検出される。
The circuit shown in FIG. 6 has a configuration in which a bias current is supplied from a current source 402 to a superconducting closed circuit 410 consisting of a quantum interference type Josephson element 400 and a load inductor 403. One end of the control line 404 of the quantum interference type Josephson element 400 is connected to the averaging circuit input line 202 via a resistor 401, and the other end is grounded. The superconducting closed path 410
A quantum interference type circuit 405 is coupled to. In the circuit shown in FIG. 6, each time a "1" signal is applied to the averaging circuit input line 202, a control current flows through the quantum interference type Josephson element 400, causing the element to temporarily transition to a voltage state. ,
In each case, a portion of the bias current is shunted to the inductor 403. Therefore, the current flowing through the inductor 403 is “
This corresponds to the number of 1" signals. This shunt current is detected by the quantum interference type circuit 405.

以上の実施例ではジョセフソン素子を例に説明を行なっ
たが、トンネルダイオードの様に段階的に遷移する素子
で構成されたしきい値論理回路にも本発明を適用できる
ことは明か。
Although the above embodiments have been explained using a Josephson element as an example, it is clear that the present invention can also be applied to a threshold logic circuit constituted by an element that transitions in stages, such as a tunnel diode.

(本発明の効果) 以上説明したごとく、本発明を用いれば、高速のジョセ
フソンスイッチング回路で、学習効率や収束性の良い学
習方法を使用できる、速度の速いしきい値論理回路を構
成できる。従って、本発明により、しきい値論理回路を
使った、認識判断を実行するのに好適な高速計算機を実
現できる。故に、本発明はこの高度の認識判断を行なう
高速計算機の実現に必要不可欠である。
(Effects of the Present Invention) As described above, by using the present invention, a high-speed threshold logic circuit that can use a learning method with good learning efficiency and convergence can be constructed using a high-speed Josephson switching circuit. Therefore, according to the present invention, it is possible to realize a high-speed computer suitable for executing recognition judgment using a threshold logic circuit. Therefore, the present invention is indispensable for realizing a high-speed computer that performs this sophisticated recognition judgment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による実施例の回路図、第2a図は従来
のしきい回路の回路図、第2b図は量子干渉型ジョセフ
ソン素子の電圧電流特性を示すグラフ、第3図は従来の
しきい回路の信号切り換え特性を示すグラフ、第4図は
学習過程で望ましい信号切り換え特性を示すグラフ、第
5図は本発明によろしきい回路を使ったしきい値論理回
路と学習システムの構成図、第6図は本実施例の平均化
回路の例を示す回路図、第7図は量子干渉型ジョセフソ
ン素子の電圧電流特性を示すグラフ。 100・・・量子干渉型ジョセフソン素子、101・・
・制御電流線、   103・・・負荷抵抗、104・
・・出力線、     105・・・出力端子、106
・・・電流源、    150・・・重み回路、151
・・・入力線、    152・・・入力端子、200
・・・平均化回路、 201・・・平均値出力線、 202・・・平均化回路入力線、 300・・・重み制御回路、 301・・・教師信号線、 302・・・教師信号端子、 310・・・重み制御線、 400・・・量子干渉型ジョセフソン素子、401・・
・抵抗、 402・・・電流源、 403・・・インダクタ、 ・・・制御線、 ・・・量子干渉回路、 ・・・超伝導閉会路、 ・・・しきい回路。 第1図 第2a図 第5図 第3図 第4図 →Ic 第5図
Fig. 1 is a circuit diagram of an embodiment according to the present invention, Fig. 2a is a circuit diagram of a conventional threshold circuit, Fig. 2b is a graph showing voltage-current characteristics of a quantum interference Josephson device, and Fig. 3 is a conventional A graph showing the signal switching characteristics of the threshold circuit. Figure 4 is a graph showing the signal switching characteristics desirable in the learning process. Figure 5 is a configuration diagram of the threshold logic circuit and learning system using the threshold circuit in the present invention. , FIG. 6 is a circuit diagram showing an example of the averaging circuit of this embodiment, and FIG. 7 is a graph showing voltage-current characteristics of a quantum interference type Josephson element. 100...Quantum interference type Josephson device, 101...
・Control current line, 103...Load resistance, 104・
...Output line, 105...Output terminal, 106
... Current source, 150 ... Weight circuit, 151
...Input line, 152...Input terminal, 200
... Averaging circuit, 201 ... Average value output line, 202 ... Averaging circuit input line, 300 ... Weight control circuit, 301 ... Teacher signal line, 302 ... Teacher signal terminal, 310... Weight control line, 400... Quantum interference type Josephson element, 401...
・Resistor, 402...Current source, 403...Inductor,...Control line,...Quantum interference circuit,...Superconducting closure path,...Threshold circuit. Figure 1 Figure 2a Figure 5 Figure 3 Figure 4 → Ic Figure 5

Claims (1)

【特許請求の範囲】 1)複数の入力信号の重み加算和を予め定められたしき
い値と比較し、比較結果に応じて出力信号を出力するし
きい値論理回路であって、該重みを変更する手段と該出
力信号の平均値信号を発生させる手段を有し、該出力信
号の平均値を使って重みを変更することを特徴とするし
きい値論理回路。 2)特許請求範囲第1項のしきい値論理回路であって、
該出力信号は“0”状態から“1”状態に段階的に遷移
する事を特徴とするしきい値論理回路。 3)特許請求範囲第2項のしきい値論理回路であって、
超伝導状態から電圧状態に段階的に遷移するジョセフソ
ン素子の電圧を出力信号とすることを特徴とするしきい
値論理回路。 4)特許請求範囲第1項のしきい値論理回路であって、
学習には複数回の試行による出力信号の平均化をおこな
い、論理動作には平均化を行なわず直接出力することを
特徴とするしきい値論理回路。 5)特許請求範囲第1項のしきい値論理回路であって、
出力信号の平均化に積分回路を用いることを特徴とする
しきい値論理回路。 6)特許請求範囲第1項のしきい値論理回路であって、
出力信号の平均化にカウンタ回路を用いることを特徴と
するしきい値論理回路。
[Claims] 1) A threshold logic circuit that compares a weighted sum of a plurality of input signals with a predetermined threshold and outputs an output signal according to the comparison result, 1. A threshold logic circuit comprising: means for modifying the output signal; and means for generating an average value signal of the output signal, the average value of the output signal being used to modify the weight. 2) A threshold logic circuit according to claim 1,
A threshold logic circuit characterized in that the output signal transitions stepwise from a "0" state to a "1" state. 3) The threshold logic circuit according to claim 2,
A threshold logic circuit characterized in that the voltage of a Josephson element that transitions stepwise from a superconducting state to a voltage state is used as an output signal. 4) The threshold logic circuit according to claim 1,
A threshold logic circuit characterized by averaging output signals through multiple trials for learning, and directly outputting signals without averaging for logic operations. 5) A threshold logic circuit according to claim 1, comprising:
A threshold logic circuit characterized in that an integrating circuit is used to average output signals. 6) A threshold logic circuit according to claim 1, comprising:
A threshold logic circuit characterized in that a counter circuit is used to average output signals.
JP2251493A 1990-09-20 1990-09-20 Threshold logic circuit Pending JPH04130592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2251493A JPH04130592A (en) 1990-09-20 1990-09-20 Threshold logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2251493A JPH04130592A (en) 1990-09-20 1990-09-20 Threshold logic circuit

Publications (1)

Publication Number Publication Date
JPH04130592A true JPH04130592A (en) 1992-05-01

Family

ID=17223620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2251493A Pending JPH04130592A (en) 1990-09-20 1990-09-20 Threshold logic circuit

Country Status (1)

Country Link
JP (1) JPH04130592A (en)

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