JPH04129423A - Superconducting multi-threshold logic circuit - Google Patents
Superconducting multi-threshold logic circuitInfo
- Publication number
- JPH04129423A JPH04129423A JP2251492A JP25149290A JPH04129423A JP H04129423 A JPH04129423 A JP H04129423A JP 2251492 A JP2251492 A JP 2251492A JP 25149290 A JP25149290 A JP 25149290A JP H04129423 A JPH04129423 A JP H04129423A
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- Prior art keywords
- threshold
- logic circuit
- circuit
- threshold logic
- quantum interference
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- 230000004907 flux Effects 0.000 claims abstract description 20
- 230000006870 function Effects 0.000 claims abstract description 18
- 230000008878 coupling Effects 0.000 abstract description 3
- 238000010168 coupling process Methods 0.000 abstract description 3
- 238000005859 coupling reaction Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 8
- 210000002569 neuron Anatomy 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 241000282412 Homo Species 0.000 description 1
- 210000004958 brain cell Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000004260 weight control Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
(発明の利用分野)
本発明は超伝導回路を使ったニューロン、特に磁束結合
型ジョセフソン素子を使った多しきい値論理回路の回路
構成に係わる。DETAILED DESCRIPTION OF THE INVENTION (Field of Application of the Invention) The present invention relates to a circuit configuration of a neuron using a superconducting circuit, particularly a multi-threshold logic circuit using a flux-coupled Josephson element.
(発明の背景)
従来の計算機はANDまたはOR回路を組み合わせた論
理回路システムで構築されている。これらの計算機は極
めて高速に動作し、人間の計算能力を遥かに上回る性能
を発揮し、社会に貢献していることは周知の事実である
。しかし、従来の計算機は、人間が日常行なっている認
識動作、判断動作には不適当であることも次第に明らか
になってきた。このため、認識、判断に好適な計算機を
構築する目的で、人間の脳細胞にニューロン)を手本に
したしきい値論理回路とそれを使った計算機システム技
術が例えば、せ利俊−「神経回路網の数理」産業図書、
昭和53年、L、 D、 Jackle、l。(Background of the Invention) Conventional computers are constructed with a logic circuit system combining AND or OR circuits. It is a well-known fact that these computers operate at extremely high speeds, exhibit performance that far exceeds human computing ability, and contribute to society. However, it has become increasingly clear that conventional computers are unsuitable for the recognition and judgment operations that humans perform on a daily basis. For this reason, for the purpose of constructing computers suitable for recognition and judgment, threshold logic circuits modeled after human brain cells (neurons) and computer system technology using them have been developed, for example, by Toshi Seri, ``neurons''. “Mathematics of Circuit Networks” Industrial Books,
1978, L. D., Jackle, L.
R,E、 Howard、 H,P、 Graf、 B
、 Straughn、 andJ、 D、 Denk
er、 ” Artificial neural n
etworksfor computing 、J
ournal of Vacuum Scienc
eTechnology B4(1)、 Jan/F
eb、 1986. pp、 61−63に開示
されている。R.E., Howard, H.P., Graf, B.
, Straughn, and J.D., Denk.
er, ” Artificial neural n
networks for computing, J.
Internal of Vacuum Science
eTechnology B4(1), Jan/F
eb, 1986. pp. 61-63.
以下に、従来技術によるしきい値論理回路の動作説明を
行い、本発明の位置付けを明らかにする。The operation of a threshold logic circuit according to the prior art will be explained below to clarify the positioning of the present invention.
第4図は従来のしきい値論理回路の動作を示す図である
。しきい値論理回路は複数個の入力線102と少なくと
も1個の出力線103を持つ回路である。入力線102
を介して入力された複数の入力信号Xiは重み部101
で重み付られ、しきい部200で予め定められたしきい
値Tと比較される。しきい部200は比較結果を基に出
力信号Fを出力線103に出力する。しきい値論理回路
では、複数の入力端子には“0または1”のデジタル信
号Xiが印加され、そのデジタル信号Xiの重み加算和
ΣW i X iがしきい値Tを超えれば出力は“l”
に、それ以外は“O”になる論理動作を行なう。ここで
、Wiは重みを表わす。従って、第4図に示すしきい値
論理回路の動作即ち入力信号Xiと出力信号Fの関係は
(1)式表わされる。FIG. 4 is a diagram showing the operation of a conventional threshold logic circuit. A threshold logic circuit is a circuit having a plurality of input lines 102 and at least one output line 103. Input line 102
The plurality of input signals Xi inputted through the weighting unit 101
and is compared with a predetermined threshold T in the threshold section 200. The threshold unit 200 outputs an output signal F to the output line 103 based on the comparison result. In a threshold logic circuit, a digital signal Xi of "0 or 1" is applied to a plurality of input terminals, and if the weighted sum ΣW i X i of the digital signals Xi exceeds a threshold T, the output becomes "l". ”
Otherwise, it performs a logical operation that becomes "O". Here, Wi represents weight. Therefore, the operation of the threshold logic circuit shown in FIG. 4, ie, the relationship between the input signal Xi and the output signal F, is expressed by equation (1).
F=OΣW i X i < TF=I Σ
W i X i ≧T ・ ・ ・ ・ (1)しき
い値論理回路では学習により、重みWiを変化させ、最
終的に目的に適応した回路システムを構築する。従って
、しきい値論理回路を構成するには、重みWiを変化さ
せる機能と、入力信号の重み加算を行ない素子をスイッ
チさせる機能を持たなければならない。通常、この重み
を制御線104から入力する重み制御信号で制御する。F=OΣW i X i < TF=IΣ
Wi X i ≧T . Therefore, in order to configure a threshold logic circuit, it is necessary to have a function of changing the weight Wi and a function of performing weight addition of input signals and switching elements. Normally, this weight is controlled by a weight control signal input from a control line 104.
従来技術では、しきい値Tは1つの値に限定し、例えば
第5図に示すしきい値特性を(1)式の近似式として採
用している。第5図に示すしきい値特性は(2)式で表
わされる。In the prior art, the threshold value T is limited to one value, and, for example, the threshold characteristic shown in FIG. 5 is employed as an approximation of equation (1). The threshold characteristic shown in FIG. 5 is expressed by equation (2).
F = 1 / (1+ e x p (ΣWiX
i−T))・ ・ ・ (2)
従来技術による、しきい値が1個しか定義されないしき
い値論理回路で実現できる論理関数には限界がある。例
えば2人力の排他論理和関数は(3)式で表わされるが
、この関数はWiをいかに変えても(1)式で表わすこ
とができない。F = 1 / (1+ e x p (ΣWiX
i-T)) (2) There is a limit to the logic functions that can be realized by a threshold logic circuit in which only one threshold is defined according to the prior art. For example, the exclusive OR function of two people is expressed by equation (3), but this function cannot be expressed by equation (1) no matter how Wi is changed.
F=0 ; (Xl =0.X2 =0)o r
(X、=1.X2 =1)
F ” 1 : (X + ” 1 + X
2 二〇 ) Or(X、=O,X2 =1)
・ ・ ・ (3)
この為、従来技術では実現する論理関数の範囲を広げる
ため、第4図に示すしきい値論理関数を多段に接続する
構成方法を採用している。この為、従来技術によるしき
い値論理回路を使って複雑な論理関数を実現しようとす
ると、多くのしきい値論理回路を何段も直並に接続した
複雑な構成を採用しなければならなくなる。この場合、
回路構成が複雑になるだけでなく、しきい値論理回路の
重みを変化させる制御が複雑であり、そのアルゴリズム
は極めて煩雑かつ膨大であり、学習速度が遅くなる欠点
がある。F=0; (Xl=0.X2=0)or
(X, = 1.X2 = 1) F ” 1 : (X + ” 1 + X
220) Or(X,=O, Adopts a configuration method that connects. For this reason, if you try to realize a complex logic function using a threshold logic circuit according to the prior art, you will have to adopt a complicated configuration in which many threshold logic circuits are connected in series. . in this case,
Not only is the circuit configuration complicated, but the control for changing the weight of the threshold logic circuit is complicated, the algorithm is extremely complicated and enormous, and the learning speed is slow.
(発明の目的)
本発明の目的は、複雑な回路構成を取らずに任意の論理
関数を実現できるしきい値論理回路を提供し、簡単な構
成で学習効率の高いニューロン素子を実現することにあ
る。(Objective of the Invention) An object of the present invention is to provide a threshold logic circuit that can realize any logical function without a complicated circuit configuration, and to realize a neuron element with a simple configuration and high learning efficiency. be.
(発明の概要)
この目的の為に、本発明では磁束結合型ジョセフソン素
子を用いた多数のしきい値を持つしきい値論理回路を採
用する。該磁束結合型ジョセフソン素子はしきい値が周
期性持ち、この周期性を利用して複数のしきい値を定義
できる。(Summary of the Invention) For this purpose, the present invention employs a threshold logic circuit having multiple threshold values using magnetic flux-coupled Josephson elements. The flux-coupled Josephson element has periodic threshold values, and this periodicity can be used to define a plurality of threshold values.
(発明の実施例) 以下に実施例を用いて本発明を説明する。(Example of the invention) The present invention will be explained below using Examples.
第1図は本発明の実施例である。第1図の実施例による
しきい値論理回路は、複数の入力線102)出力線10
3)複数の重み部101)しきい部100、制御線10
4から構成されている。該複数の入力線102)出力線
103)複数の重み部101)制御線104の役目は第
4図で説明したものと同じである。一方、しきい部は複
数のしきい値を持ち、その動作は(4)式で表わされる
。FIG. 1 shows an embodiment of the invention. The threshold logic circuit according to the embodiment of FIG.
3) Multiple weight sections 101) Threshold section 100, control line 10
It consists of 4. The roles of the plurality of input lines 102) output lines 103) the plurality of weighting units 101) control line 104 are the same as those explained in FIG. 4. On the other hand, the threshold section has a plurality of threshold values, and its operation is expressed by equation (4).
F=OT、 ≦ΣW i X i < T 2F=I
T2≦ΣW i X i < T 5F=OT、
≦ΣW i X 1 < T <F=I T4≦Σ
W iX t < T s・ ・ (4)
この様な複数のしきい値を持つしきい論理回路を採用す
ると、1個のしきい値論理回路で複雑な論理関数を実現
できる。例えば、(3)式で表わされる排他論理和も(
5)式に示すしきい値開数で表わすことができる。F=OT, ≦ΣW i X i < T 2F=I
T2≦ΣW i X i < T 5F=OT,
≦ΣW i X 1 < T <F=I T4≦Σ
W iX t < T s (4) If such a threshold logic circuit having a plurality of threshold values is employed, a complex logic function can be realized with one threshold logic circuit. For example, the exclusive OR expressed by equation (3) is also (
5) It can be expressed by the threshold numerical value shown in the equation.
F=0 0≦X + + X 2 < 0.5
F=10.5 ≦X+ +X2 < 1.5F=0
1.5 ≦X、+X2 ・ ・ ・ (5)
(5)式の例が示す様に、複数のしきい値を持つしきい
値論理回路を使えば、実現できる論理関数を増やすこと
が出来る。理論的には、無限側のしきい値を定義できる
しきい値論理関数を使えば、任意の論理関数を実現する
事が可能である。従って、複数個のしきい値を定義でき
るしきい値論理回路を使えば簡単な構成で複雑な関数を
実現でき、学習も簡単かつ高速にできるため、極めて有
効なニューロン回路を提供できる。F=0 0≦X + + X 2 < 0.5
F=10.5 ≦X+ +X2 < 1.5F=0
1.5 ≦X, +X2 ・ ・ ・ (5)
As shown in the example of equation (5), the number of logic functions that can be realized can be increased by using a threshold logic circuit having a plurality of threshold values. Theoretically, it is possible to realize any logical function by using a threshold logical function that can define a threshold on the infinite side. Therefore, by using a threshold logic circuit that can define a plurality of threshold values, a complex function can be realized with a simple configuration, and learning can be performed easily and quickly, thereby providing an extremely effective neuron circuit.
第2a図は(4)式の回路動作を行なう2接合磁束結合
型量子干渉回路の例である。第2a図に示す2接合磁束
結合型量子干渉回路はジョセフソン素子の分野では公知
のデバイスであり、例えばT、R,Gheewala、
” Josephson−Logic Device
s andCircuit″、 IEEE Trans
、 Electron Devices、 vol。FIG. 2a shows an example of a two-junction flux-coupled quantum interference circuit that performs the circuit operation of equation (4). The two-junction flux-coupled quantum interference circuit shown in FIG. 2a is a well-known device in the field of Josephson elements, such as T, R, Gheewala,
” Josephson-Logic Device
s and Circuit'', IEEE Trans
, Electron Devices, vol.
ED−27,no、 10. I)り、 1857−1
869に詳しく記述されている。第2a図に示す2接合
磁束結合型量子干渉回路は2個のジョセフソン接合20
1.202と2個のインダクタ203.204から構成
される超伝導閉回路230にバイアス線211を介して
バイアス電流Igが供給される構成である。該超伝導閉
回路230の近傍には制御電流線210が置かれ、該制
御電流線210に流れる制御電流ICによって発生する
磁束が該超伝導閉口路230に鎖交し、該超伝導閉回路
230に流れる最大超伝導電流(臨界電流)を制御する
。第2b図は第2a図に示す2接合磁束結合型量子干渉
回路の制御電流Icと臨界電流の関係例を示している。ED-27, no, 10. I) Ri, 1857-1
869 is described in detail. The two-junction flux-coupled quantum interference circuit shown in Figure 2a consists of two Josephson junctions 20
1.202 and two inductors 203 and 204, a bias current Ig is supplied via a bias line 211 to a superconducting closed circuit 230. A control current line 210 is placed near the superconducting closed circuit 230, and the magnetic flux generated by the control current IC flowing through the control current line 210 interlinks with the superconducting closed circuit 230. control the maximum superconducting current (critical current) flowing in the FIG. 2b shows an example of the relationship between the control current Ic and the critical current of the two-junction flux-coupled quantum interference circuit shown in FIG. 2a.
臨界電流は磁束量子に相当する磁束を発生する制御電流
を周期として制御電流に関して周期性を持つ。The critical current has periodicity with respect to the control current, with the period being the control current that generates magnetic flux corresponding to the magnetic flux quantum.
ここで、2接合磁束結合量子干渉回路に臨界電流よりも
小さいバイアス電流Igを流せば回路は超伝導状態に留
まり、臨界電流よりも大きいバイアス電流Igを流せば
電圧状態に遷移する。例えば、第2b図の様に臨界電流
の最大値と最小値の中間にバイアス電流Igを設定すれ
ば2接合磁束結合型量子干渉回路は制御電流Icを変化
させるにつれて、超伝導状態、電圧状態を繰り返す。バ
イアス電流Igを選ぶことにより、超伝導状態と電圧状
態の範囲割合を変えることが出来る。第2a図に示す2
接合量子干渉回路の制御電流1cが人力信号の重み加算
和 ΣW i X iであればこの回路が(4)式に示
す動作を行なうことは明らかである第3図に示すしきい
値特性は第(4)式のしきい値特性の近似として採用で
きる。第3図のしきい値特性は例えば(6)式で表わさ
れる。Here, if a bias current Ig smaller than the critical current is passed through the two-junction flux-coupled quantum interference circuit, the circuit remains in a superconducting state, and if a bias current Ig larger than the critical current is passed, it transitions to a voltage state. For example, if the bias current Ig is set between the maximum and minimum values of the critical current as shown in Figure 2b, the two-junction flux-coupled quantum interference circuit will change the superconducting state and voltage state as the control current Ic changes. repeat. By selecting the bias current Ig, the range ratio between the superconducting state and the voltage state can be changed. 2 shown in Figure 2a.
If the control current 1c of the junction quantum interference circuit is the weighted sum of human input signals ΣW i X i, it is clear that this circuit performs the operation shown in equation (4). It can be adopted as an approximation of the threshold characteristic of equation (4). The threshold characteristic shown in FIG. 3 is expressed, for example, by equation (6).
F = 1 / (1+ e x p (ΣW i
X i T 2))1/(1+exp(ΣW i
X i T 3))+1/(1+exp(ΣW i
X i T 4))−1/(1+exp(ΣWiX
i −Ts))・ ・ ・ ・ (6)
ここでT、<T2 <TI <74 <TSである。F = 1 / (1+ e x p (ΣW i
X i T 2)) 1/(1+exp(ΣW i
X i T 3))+1/(1+exp(ΣW i
X i T 4))-1/(1+exp(ΣWiX
i −Ts))・・・・・・(6) Here, T<T2<TI<74<TS.
(4)式を(6)式で近似すればこれらの関数は微分可
能であるため、ニューロン素子の学習方法として使われ
るバックプロパゲーション法が使える。If equation (4) is approximated by equation (6), these functions can be differentiated, so the backpropagation method used as a learning method for neuron elements can be used.
第6図は第2a図に示した磁束結合量子干渉回路を使っ
たしきい値論理回路の構成例である。第6図のしきい値
論理回路では、重み部101はジョセフソン素子300
と負荷抵抗301の並列接続に可変電流源310にバイ
アス電流を供給する構成であり、しきい部100はジョ
セフソン素子250に電流源220からバイアス電流を
供給する構成である。ここで、ジョセフソン素子250
は例えば第2a図に示した2接合磁束結合量子干渉を採
用する。第6図に示した重み部101の回路動作は既に
特願平01−196115原田「超伝導しきい値論理回
路」に開示されている。第6図に示すしきい部250は
複数のしきい値を持っているため、第6図に示すしきい
値論理回路が(4)式で表わされる動作を行なうことは
明かである。FIG. 6 shows a configuration example of a threshold logic circuit using the magnetic flux coupled quantum interference circuit shown in FIG. 2a. In the threshold logic circuit of FIG. 6, the weight section 101 is a Josephson element 300.
A bias current is supplied to a variable current source 310 through the parallel connection of a load resistor 301 and a load resistor 301, and a bias current is supplied from a current source 220 to a Josephson element 250 in the threshold section 100. Here, Josephson element 250
For example, the two-junction magnetic flux coupling quantum interference shown in FIG. 2a is employed. The circuit operation of the weighting section 101 shown in FIG. 6 has already been disclosed in Japanese Patent Application No. 1961-15-1961 entitled "Superconducting Threshold Logic Circuit" by Harada. Since the threshold section 250 shown in FIG. 6 has a plurality of threshold values, it is clear that the threshold logic circuit shown in FIG. 6 performs the operation expressed by equation (4).
以上の発明の実施例ではしきい部100のジョセフソン
素子として2接合磁束結合型量子干渉回路を使ったが、
他に3接合以上の磁束結合量子干渉回路や電流注入型量
子干渉回路を使っても同様の機能を実現できることは明
か。In the embodiments of the invention described above, a two-junction flux-coupled quantum interference circuit was used as the Josephson element in the threshold section 100.
It is clear that similar functions can be achieved using magnetic flux coupling quantum interference circuits with three or more junctions or current injection quantum interference circuits.
(本発明の効果)
以上説明したごとく、本発明を用いれば、簡単な構成の
高速のジョセフソンスイッチング回路で、学習速度の速
いしきい値論理回路を構成できる。(Effects of the Present Invention) As described above, by using the present invention, a threshold logic circuit with a fast learning speed can be configured using a high speed Josephson switching circuit with a simple configuration.
従って、本発明により、しきい値論理回路を使った、認
識判断を実行するのに好適な高速計算機を実現できる。Therefore, according to the present invention, it is possible to realize a high-speed computer suitable for executing recognition judgment using a threshold logic circuit.
故に、本発明はこの高度の認識判断を行なう高速計算機
の実現に必要不可欠である。Therefore, the present invention is indispensable for realizing a high-speed computer that performs this sophisticated recognition judgment.
第1図は本発明の実施例の回路図、第2a図は本発明で
使う2接合磁束結合型量子干渉回路、第2b図は第2a
図に示される回路の動作説明図、第3図は本発明による
多しきい値特性の近似図、第4図は従来のしきい値論理
回路図、第5図は従来のしきい値特性の近似図、第6図
は本発明による超伝導多しきい値論理回路の構成例を示
す図である。
100:Lきい部、 101:重み部、102:
入力線、 103:出力線、104:制御線、
200:Lきい部、201.202:ジョセ
フソン接合
203.204:インダクタ、
制御電流線、 211:バイアス線、電流源、
230.超伝導閉回路、ジョセフソン素子、
ジョセフソン素子、
負荷抵抗、 3IO:可変電流源。
第1図
;T4〈ΣX1Wi≦T5
第2a図
第す図
第3図
第4図
第5図
第6図Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2a is a two-junction flux-coupled quantum interference circuit used in the present invention, and Figure 2b is a circuit diagram of a two-junction flux-coupled quantum interference circuit used in the present invention.
3 is an approximation diagram of the multi-threshold characteristic according to the present invention, FIG. 4 is a conventional threshold logic circuit diagram, and FIG. 5 is a diagram of the conventional threshold characteristic. The approximate diagram, FIG. 6, is a diagram showing a configuration example of a superconducting multi-threshold logic circuit according to the present invention. 100: L opening part, 101: Weight part, 102:
Input line, 103: Output line, 104: Control line,
200: L threshold, 201.202: Josephson junction 203.204: Inductor, control current line, 211: Bias line, current source,
230. Superconducting closed circuit, Josephson element, Josephson element, load resistance, 3IO: variable current source. Figure 1; T4〈ΣX1Wi≦T5 Figure 2a Figure 3 Figure 4 Figure 5 Figure 6
Claims (1)
比較し、比較結果に応じて出力信号を出力するしきい値
論理回路であって、該重みを外部より変更する手段を有
し、複数のしきい値で比較できることを特徴とする多し
きい値論理回路。 2)特許請求範囲第1項の多しきい値論理回路であって
、ジョセフソン接合を使った量子干渉回路に該入力信号
の重み加算和信号を入力する構成を有することを特徴と
する超伝導多しきい値論理回路。 3)特許請求範囲第2項の超伝導多しきい値論理回路で
あって、該量子干渉回路が磁束結合量子干渉回路である
ことを特徴とする超伝導多しきい値論理回路。 4)特許請求範囲第1項の多しきい値論理回路であって
、該しきい値特性を関数 F=1/(1+exp(ΣWiXi−T_2))−1/
(1+exp(ΣWiXi−T_3))+l/(1+e
xp(ΣWiXi−T_4))−1/(1+exp(Σ
WiXi−T_5))(T_1<T_2<T_3<T_
4<T_5はしきい値)で近似し、該関数を使って学習
することを特徴とする多しきい値論理回路。[Claims] 1) A threshold logic circuit that compares a weighted sum of input signals with a predetermined threshold value and outputs an output signal according to the comparison result, wherein the weights are input from the outside. A multi-threshold logic circuit characterized in that it has means for changing and can perform comparisons using a plurality of threshold values. 2) A multi-threshold logic circuit according to claim 1, characterized in that it has a configuration in which a weighted sum signal of the input signals is input to a quantum interference circuit using a Josephson junction. Multithreshold logic circuit. 3) The superconducting multi-threshold logic circuit according to claim 2, wherein the quantum interference circuit is a flux-coupled quantum interference circuit. 4) A multi-threshold logic circuit according to claim 1, in which the threshold characteristic is expressed by a function F=1/(1+exp(ΣWiXi-T_2))-1/
(1+exp(ΣWiXi-T_3))+l/(1+e
xp(ΣWiXi-T_4))-1/(1+exp(Σ
WiXi-T_5))(T_1<T_2<T_3<T_
4<T_5 is a threshold value), and learning is performed using the function.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2251492A JPH04129423A (en) | 1990-09-20 | 1990-09-20 | Superconducting multi-threshold logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2251492A JPH04129423A (en) | 1990-09-20 | 1990-09-20 | Superconducting multi-threshold logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04129423A true JPH04129423A (en) | 1992-04-30 |
Family
ID=17223606
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2251492A Pending JPH04129423A (en) | 1990-09-20 | 1990-09-20 | Superconducting multi-threshold logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04129423A (en) |
-
1990
- 1990-09-20 JP JP2251492A patent/JPH04129423A/en active Pending
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