JPH04127868A - High pressure gate driver - Google Patents

Abstract

PURPOSE:To enhance power supply and to prevent fatal failure such as breakdown of main circuit component by employing a dual power supply for a pulse amplifier thereby preventing short circuit fault, occurring when a capacitor in any one power supply is generating gate pulses, from affecting on the gate pulse. CONSTITUTION:Since reverse bias must be applied on the gate of a gate turn OFF thyristor 36 within a short time, the time interval T after provision of an operational command P before rising of an OFF pulse J is set by a smoothing capacitor of about 22muF arranged at the output of a smoothing circuit. On the other hand, since an inverter circuit is operating with high frequency of about 30kHz, ripple current of the smoothing capacitor is high and severe operating conditions are imposed on a capacitor having low capacitance to easily cause self-heating of the capacitor. When a dual power supply system is employed, gate current of the gate turn OFF thyristor 36 is not affected by self-heating phenomenon.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-voltage gate drive device, and in particular, it strengthens the power supply of a pulse amplifier that generates on-pulses and off-pulses by using a dual system to prevent momentary power interruptions. The present invention relates to a high-voltage gate drive device that improves stability by eliminating disturbances in gate pulses caused by such disturbances.

[Conventional technology]

Conventional gate driving devices prevent half-finished gate pulses, as described in Japanese Patent Application Laid-open No. 59-72977,
It is not a method to prevent destruction of the main circuit element (gate turn-off thyristor).

[Problem to be solved by the invention]

Conventional high-voltage gate drive devices generate incomplete gate pulses when the power supply of the pulse amplifier, which amplifies the output pulse of the optical interface and generates on and off pulses, is short-circuited due to an instantaneous short-circuit failure of the filter capacitor. As a result, there was a lack of safety such as damage to the main circuit elements.

An object of the present invention is to provide a high-voltage gate drive device that strengthens the power supply, which is a factor of instability in the conventional technology, improves stability, and prevents fatal failures such as destruction of main circuit elements. There is a particular thing.

[Means to solve the problem]

In order to achieve the above object, the present invention employs a dual power supply system for the pulse amplifier that generates on-pulses and off-pulses, so that even if the capacitor of either power supply short-circuits during gate pulse generation, there is no effect on the gate pulse. This is to ensure that there are no errors.

[Effect]

As a power supply for a pulse amplifier, if a circuit system is used in which the outputs of rectifier circuits with the same rating are matched using high-speed diodes and this output is supplied to a constant voltage element, either one of the rectifier circuits will cause a voltage drop phenomenon instantaneously or continuously. Even if this occurs, the supply to the constant voltage element remains normal, so the gate pulse is not disturbed and stability is further improved. In this case, a detection circuit is installed to check each rectified output of the duplex system in the operating state, and if one of the outputs continues to decrease, this can be detected and displayed to prevent system down. It can be prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. As shown in FIG. 1, the high-voltage gate driving device of the present invention starts upon receiving a 1° operation command P from a high-voltage insulation type optical interface using an LED and a PiN photodiode.
an inverter gate circuit 2 that generates gate signals A and B;
N-channel MO8-FETs 3 and 4 operated by gate signal B whose phase is 180 degrees different from gate signal A,
Excitation current flows alternately from the power supply +V to the low voltage side windings 5a and 5b by MOS-FETs 3 and 4, and the high voltage side winding 5cm5
d, 5e-5f, 5g, and 5h, each of which generates a voltage. 5. High voltage side winding 5C-5d, 5e 5f
, 5g, 5h rectifying circuit 6~
9. Capacitors 10 to 15 for absorbing and smoothing ripples in the rectified DC voltage. Diode 18 for generating H on the OR output by matching the dual system power supplies
~21. Constant voltage element 22 that stabilizes the rectified voltage and generates +V1 and constant voltage element 23 that generates -V1 +V
1 and -V1, capacitors 16 and 17 for lowering the power supply impedance. Connected between +Vz and No, PWM
An off-pulse amplifier 24 that generates an off-pulse J in response to the signal signal. On-pulse amplifier 2 that is connected between Vl and No and generates on-pulse K in response to the PWM signal signal.
5. Check the voltage of the dual rectifier circuit outputs C and E,
Resistors 26 and 27 that output signal X. Resistors 28 and 29 which check the voltage of the rectifier circuit output and F and output a signal Y, and a comparator 31 which compares the signal and the reference voltage +VS and outputs a signal LEDI when an abnormality occurs. A comparator 32 that compares the signal Y with the reference voltage -Vs and outputs a signal LEDz when an abnormality occurs. Signal LEDz.

LED indicator 33 that receives LEDz and lights up the LED
．． It turns on when the on-pulse K is at “L” level, and resistor 3
0 through which the gate current ix flows to turn on the gate turn-off thyristor 36.
N-channel MO8-FET34 that turns on when ET35 and off pulse J are at "H" level, causes gate current 12 to flow, and turns off gate turn-off thyristor 36.
It is made up of.

The operation of this device will be explained with reference to FIG. At to in FIG. 2, when the operation command P rises from n L tt level to "H" level, at tl after a certain period of time, the inverter gate circuit 2 starts operating and gate signal A and gate signal B are generated. Then, N-channel MO5-FETs 3 and 4 are turned on alternately by these gate signals A and B.
OFF, and the exciting current flows from +V to the primary windings 5a and 5b of the high voltage isolation transformer 5, so that the windings 5cm5d, 5cm
Rectangular wave AC voltages are generated at e-5f, 5g, and 5h, respectively. This rectangular wave AC voltage of each winding is rectified by rectifier circuits 6 to 9, and DC voltages C and E, D and F,
The specified value is reached at tz.

Similarly, H on the OR output reaches the specified value, and in order to supply power to constant voltage elements 22 and 23, +■1 at tz
and -V5 are the specified values. Is operation command P input?
The time T until Vz and -v1 reach the specified values is approximately 80m5
It is. At t3.

The PWM signal is transmitted via the optical interface l to the off-pulse amplifier 24 and the on-pulse amplifier 2.
5 and changes from 'L' level to rtH' level, the off pulse J changes from 'gtH' to 'L', turning off the N-channel MO8-FET34 and reducing the gate current i.
s is cut off, and at the same time, the on-pulse K changes from “H” to “L”
As a result, the P-channel MO5-FET 35 is turned on, the main gate current 1 is caused to flow, and the gate turn-off thyristor 36 is turned on, so that the main circuit current M flows.

At t4, when the PWM signal pair changes from "H" to "L", the gate current 11 is cut off and the gate current 12
By flowing, the gate turn-off thyristor 3
6 is turned off and the main circuit current M is cut off. Thereafter, the main circuit current M corresponding to the PWM signal flows in the same manner, supplying power to the load. At t6 when the main circuit current M begins to flow, an instantaneous short circuit failure occurs in either capacitor 11 or capacitor 13, and the rectifier circuit output D
Or, even if F drops instantaneously, there is no abnormality in the OR output H, so the gate current j1 can continue to be in a normal state. t
6 to t8, the potential relationship between the signals Y and -Vs is reversed, so the comparator 32 outputs the signal LEDz, and the LED indicator 33 lights up. When a short-circuit failure occurs in a capacitor, when the circuit impedance to which the capacitor is connected is low, the function is restored by self-healing and the normal state is restored, so that the LED indicator 33 also turns off. At t7, even if either the rectifier circuit 6 or 7 fails and either the rectifier circuit output C1 or E becomes non-voltage,
Since there is no abnormality in the OR output G, the off pulse J is normal and the gate current 12 is not affected at all.If the abnormality in the rectifier circuit output continues after t7, the potential relationship between the signal X and +Vs will be normal. On the other hand, since the comparator 31 outputs the signal LEDI and the LED indicator 33 remains lit, it is easy to discover a failure.

At t6, when the PWM signal becomes inactive, the off pulse J maintains its output state, and the gate of the gate turn-off thyristor 36 maintains a reverse biased state to prevent malfunction.

During the time T from when the operation command P is input until the off-pulse J rises, the gate of the gate turn-off thyristor 36 is reverse biased within a short period of time in order to prevent breakdown of the main circuit elements due to malfunction. Since this is necessary, the capacitance value of the smoothing capacitor output from the rectifier circuit is set to about 22 μF. On the other hand, the inverter circuit is approximately 3
Because it operates at a high frequency of 0KHz, the ripple current of the smoothing capacitor is large in the operating state, creating harsh operating conditions for capacitors with small capacitance values.
The capacitor is used in a state where self-healing phenomenon is likely to occur, but if the dual system method of the present invention is used,
Even if a self-healing phenomenon occurs, the gate current of the gate turn-off thyristor 36 will not be affected.
This has the advantage of being able to prevent a destructive mode caused by turn-on→turn-off caused by a half-finished gate pulse.

〔Effect of the invention〕

According to the present invention, destruction of main circuit elements can be prevented by preventing disturbance of gate pulses without impairing functions during startup.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart showing the operating state of the present invention. 1... Optical interface, 2... Inverter gate circuit, 3-4... N-channel MO8-FET, 5
...High voltage isolation transformer, 5a~5h...Winding, 6~
9... Rectifier circuit, 10-17... Capacitor, 18
~ 21... Diode, 22-23... Constant voltage element, 24... Off-pulse amplifier, 25... On-pulse amplifier, 26-30... Resistor, 31-32... Comparator , 33... LED indicator, 34... N channel MO8-FET, 35... P channel MO8-F
ET, 36...Gate turn-off thyristor.

Claims (1)

[Claims] 1. A low voltage inverter circuit that drives a high voltage isolation transformer;
three sets of rectifier circuits that rectify the rectangular wave alternating current voltages output by the three sets of windings of the high voltage isolation transformer into direct current voltages, a smoothing capacitor that absorbs ripples, and a constant voltage element that stabilizes the gate signal; An optical interface that receives a PWM signal from a gate logic section and is highly insulated by an optical element, a pulse amplifier that amplifies the output signal of the optical interface to generate on-pulses and off-pulses, and is driven by the output of the pulse amplifier. Power MOS
In a high-voltage gate drive device constituted by FET, by making the power supply for the pulse amplifier a dual system, generation of an incomplete gate pulse due to an instantaneous short circuit of the smoothing capacitor is eliminated, and the main circuit element A high-voltage gate drive device characterized in that it prevents destruction of the gate.