JPH04127758A - Level adjustment control system - Google Patents

Abstract

PURPOSE:To enable adjustment to a prescribed level without converting a digital audio signal to an analog signal by setting a gain based on the result of comparing the level of the digital audio signal with a set threshold value, and amplifying the digital audio signal to the prescribed level. CONSTITUTION:An amplifier circuit 2 is provided to amplify the level of the digital audio signal, a gain setting part 3 is provided to set the gain of this amplifier circuit 2, a level detection circuit 4 is provided to detect the average level of the digital audio signal, and a comparator circuit 6 is provided to compare the average level of the digital audio signal with the threshold value set to a threshold value setting register 5. The gain is set based on the compared result of this comparator circuit 6, and the digital audio signal is amplified to the prescribed level by the amplifier circuit 2. Thus, the digital audio signal can be adjusted to the prescribed level without being converted to the analog signal.

Description

[Detailed Description of the Invention] 1 (Required Q: Regarding a level adjustment control method for adjusting the level of a digital audio signal when storing the digital audio signal in a storage device in a voice mail service, etc.) In a level adjustment control method for adjusting a digital audio signal to a predetermined level and storing it in a storage device, the level of the digital audio signal is adjusted to a predetermined level without converting the digital audio signal to a predetermined level. an amplifier circuit for amplifying, a gain setting section for setting the gain of the amplifier circuit, a level detection circuit for detecting the level of the digital audio signal, and a comparison between the level of the digital audio signal and a threshold set in a threshold setting register. and a comparison circuit, the gain is set based on the comparison result by the comparison circuit, and the digital audio signal is amplified by the amplifier circuit so that it reaches a predetermined level.

Industrial Field of Use: The present invention relates to a level 31 control method for adjusting the level of a digital audio signal when storing the digital audio signal in a storage device in a voice mail service or the like.

Currently, it is common for subscribers and digital exchanges to be connected by analog subscriber lines. Therefore, in the digital exchange, the analog voice signal from the subscriber must be converted into a digital voice signal according to the companding side such as μ-1aw or A-ffiaw, and exchange processing and relay transmission must be performed. Furthermore, the signal is converted into an analog voice signal and transmitted to the other subscriber via an analog subscriber line.

In addition, in voice mail services and the like, the information is stored as a digital voice signal or further compressed and encoded in a storage device such as a magnetic disk device. At this time, it is necessary to adjust the digital audio signal to a predetermined level.

[Prior art: Figure 7 is an explanatory diagram of a voice mail service, in which a storage device 81 such as a magnetic disk device is connected to a digital exchange 75 via a trunk 80, and a subscriber 71.79 and a digital exchange 73. 77: Connected by analog subscriber line 72.78, digital exchange 73.7
5.77 shows a system connected by digital relay lines 74.76, and a storage device 81 stores voice signals from subscribers requesting voice mail service.

For example, in response to a voice mail service request from subscriber 71, digital switch 73 connects analog subscriber line 72 to
For example, an analog audio signal transmitted via 8k
Hz sample, 8-bit configuration μmlaw or A-42a
It is converted into a digital audio signal according to the companding side such as w, and sent to a digital exchange 75 equipped with a storage device 81 via a digital relay line 74. digital exchange 75
transfers the received digital audio signal to storage device 81 via trunk 80 and stores it therein. In this case, 64k
The storage capacity of the storage device 81 can also be reduced by compressing and encoding a b/s digital audio signal and storing it as a 32 kb/s digital signal, for example.

The digital audio signal stored in this storage device 81 is
It is read out and transferred upon request from the subscriber, for example, according to a request from the subscriber 79 or information specified by the subscriber 71 such as a specified time or a specified subscriber.
A digital voice signal is read out from 1, sent to digital trunk line 76 via trunk 80, converted to an analog voice signal in digital exchange 77, and sent to subscriber 79 via analog subscriber line 78. . Therefore, subscriber 79 can listen to messages from subscriber 71 at a specified time or at any time.

[Problem to be solved by the invention]

The level of the digital voice signal when stored in the storage device 81 is in accordance with the level of the analog voice signal from the subscriber received by the digital exchange via the analog subscriber line, and Speech levels generally tend to be low, and attenuation due to analog subscriber lines also lowers the analog audio signal level, resulting in a lower digital audio signal level stored in storage device 81. Therefore, the level of the reproduced digital voice signal is also low, and since there is attenuation due to the analog subscriber line, the level of the reproduced voice signal becomes even lower, resulting in a significant deterioration of speech quality.

Therefore, it is known to use an analog AGC circuit to adjust the level of the digital audio signal when it is stored in the storage device 81. However, the digital audio signal has to be further converted into an analog audio signal, amplified to a predetermined level by an AGC circuit, and then converted to a digital audio signal, which has the drawback of increasing the size of the device configuration.

An object of the present invention is to adjust a digital audio signal to a desired level without converting it into an analog signal.

[Failure to solve the problem]

The level adjustment control method of the present invention compares the average level of a digital audio signal at fixed time intervals with a set threshold value and adjusts the level of the digital audio signal, and will be explained with reference to FIG.

In a level adjustment control method for adjusting a digital audio signal to a predetermined level and storing it in a storage device 1 such as a magnetic disk device or a semiconductor memory, an amplifier circuit 2 that amplifies the level of the digital audio signal, and an amplifier circuit 2 for amplifying the level of the digital audio signal, A gain setting section 3 that sets the gain of the circuit 2, a level detection circuit 4 that detects the average level of the digital audio signal, and a comparison circuit 6 that compares the average level of the digital audio signal with a threshold set in the threshold setting register 5. The gain is set based on the comparison result by the comparison circuit 6, and the digital audio signal is amplified by the amplifier circuit 2 to a predetermined level.

Further, the average level of the digital audio signal input to the amplifier circuit 2 is detected by the level detection circuit 4, and the threshold value set in the threshold value setting register 5 is sequentially updated and compared with the average level in the comparison circuit 6. The gain of the amplifier circuit 2 is set by determining the number of times the average level exceeds a threshold value.

Further, the average level of the digital audio signal output from the amplifier circuit 2 is detected by the level detection circuit 4, and the threshold value set in the threshold value setting register 5 is fixed, and the average level is compared with the comparison circuit 6, and the level is determined. The gain of the amplifier circuit 2 is set so that the number of times the average level detected by the detection circuit 4 exceeds a threshold value is a predetermined number of times.

(Operation) The average level of the digital audio signal is detected by the level detection circuit 4, and compared with the threshold value set in the threshold value setting register 5 in the comparison circuit 6, thereby determining the magnitude of the level of the digital audio signal. , the gain of the amplifier circuit 2 is set in the gain setting section 3.

In that case, if the average level of the input digital audio signal of the amplifier circuit 2 is detected and compared sequentially using different thresholds, the magnitude of the average level can be determined by the number of times each threshold is exceeded, so if the average level is low, When the average level is high, the gain is set to be large, and when the average level is high, the gain is set to be small, and the amplification circuit 2 amplifies the digital audio signal according to the set gain, thereby adjusting the digital audio signal to a predetermined level and storing it in the storage device 1. can be done.

Further, when the average level of the output digital audio signal of the amplifier circuit 2 is detected and compared with a fixed threshold value, if the number of times the threshold value is exceeded is greater than a predetermined number, the gain is decreased, and in the opposite case, the gain is increased. Accordingly, the average level of the output digital audio signal can be adjusted to a predetermined level and stored in the storage device 1.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, in which 11 is a subscriber, 12 is a digital exchange, and 13 is a processor (C
C), 14 is a memory (M E
M), 15 is a read-only memory (ROM) that stores programs, etc., 16 is a data bus, 1 is an amplifier circuit,
18 is a gain setting register, 19 is a comparison circuit, 20 is a threshold value setting register, 21 is a level detection circuit, 22 is a direct memory access control circuit (DMAC), 23 is a timing control circuit, 24 is a serial/parallel conversion circuit (S/P ),
25 level conversion section (V
CM), 26 is a conversion data set register (SR)
It is.

The storage device 1 in FIG. 1 corresponds to the memory iJ 144, the amplifier circuit 2 corresponds to the amplifier circuit 17, the gain setting unit 3 corresponds to the processing function of the processor 13 and the gain setting register 18, and the level detection Circuit 4 corresponds to level detection circuit 21 , threshold setting register 5 corresponds to threshold setting register 20 , and comparison circuit 6 corresponds to comparison circuit 19 .

The processor 13 controls each part according to the program stored in the read-only memory 15, controls the gain of the amplifier circuit 17 based on the level determination of the digital audio signal, and amplifies the digital audio signal to a predetermined level. controls writing to the memory 14S, and also controls writing to the memory 14S.
It controls the transmission of digital voice signals read from the digital audio signal to the subscriber via the digital exchange 12.

The analog voice signal from the subscriber 11 is converted into a digital voice signal C2 in the digital exchange 12, as in the conventional example. For example, 8kHz sample, 8bis.7
The digital audio signal is converted into a digital audio signal in accordance with the companding rule C2 of the following configuration. When this digital audio signal is stored in the memory 14, it is amplified to a predetermined level by an amplifier circuit 17, and the amplifier circuit 17, for example, combines a serial-parallel converter circuit 24, a level converter 25, and the converted data. The signal is converted into an 8-bit parallel digital signal by the serial/parallel converter circuit 24 and becomes part of the address of the level converter 25, and the gain setting register IEH is configured to provide a set several-bit gain. is the remaining address.

This level converter 25 converts the 8-bit digital audio signal and the several-bit gain into 71-res.
It consists of a read-only memory from which a digital audio signal with a bit configuration is read out, and the read digital audio signal with an 8-bit configuration is set in a conversion data set register 26. That is, a digital audio signal whose level has been amplified is output from the amplifier circuit 17 according to the gain O set in the gain setting register 1.

The direct memory access control circuit 22 controls the data bus 1 by applying an interrupt signal IRQ to the processor 13.
6, transfers the output digital audio signal of the amplifier circuit 17 to the memory 14 via the data bus 16, and writes the digital audio signal in the memory 14.

In order to set the gain of the amplifier circuit 17, the level detection circuit 2
1, the average level of the digital audio signal is detected in accordance with the timing signal from the timing control plate circuit 23, and the average level for each predetermined time is compared with the threshold value set in the threshold value setting register 20 by the comparison circuit I9. In this case, there are cases in which the threshold values set in the threshold value setting register 20 are updated sequentially and cases in which they are fixed.
When applying the input digital audio signal to the level detection circuit 21 through the path shown by the dotted line, the threshold values are updated sequentially,
The gain of the amplifier circuit 17 is determined by determining the level of the digital audio signal, and when the output digital audio signal of the amplifier circuit 17 is applied to the level detection circuit 21 through the path shown by the solid line, the threshold value is fixed and The gain of the amplifier circuit 17 is set so that the average level of the digital audio signal whose level has been amplified by the amplifier circuit 17 becomes the threshold value.

FIG. 3 is a flowchart of an embodiment of the present invention, in which the threshold set in the threshold setting register 20 is sequentially updated under the control of the processor 13, and the gain of the amplifier circuit 17 is set to A.
In this case, the time or unit time in which one block is transferred under the control of the direct memory access control circuit 22 is set as t, and the counter TCNT (processor, 7sa 130 count function) al), T
For CN”r#nXL (N), sequence 5EQO
~5EQ3 are executed sequentially, and if TCNT=nXL (Y
) is the level 1 to 3 judgment counter LVICNT-LV
Compare the value of 3CNT (which can be configured by the counting function of processor 3, etc.), and set MP to the gain of the amplifier circuit 17 (al9).

Sequence 5 EQO is a sequence for determining whether the input digital audio signal is audible or silent; the input digital audio signal of the amplifier circuit 17 is applied to the level detection circuit 21, and the average level detected by the level detection circuit 21 is AV and the threshold L set in the threshold setting register 20
It is compared with V in the comparison circuit 19 to determine whether AV>LV (a2). The threshold value LV in this case is set to the threshold value 1vo of level 0. When AV > LV, the average level AV of the digital audio signal is very low, so it is determined that there is no sound and the process returns to the first step (RTI) (a20
), or when AV>LV, set the level 10 threshold It,・1 in the threshold setting register 20 a3), sequence S
Let EQ be the next --- 5EQl (a4).

In Sequence 5 EQI: Yo, level detection time! 21 and the threshold value LV-IV1 set in the threshold value setting register 20 in step (a3) 4m.
The comparator circuit 19 compares them to determine whether AV>LV or not.a5) If AV>LV is not the case, proceed to step 7 (al), and if AV>LV, level 1 is reached. The determination counter LVICNT is incremented by 1 (a6). Then, the threshold value IV2 of level 2 is set in the threshold value setting register 20 (al), and the sequence SEQ is set to the next sequence 5EQ2 (a8).

In the next sequence 5EQ2, the average level AV detected by the level detection circuit 21 and the threshold value LV-1v2 set in the threshold value setting register 20 in step (al) are calculated.
are compared in the comparison circuit 19 to determine whether AV>LV or not (a9), and if AV>LV is not the case, step (al
l), and when A V > L VO, Le, Le 2
The judgment counter LV2CNT is incremented by 1 (alO), and the threshold value 1v3 of LE3 is set in the threshold value setting register 20.
Set allL, and set the sequence SEQ to the next sequence 5EQ3 (al2).

In the next sequence 5EQ3, the average level AV detected by the level detection circuit 21 and the threshold value LV=lv set in the threshold value setting register 20 in step (all)
3 in the comparator circuit 19 to determine whether AV>LV or not (al3). If AV>LV is not the case, step (al3) is performed.
al5), and when AV>LV0, the level 3 judgment counter LV3CNT is incremented by 1 (al4), and
Set the threshold value 1vo of level O in the threshold value setting register 20 al5), and set the sequence SEQ to the next sequence 5EQ.
O (al6).

Then, the counter TCNT is +IL (al7), the process returns to the first step (a 20 ), and the above steps are repeated until TCNT=n×t.

When T CN T = n X t, levels 1 to 3
The processor 13 compares the values of the determination counters LVICNT to LV3CNT al8), and when the content of the level 1 determination counter LVICNT is the maximum, the gain AMP of the amplifier circuit 17 is set to AMPI, and the level 2 determination counter LV
When the content of 2CNT is maximum, the gain A of the amplifier circuit 17
MP is AMP2, level 3 judgment counter LV3
When the content of CNT is maximum, the gain AMP of the amplifier circuit 17
Let be AMP3 (al9).

As mentioned above, the 1iEl value (]VQ<I
vl<lv2<1v3) are sequentially set in the threshold setting register 20 under the control of the processor 13, and levels 1 to 3
The determination counter LVICNT-LV3 CNT counts the number of times the average level of the digital audio signal exceeds the threshold of levels 1 to 3, and by comparing the count contents, the gain of the amplifier circuit 17 (AMP1>AMP2>AMP3
) is set in the gain setting register 18. For example, when the average level of the digital audio signal is the lowest, a large gain IAMPI will be set.

4 and 5 are flowcharts of another embodiment of the present invention, step (bl) is the same as step (al) in FIG. 3, and sequences 5EQO, 5EQ
2 is a sequence for determining whether there is a sound or no sound, and the input digital audio signal of the amplifier circuit 17 is sent to the level detection circuit 21
In addition, the average level is detected, and the average level AV and O
Compare the level threshold LV with b2. bl 1), :>
-In the case of Kens 5 EQO, when there is a sound (AV>LV),
The threshold LV is set to the threshold 1vl of level 1 (b3), and the sequence SEQ is set to the next sequence 5EQI (b4).

In addition, in the case of sequence 5EQ2, when there is a sound (AV>LV), set the threshold LV to the level 2 threshold]v2),
Let the sequence SEQ be the next sequence 5EQ3 (b
l3).

In sequence 5EQI, using the level 1 threshold 1vl set in step (b3), AV>LV=
l v 1 or not b5), and when AV>LV, set the audio high state counter CNTO to 11 b7), AV>
When it is not LV, set the audio low state counter CNTl to -IL(
b6), convert the sequence SEQ to the first sequence 5EQO
(b8).

Then, the threshold LV is set to the threshold 1 v O! of level O! Return to the second step b9), set the counter TCNT to -IL (blo), and return to the first step (RTI) (b20).

In sequence 5EQ3, using the level 2 threshold 1v2 set in step (bl2), AV>LV
- ]v2 or not (bl4), if AV>LV, set the audio high state counter CNTO to 1IL (bl6), AV
>If not LV, the voice low state counter CNT1 is divided by 1 (bl5). Then, set the sequence SEQ to the next sequence 5EQ2 bl7), return the threshold LV to the threshold 1VO of level O bl8), increase the counter TCNT by +1 bl9), and return to the first step (RTI) (b20
).

When the counter TCNT reaches nXt, it is determined whether the previous sequence is 5EQI or 5EQ3 b21), and in the case of sequence 5EQI, the audio high state counter CNTO and the audio low state counter CNTl are compared b22), C
If NTO>CNTl, the gain AMP of the amplifier circuit 17
be the lowest AMPIb28), and CNTO>CN
If it is not Tl, the gain AMP of the amplifier circuit 17 is set to intermediate AMP2 b24), the count content of the counter TCNT is set to 0 b25), the sequence SEQ is set to sequence 5EQ2 b26), and the process returns to the first step (b
27).

If the current sequence is sequence 5EQ3,
Audio high status counter CNTO and audio low status counter CN
b23), if CNTo>CNTl, set the gain AMP of the amplifier circuit 17 to the intermediate gain AMP2b29), and if CNTO>CNT1, set the gain AMP of the amplifier circuit 17 to the highest gain AMP3. do (b
30).

Through the above processing, the gain AMP of the amplifier circuit 17 becomes AMP
1<AMP2<AMP3, and a digital audio signal amplified to a predetermined level is written into the memory 14.

FIG. 6 is a flowchart of still another embodiment of the present invention, showing a case where the threshold value LV set in the threshold value setting register 20 is fixed, and the digital audio signal amplified by the amplifier circuit 17 is passed through the level detection circuit through the solid line path. In addition to 21, an average level is detected and the average level is added to the comparison circuit 19. Then, as in steps (al) and (bl) in the above embodiment, the counter TCNT is set to t.
1) If TCNT+nXt, execute sequences 5EQO and 5EQI, and TCNT=
In the case of nXt, the gain AMP of the amplifier circuit 17 is set (c7).

Sequence 5EQO determines whether there is a sound or no sound.
The average level AV of the digital audio signal and the threshold value LV set in the threshold value setting register 20 are compared in the comparison circuit 19c2), and when AV>LV is not determined as silence,
Also, when AV>LV, the sequence SEQ is changed to the next sequence 5EQI (c3), and the process returns to the first step (c1
0).

Sequence 5EQI determines whether AV>LV (c
4) When AV>LVO, level judgment counter LVC
NT by -j-LL (C5), counter TCNT by +l (C6), and return to the first step by RTI (cl
O). If AV>LV is not satisfied, the process moves to step (C6).

Also, when T CN T = n X t, the amplifier circuit 1
When the gain of 7 is set to the relationship AMP1>AMP2>AMP3, when the gain of the amplifier circuit 17 is AMPI, if the level judgment counter LVCNT is larger than the judgment constant ml, the gain is reduced to AMP2. Further, when the gain is AMP2, if the level judgment counter LVCNT is larger than the judgment constant m2, the gain is reduced to AMP3.

Further, in the case of the gain in the relationship AMP1<AMP2<AMP3, when the gain of the amplifier circuit 17 is AMPI, if the level judgment counter LVCNT is smaller than the judgment constant ml, the gain is increased to AMP2.

Also, when the gain is AMP2, the level judgment counter LVC
If NT is smaller than the determination constant m2, the gain is increased to AMP3 (C7).

Then, a counter TCNT and a level judgment counter LV
Clear CNT (C8), change sequence SEQ to the first sequence 5EQO (C9), and return to the first step (clo).

In each of the embodiments described above, the gain of the amplifier circuit 17 is set to AM
Although the case where the level is set to three levels, P1 to AMP3, is shown, it is of course possible to set more levels, and the amplifier circuit 17 can also be configured using a multiplier circuit, etc. It is.

〔Effect of the invention〕

As explained above, the present invention detects the average level of a digital audio signal by the level detection circuit 4, compares it with the threshold set in the threshold value setting register 5 in the comparison circuit 6, and adjusts the gain based on the comparison result. The gain of the amplifier circuit 2 is set by the setting section 3, and the digital audio signal is amplified to a predetermined level and stored in the storage device l, and the digital audio signal is adjusted to the predetermined level without converting it into an analog signal. Therefore, there is an advantage that a voice mail service or the like can be realized with an economical configuration without deteriorating voice quality.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a flowchart of an embodiment of the present invention, and FIGS. 4 and 5 are other embodiments of the present invention. FIG. 6 is a flowchart of another embodiment of the present invention, and FIG. 7 is an explanatory diagram of a voice mail service. 1 is a storage device, 2 is an amplifier circuit, 3 is a gain setting section, 4 is a level detection circuit, 5 is a threshold value setting register, and 6 is a comparison circuit.

Claims (3)

[Claims] (1) In a level adjustment control method for adjusting a digital audio signal to a predetermined level and storing it in the storage device (1), an amplifier circuit (
2), a gain setting section (3) for setting the gain of the amplifier circuit (2), a level detection circuit (4) for detecting the level of the digital audio signal, and a level and threshold setting register for the digital audio signal. (
a comparison circuit (6) that compares the digital audio signal with a threshold value set in (5), and sets the gain based on the comparison result by the comparison circuit (6), and adjusts the digital audio signal to a predetermined level. A level adjustment control method characterized by amplification using an amplifier circuit (2). (2) The level of the digital audio signal input to the amplifier circuit (2) is detected in the level detection circuit (4), and the threshold value set in the threshold value setting register (5) is sequentially updated. 2. The gain of the amplifier circuit (2) is set by comparing the level in the comparing circuit (6) and determining the number of times the level exceeds the threshold value. Level adjustment control method. (3) Detecting the level of the digital audio signal output from the amplifier circuit (2) in the level detection circuit (4), and fixing the threshold value set in the threshold value setting register (5). The level is compared with the comparison circuit (6), and the gain of the amplifier circuit (2) is set so that the number of times the level detected by the level detection circuit (4) exceeds the threshold is a predetermined number. The level adjustment control system according to claim 1, characterized in that: