JPH04127746A - Line information delay difference absorbing system for atm network - Google Patents

Abstract

PURPOSE:To reduce the capacity of a buffer memory and to improve communication quality by minimizing the delay of read start time from the delay difference absorbing buffer memory. CONSTITUTION:A cell decomposing device 2 is equipped with a delay difference absorbing buffer 3 to output the information cell of a reception line after delaying the cell so as to satisfy a prescribed delay arrival abandonment ratio, and a control part 4 to control the delay difference absorbing buffer 3. A delay difference absorbing delay time minimizing means 5 of this control part 4 sets delay difference absorption delay time after receiving the first cell after starting communication equal to difference between maximum queuing delay time and minimum queuing delay time and therefore, delay time is suppressed at the delay time absorbing buffer. Thus end-end delay time can be shortened, and the capacity of the delay difference absorbing buffer can be minimized.

Description

[Detailed Description of the Invention] [Summary] Regarding a line information delay difference absorption method in an ATM network, the delay time in the delay difference absorption buffer is minimized, and the end-
Cell disassembly that reproduces line information cells received via the ATM network in synchronization with the generation cycle of the line information cells, with the aim of shortening the end delay time and minimizing the capacity of the delay difference absorption buffer. The device includes: a delay difference absorption buffer that outputs the received line information cell after delaying it so as to satisfy a predetermined late arrival/discard rate; and a control unit that controls the delay difference absorption buffer, the control unit , the delay difference absorption delay time (AD) after receiving the first cell after communication starts, and the maximum queuing delay time (Q
) and the minimum queuing delay time (Ω1゜,
, ) to minimize the delay difference absorption delay time.

[Industrial application field]

The present invention is an ATM (Asynchronous Tractor).
nsfer Made) network, an AT system that absorbs the delay fluctuations in information that occur in the ATM network and restores the information to the generation cycle at the receiving terminal.
This paper relates to a line information delay difference absorption method in the M network.

In recent years, there has been an increasing demand for broadband 15DN that efficiently realizes multimedia communications including high-quality video information in communication networks. At CCITT, ATM (Asynchronous
.

US Transfer Mode) is currently being considered in accordance with the 1192 recommendation.

Figure 7 is A for explaining the industrial application field of the present invention.
1 is a block diagram showing a TM switching system, which includes a transmitting terminal 71, a cell forming device 72, an ATM network 73, a cell disassembling device 74, and a receiving terminal 75. The present invention relates to a line information delay difference absorption method in the cell disassembly device 74 in this system.

FIG. 8 is a time chart showing the output of each device shown in FIG.

In FIGS. 7 and 8, in the ATM switching system, information (1) output from a transmitting terminal 71 at a constant period T is divided into fixed length cells (2) by a cell generator 72 and transmitted to the ATM.
The output (3) of the ATM network 63 after being transferred to the M network 73 and subjected to the switching operation is sent to the transmitting terminal 7 by the cell disassembly device 74.
It is synchronized with the cell having the same cycle as the output from 1, and is manually input to the receiving terminal 75 (4).

Similar to packet switching, this ATM exchange transfers information by allocating the number of cells according to the information bandwidth requested by the user, so it is possible to centrally handle various information such as information on different bandwidths and burst information, and is configured as a single network. This can be realized through network design, maintenance,
It has the potential to improve operational efficiency and to make efficient use of transmission lines and switching equipment by statistically multiplexing burst information (statistical multiplexing effect).

However, when accommodating line information, the cell creation delay PD, A required to convert source information into cells as in packet switching
A queuing delay QD required from the input to the output of the TM network 730 and a variation AD in the queuing delay between the output of the ATM network 73 and the output of the cell disassembly device 74 occur, and due to the variation AD in the queuing delay, Even though the line information is created periodically at the cell stage, the intervals between the cells arriving at the receiving terminal fluctuate. Therefore, a method is adopted in which the cell disassembly device 74 writes a cell every time a cell arrives and restores the line information by providing a buffer for absorbing delay differences which is periodically read out at the information cycle. Generally, in order to absorb the delay difference between arriving cells of line information, it is sufficient to prepare a buffer with a sufficiently large capacity for delay difference absorption, but there is a problem in that the storage time in the buffer increases the delay time.

[Conventional technology]

As a conventional delay difference absorption method, IEICE Information Network Study Group JN87-112, pp. 13-1
There is an lSt cell system described in section 4 of ``Circuit switching service in rATM'' described on page 8. In this method, as shown in FIG. 7 of the same document, after writing the first cell to the delay difference absorption buffer, the received cells are accumulated for the maximum queuing delay time in the network, and the first cell is read out. A method was adopted to start the process. In this system, the maximum end-to-end delay between the transmitting terminal 71 and the receiving terminal 75 is determined by the cell creation delay time FD, the maximum delay ODMaX from the output of the cell forming device 72 to the output of the ATM network 73, and the maximum delay ODMa FD which is the sum of the delay difference absorption delay AD=QD from the output of the cell disassembly device 64 to the output of the cell disassembly device 64
+2QD6, (AD=QD□, PD: cell creation delay, QD□X: maximum queuing delay, AD: delay difference absorption delay).

That is, in this prior art, the delay difference absorption delay AD is set equal to the maximum queuing delay QD, ,X.

By doing so, a predetermined late arrival discard rate can be satisfied even when the queuing delay time QD of the first cell is the minimum. Here, the late arrival discard rate needs to be considered only in circuit switching services, and underflow occurs when a cell arrives with a queuing delay that is greater than the load delay for absorbing delay fluctuations at the receiving terminal. This is the case when a cell is discarded due to the occurrence of a cell.

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, there are problems such as severe end-to-end delay in low-speed calls and increase in the required capacity of the delay difference absorption buffer in high-speed calls.

An object of the present invention is to minimize the delay time in the delay difference absorption buffer, shorten the end-to-end delay time, and minimize the capacity of the delay difference absorption buffer.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, 1 is an ATM network, 2 is a cell disassembly unit, 3 is a delay difference absorbing buffer, 4 is a control unit, 5 is delay difference absorbing delay time minimizing means, and 6 is minimum delay time determining means.

The delay difference absorption delay time minimizing means 5 sets the delay difference absorption delay AD from the received cell from the ATM network 1 to the minimum. As a means to do so, as an AD (QDmay QD
+ath). The reason is that QD, , is considered to be a fixed delay. The end at this time
The maximum end delay is (PD+2QD,,X-QD,,
,,) becomes.

According to another aspect of the invention, the received cell spacing is monitored from the largest number of cells and the QDffii. By estimating
Identify PD+QD to approach AM as the end-to-end maximum delay.

[Effect]

Since the delay time in the delay difference absorption buffer is suppressed as much as possible, it is possible to shorten the end-to-end delay time and minimize the capacity of the delay difference absorption buffer.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a cell disassembly device according to the first embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of signal cells transferred from an ATM network. In FIG. 2, 21 is a cell detection section, 22 is a buffer memory section, 23 is a signal processing section, 24 is a processor section, and 25 is a cycle succession control section.

Prior to the start of communication, the information speed specified by the receiving terminal
/s is notified from the ATM network. This communication requires a certain VCI (Virtual Cell Identity).
A cell with a fier) is used. For example, ver=
Assuming that a signal cell of z is used, the cell detection section 31 that received this signal cell analyzes the VCI and finds that it is Z, and transfers the signal cell to the signal processing section 33 (■→ ■). The signal processing section analyzes the information field in the signal cell and notifies the processor section 24 of the terminal information speed X b/s written therein.

When the processor section 24 receives the terminal information speed, it initializes the cell detection section 21, buffer memory section 22, and periodic readout control section 25 (■, ■, ■). The processor 24 notifies the buffer memory section 21 that the VCI of the cell to be written to the buffer memory is Y. The processor 24 also instructs the buffer memory section 22 to reset the buffer memory, and also instructs the buffer memory section 22 to set the maximum queuing delay time. Ω, the number of bits N accumulated in a time δ equal to the difference between X and the minimum queuing delay time Q, 0. Here, N is (
Q□8-Ro1,1)・X (bit).

The processor section 24 also resets the timer in the periodic readout control section 25 and notifies the cell generation period T. Here, T is the number of information bits in one cell/X.

When communication to the terminal starts and a cell arrives at the terminal (
(2), the cell detection unit 2I checks the internal cell CI, and the cell detection unit 21 gives the buffer memory 22 a time write enable pulse WE for only the cell information of VCI=Y (■), and the information is transferred to the buffer memory 22. (■).

When the information written in the buffer memory 22 reaches the above-mentioned N bits, the buffer memory 22 generates a flag signal FLG and supplies it to the periodic read control section 25. As a result, the periodic readout control section 25 supplies the read enable signal RE to the buffer memory 22 to start successive reading and read information from the buffer memory 22 every hour.

FIG. 4 is a time chart illustrating the successive start time according to the above embodiment of the present invention. In the figure, (1) is the timing t of cell output from the information source. , jl+
t2+---, (2) shows the output of the ATM network, that is, the reception timing aOt al+ a2+ - of the received cell received by the cell detection unit 21, and (3) shows the output from the buffer memory 22 after absorbing the delay difference. The read timing b, , b, , b, , , , is shown.

As shown in the figure, cells are output at a constant period T at the information source. The cell detection unit 21 detects cells to be received from the received cell stream, and detects cells to be received at irregular timing a for each reception. , al+ a2+ , , , , are written into the buffer memory 22. The time ΩD from time t0 to reception of the first cell is the queuing delay.

At the same time as the first information is written into the buffer memory 21 at timing aO, the processor unit 24 drives a timer in the periodic read control unit 25, and δ-QD, .

QD... Later time. The reading starts from , and is read out at the same period T as the period of the information generation source.

The maximum end-to-end delay at this time is PD + 2ΩDwa
x QD sih, and the delay time is shorter than before, so the capacity of the buffer memory can be reduced.

FIG. 5 is a block diagram showing the configuration of a cell disassembly apparatus according to a second embodiment of the present invention. In the figure, the same parts as in FIG. 2 are given the same reference numerals, and the parts different from those in FIG. This is what is being done. In this embodiment, from the reception timing of the first received cell in the first embodiment, δ・QD, aX−QD, .
, instead of starting reading after delaying Q.
A plurality of received cells are consecutively received within a predetermined time shorter than DI@aX, and reading from the buffer memory is started based on the delay time of the cell showing the smallest delay among them.

For this purpose, the processor unit 24 also performs the initial setting of the internal timer for control in the trigger control unit 51, and
The cell generation cycle T is notified.

In the trigger control unit 51, for example, the formula i=(QD,,X-
Find the cell with the minimum delay from the first cell determined from QD30, )/T, estimate the time at which reading from that cell should start from the buffer memory 22, and generate the trigger signal TRG.
is generated and given to the periodic readout control section 25, instructing the periodic readout control section 25 to read information into the buffer memory 22 (■). Thereafter, the periodic readout control section 25 instructs the buffer memory section 22 to read out information regardless of the state of the FLG.

FIG. 6 is a time chart for explaining the generation timing of the trigger signal TRG.

When the first cell arrives a. To a. Let +δ be a tentative successive start time Z. At the next cell arrival time a1, (at+δ−
T) is calculated and compared with the previous time Z, and the earlier one is set to 2. In the example of FIG. 6, 2=(a, +δ-T). Then, at this time b0, a trigger pulse TRG is generated.

As described above, according to the second embodiment of the present invention, when a plurality of cells exist within the delay fluctuation time (ΩD□8−ΩD, l, ) in the network, optimal buffer readout is started. Focusing on the fact that a plurality of cells are received by the cell disassembly device by that time, the cell disassembly device determines the buffer read start time based on a cell with a small internal delay among these received cells. This implementation method estimates based on the cell arrival interval as described above.

That is, when the first cell is received, the trigger control unit 51 starts a one-hour timer. If a cell is received within this timer, the timer is restarted when the cell is received. If no cell is received within the timer, start the timer after the timeout. Delay fluctuation (QD,,X-QD-ih
) starts reading the delay difference absorption buffer one hour after receiving the last cell within the time period.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the delay time can be minimized by minimizing the delay in the start time of reading from the delay difference absorbing buffer memory, so the capacity of the puffer memory can be reduced and the quality of communication can be improved. I can contribute.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram showing the configuration of a cell disassembly device according to the first embodiment of the present invention. FIG. 3 is a diagram showing the configuration of a signal cell. FIG. 5 is a block diagram showing the configuration of the cell excuse device according to the second embodiment of the present invention; FIG. Fig. 7 is a block diagram showing the configuration of an ATM switching system as an industrial application field of the present invention; Fig. 8 shows the output of each device in Fig. 7; It is a time chart showing. In the figure, denotes an ATM network, a cell disassembly section, a delay difference absorption buffer, a control section, a delay difference absorption delay time minimizing means, and a minimum delay time determining means.

Claims (1)

[Claims] 1. In a cell disassembly device (2) that reproduces a line information cell received via an ATM network (1) in synchronization with the generation cycle of the line information cell, the received line information cell a delay difference absorption buffer (3) that outputs after delaying the delay difference so as to satisfy a predetermined late arrival/discard rate, and a control section (4) that controls the delay difference absorption buffer (3), the control section (4) is the delay difference absorption delay time (AD) after receiving the first cell after the start of communication, and the maximum queuing delay time (Q_m_a_x) and the minimum queuing delay time (Q
_m_i_n) A characterized in that it is equipped with a delay difference absorption delay time minimizing means (5) that makes the time equal to the difference between
Line information delay difference absorption method in TM network. 2. In the system according to claim 1, the minimum delay time is determined from among the cells accumulated in the delay difference absorption buffer (3) within a predetermined time shorter than the maximum queuing delay time after the start of communication, and 1. A line information delay difference absorption system in an ATM network, comprising a minimum delay time determining means for determining a minimum delay time as a delay time between input and output of the ATM network.