JP3001493B2 - Burst circuit switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an STM (Synchronous
Transfer Mode). The present invention relates to a circuit switching technology in an STM communication network.

[0002]

2. Description of the Related Art In a burst circuit switching network in which circuit setting is performed by setting switching information of a time slot from a transmitting side, when an edge node of the network receives a packet, a destination specified by an address mounted on the packet is received. Of the edge node in which E. is accommodated. A line is set by generating 164 addresses or time slot exchange information up to that.

FIG. FIG. 6 is a diagram illustrating an example of a burst circuit switching network when generating 164 addresses. FIG. 11 is a diagram showing an example of a burst circuit switching network when generating time slot switching information.

[0004] In the burst circuit switching network shown in FIG. A path is assigned to the corresponding E.164 address, and E.164 written in the header. The data is transferred to a desired destination by writing the data in a time slot corresponding to a predetermined path corresponding to the 164 address.

Namely, in the example of FIG. 10, the communication terminal TE
IP (Internet Protocol) packets sent from
STM switch 60 at the entrance of burst circuit switching network N1
Is reached, the control device 65 provided in the STM exchange 60 controls the E.E.M. corresponding to the destination written in the IP header. 164 addresses are assigned. This E.
The 164 address is E.E. It is added to the IP header as a 164 header. In the STM exchanges 60 to 63, E. By writing the data of the packet in the time slot corresponding to the path corresponding to the 164 address, the data can be transferred to a desired destination.

In the burst circuit switching network shown in FIG.
A time slot is assigned to each route toward the TM exchanges 70 to 72.

[0007] In the STM exchange 70 at the entrance of the burst circuit switching network, time slot exchange information to a desired destination is generated in accordance with the destination information written in the IP header of the IP packet transmitted from the communication terminal TE. .
In the example of FIG. 11, the STM exchange 70 to the STM exchange 7
Up to 1, data is transferred by time slot # 1,
Data is transferred from the STM exchange 71 to the STM exchange 72 by the time slot # 4. This time slot exchange information is added to data as a header. Note that “PRE” in FIG. 11 indicates PREAMBLE. Each of the STM switches 70 to 72 has an address control memory AC.
An M (Address Control Memory) is provided, and packets can be transferred to a desired destination by writing data arriving in a predetermined time slot according to the time slot exchange information written in the header.

[0008] The burst circuit switching network mainly includes a burst circuit switching device. The burst line switching device sets its own address control memory (ACM) according to the time slot switching information sent from the transmitting side. FIG. 12 is a diagram showing an example of a conventional burst line switching device. The line is set by setting the time slot value to the address of the address control memory ACM indicated by the value placed in a certain time slot. In the example of FIG. 12, line setting is to be performed using the second time slot of the input side line, and since the head of the time slot exchange information is “3”, “3” is added to the address 3 of the address control memory ACM. 2 "is written.

As described above, the transmission side edge node of the burst circuit switching network generates the time slot exchange information up to the reception side. When a packet arrives from the sending terminal,
The transmitting-side edge node sets time slot exchange information according to the destination address of the packet header and performs line setting. Packet transfer is performed along the line thus set.

[0010]

In the conventional method of generating time slot exchange information at a transmitting edge node,
Since line setting is performed irrespective of the use state of the time slot of the link on the way, the time slot may not be captured by the link on the way. In this case, there is a problem that the line setting request is discarded on the way. Further, when the packet is discarded, the transmission side needs to perform the line setting again from the beginning, which causes a problem that the packet transfer delay time becomes long.

FIG. 9 is a diagram showing a problem in a case where only a part of time slots can be used in communication using a plurality of time slots. Further, in the case of communication using a plurality of time slots as shown in FIG. 9, when only some of the time slots can be captured by an intermediate link, the time Unable to use slot. In FIG. 9, when communication requiring two time slots can capture only one time slot, the packet is temporarily stored in the buffer device and stored in the queue A and the queue B. At this time, since only one time slot can be captured, only one of the two queues can be read. However, since the interleaved information is written in the queues A and B, if the information is read from only one of the queues (for example, the queue A), the read information becomes meaningless information.

The present invention has been made in view of such a background, and an object of the present invention is to provide a burst line switching apparatus capable of suppressing discard of a line setting request. SUMMARY OF THE INVENTION It is an object of the present invention to provide a burst circuit switching device that can reduce a packet transfer delay time. The present invention provides a burst circuit switching apparatus that can perform communication while maintaining the order of time slots even when only some of the time slots can be captured on an intermediate link for communication using a plurality of time slots. The purpose is to do.

[0013]

When a packet arrives at the burst line switching device of the present invention and a time slot of an output line indicated by the time slot switching information has no free space, a buffer device is connected. The packet is transferred to the output terminal.

The buffer device records the order in which the packets arrived. The status of the output line is monitored, and when a free time slot is created, the buffer device is notified. Upon receiving the notification, the buffer device transfers the oldest packet destined for the output line.

When a packet arrives at the burst line switching apparatus of the present invention and there is no available time slot in the output line indicated by the time slot switching information, the output terminal to which the buffer device is connected is connected to the output terminal. The packet is forwarded. The buffer device generates a queue for the packet and starts a timer. When the timer finishes counting, the packet is transferred to the input terminal again. The packet transferred from the buffer device issues a line setting request to the switching device again.
At this time, if there is an empty time slot on the line, the packet is serviced, but if there is no empty time slot again, the packet returns to the buffer device.

In the case of a setting request to the same output line from two or more time slots on the same or different lines, the slot switching device between the burst line switching device and the buffer device converts these time slots from these time slots. Can be stored in the same logical queue. Thereby, for a communication requiring a plurality of time slots, the time slots can be stored in the buffer device while maintaining the order of the time slots.

That is, a first aspect of the present invention is a burst circuit switching apparatus provided with means for transferring a packet to a predetermined time slot in accordance with the destination of an incoming packet. A feature of the present invention resides in that a means for monitoring the vacancy status of a time slot and a buffer for temporarily storing a packet to be loaded in the time slot when the predetermined time slot is not vacant are provided.

Thus, for example, when this packet is a packet used for a line setting request, it is possible to avoid that the line setting request does not reach the other party due to discarding of the packet. Further, retransmission of a packet that occurs when a packet is discarded can be eliminated, so that a packet transfer delay time can be reduced.

It is preferable that the apparatus further comprises means for reading the packet from the buffer when the predetermined time slot becomes available according to the monitoring result of the monitoring means.

At this time, there is provided means for storing the storage order of the packets in the buffer, and the reading means reads the packet in the order from the previous one in accordance with the storage order in the buffer stored in the storage means. It is desirable to include a delivery means.

Further, a timer may be provided for starting time counting from the time when the packet is stored in the buffer, and the timer means may be provided with a means for reading out from the buffer the packet for which a predetermined time has been counted. it can.

Thus, it is not necessary to monitor each time whether or not a predetermined time slot is available, and the configuration of the apparatus can be simplified.

A queue may be provided for each time slot corresponding to a different path, and means for storing a plurality of packets destined for the same path in the queue of the time slot corresponding to the same path may be provided.

Thus, when one data is transferred by using a plurality of packets, the transfer order of the packets can be prevented from being changed.

[0025] A second aspect of the present invention is a burst circuit switching network provided with the burst circuit switching device.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to FIGS.
This will be described with reference to FIGS. FIG. 1 is a block diagram of a main part of a burst circuit switching apparatus according to a first embodiment of the present invention. FIG. 4 is a block diagram of a main part of a burst circuit switching apparatus according to a second embodiment of the present invention. FIG. 5 is a block diagram of a main part of a burst line switching apparatus according to a third embodiment of the present invention. FIG. 8 is a block diagram of a main part of a burst line switching apparatus according to a fourth embodiment of the present invention.

The present invention, as shown in FIG. 1, is a burst line switching apparatus provided with an address control memory (ACM) 1 which is means for transferring a packet to a predetermined time slot according to the destination of an incoming packet. . The present invention is characterized in that the output line availability monitoring unit 2 is a means for monitoring the availability of a time slot, and temporarily stores packets to be loaded in the time slot when the predetermined time slot has no availability. And a buffer section 3.

A packet sequence holding unit 4 is provided for reading out the packet from the buffer unit 3 when the predetermined time slot is vacant according to the monitoring result of the output line vacancy monitoring unit 2. The packet order holding unit 4 stores the order in which the packets are stored in the buffer unit 3 and reads out the packets in the order from the earlier according to the stored order in the buffer unit 3.

As shown in FIG. 4, a timer 5 starts counting from the time when the packet is stored in the buffer unit 3.
And the timer 5 may read from the buffer unit 3 the packet for which the measurement of the predetermined time has been completed.

As shown in FIGS. 5 and 8, queues 10-1 to 10-1 are provided for each time slot corresponding to a different route.
10-3, a plurality of packets destined for the same route are queued in a time slot queue 10 corresponding to the same route.
-I (i is an integer from 1 to 3) may be provided with a slot exchange unit 6 which is a means for storing the data in i.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing a configuration of the buffer unit 4 according to the first embodiment of the present invention. FIG. 3 is a diagram for explaining the packet order holding unit 4.

As shown in FIG. 1, the burst line switching apparatus according to the first embodiment of the present invention comprises an address control memory 1, a buffer unit 3, a packet order holding unit 4, an output line availability monitoring unit 2, and a line switching unit 50. Consists of The buffer unit 3 and the circuit switching unit 50 are connected by a time-division multiplex line, and communication can be performed between them regardless of where information is placed at each time slot position on the line.

The output line vacancy monitoring unit 2 monitors the vacancy of each output line, and when a vacant time slot is created, notifies the buffer unit 3 of the line number. When notified of the output line number for which an empty time slot has been created, the buffer unit 3 selects and transfers the oldest packet among the packets addressed to that line.

FIG. 2 shows an example of the configuration of the buffer unit 3. The buffer unit 3 includes time division multiplex blocks 11 and 12, and a queue generation block 10. The time division multiplex blocks 11 and 12 are devices for separating the time division communication path connecting the buffer unit 3 and the circuit switching unit 50 according to the order of the time slots. When a packet to be newly transferred to the buffer unit 3 is detected, the queue generation block 10 newly generates a queue and generates a correspondence between the queue number and the time slot.

FIG. 3 shows a configuration example of the packet order holding unit 4. The packet order holding unit 4 is formed of a ring-shaped register, and forms a chain at points for each output line.
When an empty slot is created in an output line, the queue at the head of the chain starts to be transferred. In FIG. 3, queues A, C, and E are sent to the output line in order, and queues B,
D indicates that the packet has arrived.

Second Embodiment The configuration of the second embodiment of the present invention will be described with reference to FIG. FIG. 4 includes a circuit switching unit 50 and a buffer unit 3, and the buffer unit 3 logically divides and holds queues 10-1 to 10-3 for each packet. Also, a timer 5 is provided for each queue. In FIG. 4, when the packet is transferred to the buffer unit 3, the queues 10-1 to 10-1
-3 is generated, and the timer 5 associated with the queues 10-1 to 10-3 is set to a predetermined value. Timer 5
Is completed, the transfer of the packet from the buffer unit 3 starts.

In the first embodiment of the present invention, it is necessary to exchange information on the output line for which an empty time slot has been created between the output line availability monitoring section 2 and the buffer section 3. In the example, since the buffer unit 3 can autonomously determine the operation, it is easy to configure a high-speed circuit.

(Third Embodiment) A third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a diagram showing the configuration of the third embodiment of the present invention. A major difference between the third embodiment of the present invention shown in FIG. 5 and the first embodiment of the present invention shown in FIG. 1 is that, in the third embodiment of the present invention, the slot switching section 6 is provided between the circuit switching section 50 and the buffer section 3. Is given. This slot exchange unit 6
Is to bundle a plurality of time slots into one logical queue. In the first and second embodiments of the present invention, the time slots and the logical queues on the time division multiplex line connecting the buffer unit 3 and the circuit switching unit 50 are connected one-to-one. This is for associating a plurality of time slots with one logical queue. In the example of FIG. 5, the second and third slots of the time division multiplex line between the circuit switching unit 50 and the buffer unit 3 are allocated to the queue A.

At this time, when information from a plurality of time slots is put into one queue, the leading time slot exchange information is written into the queue so as not to overlap. FIG. 6 is a diagram showing a situation in which the leading time slot exchange information is written in the queue so as not to overlap. In the example of FIG. 6, the second and third time-division multiplex lines between the circuit switching unit 50 and the buffer unit 3 are
The time slot exchange information arriving using the slots indicates the third, second, sixth and first. The duplicated timeslot exchange information is discarded without being written to the queue A.

The output line availability monitoring unit 2 monitors the availability of time slots for each output line, and when an empty slot is created, notifies the buffer unit 3 of the line number and the number of empty slots. When transferring a packet, the number of time slots read from the buffer unit 3 is adjusted within the range up to the number of empty slots of the maximum output line. FIG. 7 is a diagram showing a situation in which the time slot exchange information is copied and the packet is transferred. If the number of time slots to be read is plural as shown in FIG. 7, when reading is started, the packet is transferred while copying the time slot exchange information. In the example of FIG. 7, the first and second slots on the time division multiplex line from the buffer unit 3 to the circuit switching unit 50 are allocated to the queue A.

(Fourth Embodiment) A fourth embodiment of the present invention will be described with reference to FIG. A major difference between the fourth embodiment of the present invention shown in FIG. 8 and the second embodiment of the present invention shown in FIG. 4 is that a slot switching unit 6 is provided between the circuit switching unit 50 and the buffer unit 3 in FIG. Is Rukoto. The operation of the slot exchange section 6 is the same as that described in the third embodiment of the present invention.

(Summary of Embodiment) In a conventional burst line switching apparatus, when a time slot cannot be captured on a link on the way, there is a problem that the line setting request is discarded on the way. Further, when the packet is discarded, the transmission side needs to perform the line setting again from the beginning, which causes a problem that the packet transfer delay time becomes long. In the case of communication using multiple time slots, only some of the time slots are captured on the link on the way.
If the time slots cannot be caught , some of the time slots cannot be used while maintaining the order of the time slots.

In the present invention, even when a time slot cannot be captured on the way by the buffer unit 3, a line can be set up to a node on the way. By performing retransmission by an autonomous timeout by the output line availability monitoring unit 2 or the timer 5, packets can be sequentially transmitted to downstream nodes after a time slot becomes available. Therefore, the packet transfer delay time can be reduced. In addition, by installing the slot switching unit 6 on the time division multiplex line between the buffer unit 3 and the circuit switching unit 50, the order of the time slots is maintained even when communication is performed using a plurality of time slots. As it is, it is possible to communicate using some time slots.

[0044]

As described above, according to the present invention,
Discard of the line setting request can be suppressed. Therefore, since retransmitted packets can be suppressed, the packet transfer delay time can be reduced. Further, even when only a part of the time slots can be captured by a link in the middle of the communication using a plurality of time slots, the communication can be performed while maintaining the order of the time slots.

[Brief description of the drawings]

FIG. 1 is a block diagram of a main part of a burst circuit switching apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a buffer unit according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining a packet order holding unit.

FIG. 4 is a block diagram of a main part of a burst circuit switching device according to a second embodiment of the present invention.

FIG. 5 is a block diagram of a main part of a burst circuit switching device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing a situation in which the leading time slot exchange information is written in a queue so as not to overlap.

FIG. 7 is a diagram showing a situation in which time slot exchange information is copied and a packet is transferred.

FIG. 8 is a block diagram of a main part of a burst line switching apparatus according to a fourth embodiment of the present invention.

FIG. 9 is a diagram showing a problem when only a part of time slots can be used in communication using a plurality of time slots.

FIG. The figure which shows the example of the burst circuit switching network when generating a 164 address.

FIG. 11 is a diagram showing an example of a burst circuit switching network when generating time slot switching information.

FIG. 12 is a diagram showing an example of a conventional burst line switching device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address control memory 2 Output line availability monitoring unit 3 Buffer unit 4 Packet order holding unit 5 Timer 6 Slot switching unit 10-1 to 10-3 Queue generation block 11, 12 Time division multiplex block 50 Line switching unit 60 to 63 70-72 STM exchange 65 Control unit TE Communication terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 H04Q 11/04

Claims (3)

(57) [Claims] 1. A given to the header of an incoming packet
Address control memo according to time slot exchange information
Set the time slot value to the address of
In the burst circuit switching device having means for changing carrying packets to the set time slot, and means for monitoring the availability of time slots, to put in the time slot when there is no space in the predetermined time slot packet And a buffer for temporarily accumulating the packet, and starts timing from the time when the packet is accumulated in the buffer.
Timer means for starting the timer, and the timer means
Means for reading a packet whose time has been counted from the buffer
Burst line switching apparatus characterized by comprising a. Means for setting a time slot value in an address control memory in accordance with time slot exchange information given to a header of an incoming packet, setting a line, and transferring a packet to the set time slot. The burst circuit switching device includes means for monitoring the availability of a time slot, and a buffer for temporarily storing a packet to be loaded in the time slot when the predetermined time slot is not available. A burst circuit switching device comprising means for storing data in correspondence with a logical queue. 3. A burst circuit switching network comprising the burst circuit switching device according to claim 1.