JPH04127535A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make an electric field accelerating the diffusion of minor carrier of a base layer for increasing the cut-off frequency fr by a method wherein, within a heterojunction bipolar transistor, III-V compound semiconductor crystal in larger lattice constant than that of silicon comprising a base is arranged not only beneath the emitter but also a base. CONSTITUTION:A high concentration N-type buried layer 2 to be a subcollector and a high concentration P-type ion implanted layer 3 to be a channel stopper are formed on a P-type silicon substrate 1. Next, N-type epitaxial layers about 0.8mum thick and a field oxide film 4 by a LOCOS selective oxidizing process are formed. Next, a collector is composed of these N-type epitaxial layers 5 and an N-type gallium arsenide layer 6 500Angstrom thick formed on the layers 5. Furthermore, a P-type silicon layer 7 600Angstrom thick to be a base is formed while an N-type gallium arsenide layer 9 100Angstrom thick to be an emitter and an N-type polysilicon layer 10 2300Angstrom thick are formed in the opening of an oxide film 8 and then an aluminum electrodes 11 to be the base, emitter and collector electrodes are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bipolar transistors, and particularly to heterojunction bipolar transistors.

[Conventional technology]

Wide bandgap emitter type bipolar transistors, in which the emitter is made of a material wider than the forbidden band width of the material constituting the base-collector, have a high amplification factor, and are being developed as ultra-high speed and ultra-high frequency devices.

A conventional heterojunction bipolar transistor will be described with reference to FIG.

N-type epitaxial layer 5 and high concentration N-type arsenic buried layer 2
The collector consisting of the P-type epitaxial layer 7 and the base consisting of the P-type epitaxial layer 7 are both made of silicon.

On the other hand, the emitter is composed of an N-type gallium arsenide layer 9 and a heavily doped N-type polysilicon layer 10.

The presence of the gallium arsenide layer suppresses the injection of holes from the base to the emitter and improves the current amplification factor h-.

[Problem to be solved by the invention]

To improve the cutoff frequency f7, the metallurgically doped base width must be thinned to shorten the base transit time of minority carriers.

The movement of minority carriers in the neutral base (the non-depleted region of the metallurgical base) layer is controlled by diffusion, and the electric field is affected by the impurity concentration distribution and the alloy composition distribution between semiconductor materials with different forbidden band widths. Occur. This electric field affects the neutral base migration of minority carriers.

Furthermore, stress is a factor that causes an electric field to be generated in the neutral base layer. When gallium arsenide, GaAs, gallium phosphide, GaP, or the like having a larger lattice constant than silicon is used as the emitter, tensile stress is applied to the base layer near the emitter, producing a decelerating electric field. This has the disadvantage that the forbidden band width is reduced and the diffusion of minority carriers in the base layer is slowed down.

[Means to solve the problem]

By making the lattice constant of the base layer near the collector smaller than that of the collector layer near the base, the heterojunction bipolar transistor of the present invention has a critical value at which misfit dislocations occur due to lattice mismatch in the base region near the collector. The f-a is improved by applying tensile stress to reduce the forbidden band width within a range not exceeding , and by generating an electric field that accelerates the diffusion of minority carriers in the base layer.

[Effect]

Dislocations occur to relieve stress due to lattice mismatch.

To avoid this transition, there is a limit to the film thickness that can be grown.

The critical film thickness is W1, and each lattice constant of different materials is asb.
Then, (as a<b), it is expressed as follows.

〔Example〕

Next, the structure of a hetero bipolar transistor as a first embodiment of the present invention will be described with reference to the cross-sectional view of FIG. 1(C).

A heavily doped N-type buried layer 2 serving as a sub-collector and a heavily doped P-type ion-implanted layer 3 serving as a channel stopper are formed on a P-type silicon substrate 1 having a specific resistance of 10 to 20 Ω·Cm.

An N-type epitaxial layer 5 having a concentration of lXl0"cm-3 and a thickness of about 0.8 μm is formed, and a field oxide film 4 is formed by the LOGO8 selective oxidation method. The concentration is 2X10
An N-type gallium arsenide layer 6 having a thickness of 500 cm and a thickness of 500 cm forms the collector.

Furthermore, the base concentration is 2X10"cm-' and the thickness is 6
A P-type silicon layer 7 of 0.000 nm is formed in the opening of the oxide film 8 to serve as an emitter with a concentration of 2×10'8 cm-3 and a thickness of 10.
0N type gallium arsenide layer 9 and concentration 5X10"cm-
3. Seven N-type polysilicone layers 10 having a thickness of 2300 nm are formed, and aluminum electrodes 11 serving as base, emitter, and collector electrodes are formed.

FIG. 2 shows the lattice constant in the depth direction from the emitter electrode.

It consists of 2,300 N-type polysilicon layers for the emitter, 100 N-type GaAs layers for the hole barrier, 600 P-type polysilicon layers for the base, and 500 N-type GaAS layers for the collector.

Next, a method for manufacturing a hetero bipolar transistor, which is an embodiment of the present invention, will be explained with reference to FIGS. 1(a) to 1(C).

First, as shown in FIG. 1(a), an arsenic buried layer 2 and a boron buried layer 3 are formed on a P-type silicon substrate 1, and an N-type epitaxial layer 5 is grown.

A field oxide film 4 is formed by the LOGO8 selective oxidation method using a nitride film (not shown) as a mask, and then selectively applied to the opening of the N-type epitaxial layer 5 in a molecular beam epitaxial (MBE) apparatus. An N-type single crystal gallium arsenide layer 8 and a P-type wheel crystal silicon layer 7 are grown.

When selective growth is not possible like in gas source MBE,
After depositing on the entire surface, use photoresist as a mask and R
Unnecessary P-type silicon layer 7 and N-type gallium arsenide layer 6 are removed by dry etching such as IE method.

Next, as shown in FIG. 1(b), an oxide film 8 is deposited on the P-type silicon layer 7 that will serve as the base, and after opening the intended emitter region by photolithography, the oxide film 8 is continuously deposited in the MBE apparatus. An N-type single crystal gallium arsenide layer 9 and a high concentration N-type polysilicon layer 10 are grown.

Next, as shown in FIG. 1C, the heavily doped N-type polysilicon layer 10 and the N-type gallium arsenide layer 9 other than the emitter region are removed by dry etching such as RIE using a photoresist as a mask.

Next, after opening the base and collector parts, aluminum or the like is deposited on the entire surface, and then aluminum electrodes 11 are formed by a photolithography process to complete the element part.

〔Effect of the invention〕

In a heterojunction bipolar transistor, a ■-■ group compound semiconductor crystal, which has a larger lattice constant than the silicon constituting the base, is arranged not only at the emitter but also under the base. Tensile stress can be applied to the base region near the collector to alleviate the retarding electric field. This has the effect of reducing the forbidden band width of the base, generating an electric field inside the base, and shortening the time required for minority carriers to travel through the base.

[Brief explanation of drawings]

FIGS. 1(a) to (C) are cross-sectional views showing an embodiment of the present invention in the order of steps, FIG. 2 is a distribution of lattice constants in the depth direction of an emitter longitudinal section in an embodiment of the present invention, and FIG. 1 is a cross-sectional view of a heterojunction bipolar transistor according to the prior art; FIG. 1... P-type silicon substrate, 2... N-type arsenic buried layer,
3... P-type boron buried layer, 4... Field oxide film,
5... N-type epitaxial layer, 6... N-type gallium arsenide layer, 7... P-type silicon base layer, 8... Oxide film, 9... N-type gallium arsenide layer, 10... High concentration N
Type polysilicon layer, 11...aluminum electrode.

Claims (1)

[Claims] 1. A first conductivity type III selectively formed on a group IV single-element semiconductor substrate.
- a group V compound semiconductor single crystal first island region is formed; a second conductivity type group IV single element semiconductor single crystal second island region is formed on the first island region; and a second conductivity type group IV single element semiconductor single crystal second island region; A first semiconductor having a wider forbidden band width than the Group IV semiconductor constituting the second island region is formed on the top.
A conductivity type III-V group compound semiconductor third island region is formed, and the lattice constants of the single crystal materials constituting the first island region, the second island region, and the third island region are respectively a_1,
When a_2 and a_3 and the thicknesses are W_1, W_2 and W_3, W_1<a_1^2/|a_1-a_2| W_2<a_2^2/|a_2-a_1| and W_2<a_2^2/|a_3-a_2 |W_3<
a_3^2/|a_3-a_2|, forming a heterojunction bipolar transistor in which the first island region is a collector, the second island region is a base, and the third island region is an emitter. semiconductor device. 2. The first conductivity type is in contact with at least a part of the third island region.
The semiconductor according to claim 1, wherein a fourth group IV polycrystalline island region is formed, the first island region is a collector, the second island region is a base, and the third island region and the fourth island region are emitters. Device.