JPH04127436A - Formation of bump - Google Patents
Formation of bumpInfo
- Publication number
- JPH04127436A JPH04127436A JP2249594A JP24959490A JPH04127436A JP H04127436 A JPH04127436 A JP H04127436A JP 2249594 A JP2249594 A JP 2249594A JP 24959490 A JP24959490 A JP 24959490A JP H04127436 A JPH04127436 A JP H04127436A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- electrode pad
- barrier metal
- melting point
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000003960 organic solvent Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 claims description 16
- 238000012856 packing Methods 0.000 claims description 3
- 230000004888 barrier function Effects 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 230000004907 flux Effects 0.000 abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 238000009713 electroplating Methods 0.000 abstract description 3
- 239000000463 material Substances 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 230000008018 melting Effects 0.000 description 15
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 12
- 235000011187 glycerol Nutrition 0.000 description 6
- 238000009835 boiling Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置を７リツプチツプボンデイングに
より実装する際の半田バンプの形成方法に関するもので
、融点の高い半田バンプの形成に特に有用なものである
。Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a method for forming solder bumps when a semiconductor device is mounted by 7-lip chip bonding, and is particularly useful for forming solder bumps with a high melting point. It is something.
（従来の技術）
近年、半導体装置の接続端子数は増加の傾向にあり、Ｌ
、ＳＩチップの全面に接続端子を設ける７リツプチツプ
ボンデイング方式が広く使用されている、その接続端子
の形態によってボール方式。(Prior art) In recent years, the number of connection terminals for semiconductor devices has been increasing, and
The 7-lip chip bonding method, in which connection terminals are provided on the entire surface of the SI chip, is widely used, and the ball method is used depending on the form of the connection terminals.
ペデスタル方式、バンプ方式等があるが、バンプ方式が
一般に使用され、バンプの材料としてはＡｔ、Ｃｕ、Ａ
ｇ、Ｓｎ、Ｐｂ又は半田等が使用さレル。There are pedestal methods, bump methods, etc., but the bump method is generally used, and the bump materials include At, Cu, and A.
G, Sn, Pb or solder are used.
本発明はこの半田バンブの形成方法の改良に係るもので
ある。半田バンプは、−船釣に、ＬＳＩチップの電極パ
ッド上に電解めっき法や蒸着法等によって形成される。The present invention relates to an improvement in the method for forming solder bumps. The solder bumps are formed on the electrode pads of the LSI chip by electrolytic plating, vapor deposition, or the like.
第２図（ａ）及び（ｂ）はその形成方法の一例の工程を
示すものである。第２図（ａ）において、半導体基板１
の表面には集積回路が形成されており、その電極パッド
２の上部にバリアメタルｌ＃４を介して耳状の半田層７
が形成されている。電極パッド２以外の表面は絶縁層８
によって被覆されている。半田層７の成分がＳｎ：Ｐｂ
＝６：４の共晶組成（融点：１８８℃）の場合、前記の
半田層７を還元力を有する有機溶剤、例えばグリセリン
の高温溶液（温度；２００℃以上）に浸漬するグリセリ
ン法を用い、−旦半田の融点以上に加熱し冷却するウェ
ットパック法により、表面張力を利用してｖＪ２図（ｂ
）に示されるように半田層７を半球状にしてバンプを形
成していた。FIGS. 2(a) and 2(b) show steps of an example of a method for forming the same. In FIG. 2(a), a semiconductor substrate 1
An integrated circuit is formed on the surface of the electrode pad 2, and an ear-shaped solder layer 7 is formed on the top of the electrode pad 2 via a barrier metal l#4.
is formed. The surface other than the electrode pad 2 is an insulating layer 8
covered by. The components of the solder layer 7 are Sn:Pb
In the case of a eutectic composition of = 6:4 (melting point: 188°C), a glycerin method is used in which the solder layer 7 is immersed in a high-temperature solution (temperature: 200°C or higher) of an organic solvent having reducing power, such as glycerin. - Using the wet pack method, which heats the solder above its melting point and then cools it, the vJ2 diagram (b)
), the solder layer 7 was made into a hemispherical shape to form a bump.
耐熱性を要する半導体装置には高融点の半田を使用する
必要がある。例えば半田の組成比がｓｎ：Ｐｂ＝５：９
５のような高融点半田をバンプとして使用する場合、そ
の融点（８０５℃）はグリセリンの沸点（２９０℃）以
上になるため、グリセリン法によるウェットパックは行
えない。そのため、高融点半田のウェットパックには、
リフロー炉を使用することが多い。Semiconductor devices that require heat resistance must use solder with a high melting point. For example, the composition ratio of solder is sn:Pb=5:9
When a high melting point solder such as No. 5 is used as a bump, its melting point (805° C.) is higher than the boiling point of glycerin (290° C.), so wet packing using the glycerin method cannot be performed. Therefore, the wet pack of high melting point solder requires
A reflow oven is often used.
（発明が解決しようとする課題）
前述のように、高融点半田を用いたバンプを、す７０−
炉を使用して、ウェットパックにより形成する場合は、
適当なフラックスを塗布した第２図（８）の状態のウェ
ーハを、約８２０℃ＭＡＸの温度プロファイルを有する
リフロー炉に通し、その後溶剤によってフラックスの洗
浄を行わなければならない。そのため、洗浄不良による
フラックス残渣の影響でＬＳＩの電気的な信頼性が低下
する危険性があり、歩留り低下を来す原因となっていた
。(Problems to be Solved by the Invention) As mentioned above, bumps using high melting point solder are
When forming by wet pack using a furnace,
The wafer in the state shown in FIG. 2 (8) coated with a suitable flux is passed through a reflow oven having a temperature profile of about 820° C. MAX, and then the flux must be cleaned with a solvent. Therefore, there is a risk that the electrical reliability of the LSI will be lowered due to the influence of flux residue due to poor cleaning, causing a decrease in yield.
（課題を解決するための手段）
前述の課題を解決するため、本発明においては、バンプ
材料として高融点半田を用い、加圧した高温の還元力を
有する有機溶剤浴を行ってウェットパックを施した。(Means for Solving the Problem) In order to solve the above-mentioned problem, in the present invention, a high melting point solder is used as the bump material, and a wet pack is applied by applying a pressurized high temperature organic solvent bath having reducing power. did.
（作 用〕
加圧された有機溶剤はその沸点が上昇するため、その圧
力を調節することにより、高融点半田の融点以上にその
沸点を制御できるから、常圧では使用できなかった有機
溶剤中でも、ウェットパックを行うことができる。(Function) The boiling point of a pressurized organic solvent increases, so by adjusting the pressure, the boiling point can be controlled to a level higher than the melting point of high melting point solder, so even organic solvents that cannot be used at normal pressure can be used. , you can do a wet pack.
（実施例）
第１図（ａ）乃至（ｆ）は本発明の一実施例の各工程を
示す略断面図である。従来の方法と異なる所はウェット
パックの工程である。(Embodiment) FIGS. 1(a) to 1(f) are schematic cross-sectional views showing each step of an embodiment of the present invention. The difference from the conventional method is the wet pack process.
まず、第１図（ａ） Ｋ示されるように、半導体基板１
の表面に形成された集積回路の全面を被覆する絶縁層８
に、電極パッド２の表面を露出するように、窓を設ける
。First, as shown in FIG. 1(a), a semiconductor substrate 1 is
an insulating layer 8 covering the entire surface of the integrated circuit formed on the surface of the integrated circuit;
A window is provided to expose the surface of the electrode pad 2.
次に第１図（ｂ）に示されるように、全面にバリアメタ
ル層４を、例えばスパッタリングにより形成する。バリ
アメタルとしては、Ｔｉ、Ｃｕ等が使用される。Next, as shown in FIG. 1(b), a barrier metal layer 4 is formed on the entire surface by, for example, sputtering. Ti, Cu, etc. are used as the barrier metal.
次に第１図（ｃ）ＶＣ示されるように、全面に塗布され
たフォトレジス）６ｆＣＳ［極パッド２の表面のみ開口
するように、パターニングする。Next, as shown in FIG. 1(c) VC, the photoresist (6fCS) coated on the entire surface is patterned so that only the surface of the electrode pad 2 is opened.
次に第１図（ｄ）Ｋ示されるように、例えば電解めっき
により、電極パッド２上に高融点半田層６を堆積する。Next, as shown in FIG. 1(d)K, a high melting point solder layer 6 is deposited on the electrode pad 2 by, for example, electrolytic plating.
次に７オトレジスト５を剥離し、さらに半田めっき部以
外のバリアメタルをエツチングにより除去すると、第１
図（ｅ）ＶＣ示される状態となる。これは第２図（ａ）
に対応する。Next, the 7th photoresist 5 is peeled off, and the barrier metal other than the solder plated area is removed by etching.
Figure (e) VC is in the state shown. This is Figure 2(a)
corresponds to
次に８ ａｔｍ、 ８２０℃のグリセリン浴に浸漬して
、高融点半田層６をウェットパックすると、第１図（ｆ
）に示されるような形伏となる。これは第２図（ｂ）に
対応する。Next, the high melting point solder layer 6 is wet-packed by immersing it in a glycerin bath at 820° C. at 8 atm.
). This corresponds to FIG. 2(b).
（発明の効果）
以上のように、本発明によれば高融点半田のウェットパ
ックを、リフロー炉によらずグリセリン浴中で行えるた
め、工程が簡単であり、しかもフラックスを使用しない
ため、フラックス残渣によるＬＳＩ素子特性の低下がな
く、信頼性を大幅に向上することができる。(Effects of the Invention) As described above, according to the present invention, wet packing of high melting point solder can be performed in a glycerin bath without using a reflow oven, so the process is simple, and since no flux is used, flux residue is eliminated. There is no deterioration in LSI device characteristics caused by this, and reliability can be greatly improved.
第１図（ａ）乃至（ｆ）は本発明の一実施例の各工程の
略断面図、第２図（ａ） ｒ （ｂ）はそれぞれ従来の
半田バンプのウェットパックの前後を示す略断面図であ
る。
ｌ・・・半導体基板、２・・・電極パッド、８・・・絶
縁層、４・・・バリアメタル層、５・・・フォトレジス
ト、６・・・高融点半田層、７・・・半田層
（り
第
（ａ）
纂
（ｅ）FIGS. 1(a) to (f) are schematic cross-sectional views of each process of an embodiment of the present invention, and FIGS. 2(a) and (b) are schematic cross-sectional views showing the front and back of a conventional solder bump wet pack, respectively. It is a diagram. l... Semiconductor substrate, 2... Electrode pad, 8... Insulating layer, 4... Barrier metal layer, 5... Photoresist, 6... High melting point solder layer, 7... Solder Layer (a) (e)
Claims (1)
上に形成した高融点半田層を、加圧した高温の還元力を
有する有機溶剤を用いてウェットパックすることを特徴
とするバンプの形成方法1. A bump formation method characterized by wet-packing a high-melting point solder layer formed on an electrode pad of an integrated circuit formed on the surface of a semiconductor substrate using a pressurized high-temperature organic solvent having reducing power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2249594A JPH04127436A (en) | 1990-09-18 | 1990-09-18 | Formation of bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2249594A JPH04127436A (en) | 1990-09-18 | 1990-09-18 | Formation of bump |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04127436A true JPH04127436A (en) | 1992-04-28 |
Family
ID=17195341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2249594A Pending JPH04127436A (en) | 1990-09-18 | 1990-09-18 | Formation of bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04127436A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996008337A1 (en) * | 1994-09-15 | 1996-03-21 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of applying solder to connection surfaces, and method of producing a solder alloy |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
-
1990
- 1990-09-18 JP JP2249594A patent/JPH04127436A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1996008337A1 (en) * | 1994-09-15 | 1996-03-21 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Method of applying solder to connection surfaces, and method of producing a solder alloy |
| US6070788A (en) * | 1994-09-15 | 2000-06-06 | Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. | Method of soldering terminal faces, as well as a method of manufacturing a solder alloy |
| US6461953B1 (en) | 1998-08-10 | 2002-10-08 | Fujitsu Limited | Solder bump forming method, electronic component mounting method, and electronic component mounting structure |
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