JPH04125933A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04125933A JPH04125933A JP24644690A JP24644690A JPH04125933A JP H04125933 A JPH04125933 A JP H04125933A JP 24644690 A JP24644690 A JP 24644690A JP 24644690 A JP24644690 A JP 24644690A JP H04125933 A JPH04125933 A JP H04125933A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- heat treatment
- diffused
- low lifetime
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000002245 particle Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 230000001678 irradiating effect Effects 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- 239000012141 concentrate Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- 229910052742 iron Inorganic materials 0.000 claims description 2
- 229910052717 sulfur Inorganic materials 0.000 claims description 2
- 229910052725 zinc Inorganic materials 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 17
- 238000009792 diffusion process Methods 0.000 abstract description 12
- 230000001133 acceleration Effects 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 18
- 238000005516 engineering process Methods 0.000 description 12
- 230000007547 defect Effects 0.000 description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000004807 localization Effects 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000003057 platinum Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8611—Planar PN junction diodes
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明はキャリアの低ライフタイム層の局在化技術に係
わる半導体装置、特に高速スイッチング素子の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, particularly a high-speed switching element, related to a technique for localizing a low lifetime layer of carriers.
（従来の技術）
半導体高速スイッチング素子においては、一般に、キャ
リアの低ライフタイム層を半導体基板中に形成し、キャ
リアの消失を速め、スイッチング速度を上げることが行
われる。(Prior Art) In semiconductor high-speed switching devices, generally a low carrier lifetime layer is formed in a semiconductor substrate to accelerate carrier disappearance and increase switching speed.
この低ライフタイム層の形成技術としては、従来、白金
拡散技術、電子照射技術、プロトン照射技術等によるも
のがある。Conventional techniques for forming this low lifetime layer include platinum diffusion technology, electron irradiation technology, proton irradiation technology, and the like.
白金拡散技術によるものは、基板における素子の形成さ
れている面から白金を拡散させ、この白金により形成さ
れるデイ−ブレベル（ｄｅｅｐ １ｅｖｅｌ ：深い準
位）によりキャリアのライフタイムを制御するものであ
る。In the platinum diffusion technology, platinum is diffused from the surface of the substrate where the elements are formed, and the carrier lifetime is controlled by the deep level (deep level) formed by this platinum. .
電子照射技術によるものは、基板に電子を照射し通過さ
せ、この通過によって基板内部に欠陥をつくり、この欠
陥をもって素子全体に低ライフタイム層を形成するもの
である。In the electron irradiation technology, a substrate is irradiated with electrons, and the electrons pass through the substrate, creating defects inside the substrate, and these defects form a low lifetime layer over the entire device.
プロトン照射技術によるものは、基板に対し所定元素の
プロトンを照射し、その基板中における停止領域に形成
された欠陥を用いて低ライフタイム層を形成するもので
ある。In the proton irradiation technique, a substrate is irradiated with protons of a predetermined element, and a low lifetime layer is formed using defects formed in a stop region in the substrate.
第４図（ａ）〜（Ｃ）は各技術による低ライフタイム層
を持つ素子を示すものである。FIGS. 4(a) to 4(c) show devices having low lifetime layers according to each technology.
まず第４図（ａ）は白金拡散技術によるものであって、
この図において、３０１は一つの導電性を有する例えば
ｎ型のシリコン基板である。この基板３０１内の表面部
には例えば硼素拡散によるｐ型の反導電性半導体層３０
２が形成されているとともに、同基板３０１の表面上に
は熱酸化膜３０３が形成されている。反導電性半導体層
３０２上にはＡＩ電極３０４が形成され、基板３０１の
裏面には裏面電極３０５が形成されている。First, Figure 4(a) is based on platinum diffusion technology,
In this figure, 301 is an n-type silicon substrate having one conductivity, for example. On the surface of this substrate 301, a p-type anti-conductive semiconductor layer 30 is formed by boron diffusion, for example.
A thermal oxide film 303 is also formed on the surface of the substrate 301. An AI electrode 304 is formed on the anti-conductive semiconductor layer 302, and a back electrode 305 is formed on the back surface of the substrate 301.
そして、基板３０１には素子形成面側に白金拡散による
低ライフタイム層３０６が形成されている。A low lifetime layer 306 formed by diffusion of platinum is formed on the element forming surface of the substrate 301.
第４図（ｂ）は電子照射技術による低ライフタイム層を
持つ素子を示すものである。FIG. 4(b) shows an element having a low lifetime layer produced by electron irradiation technology.
この電子照射技術による場合には、基板３０１全体に亘
り低ライフタイム層３０６が形成されている。When this electron irradiation technique is used, a low lifetime layer 306 is formed over the entire substrate 301.
第４図（ｃ）ははプロトン照射技術によるものを示して
いる。FIG. 4(c) shows the proton irradiation technique.
このプロトン照射技術による場合には、低ライフタイム
層３０６が基板３０１のプロトン停止領域に局在してい
る。With this proton irradiation technique, the low lifetime layer 306 is localized in the proton stopping region of the substrate 301.
以上の３技術によれば、半導体基板中にキャリアの低ラ
イフタイム層を形成し、素子の高速スイッチング動作を
得ることができる。According to the above three techniques, a low carrier lifetime layer can be formed in a semiconductor substrate, and high-speed switching operation of an element can be obtained.
しかしながら、これらの技術にはそれぞれ次のような問
題がある。However, each of these techniques has the following problems.
まず、低ライフタイム層はこれによる基板の欠陥度合い
に応じただけ素子のスイッチング速度を向上させるが、
この欠陥の度合いが高い程、基板の抵抗率が上がり電圧
降下を増加させることとなり、結果として素子のオン電
圧を上昇させてしまうため、あまり欠陥度合いを高める
ことはできない。First, the low lifetime layer improves the switching speed of the device according to the degree of defects in the substrate.
The higher the degree of defects, the higher the resistivity of the substrate increases and the voltage drop increases, resulting in an increase in the on-voltage of the element, so it is not possible to increase the degree of defects very much.
また、キャリアは基板の特定の位置に集中する性質があ
るため、低ライフタイム層はその位置に局在化させれば
足りるものである。Furthermore, since carriers have the property of concentrating at a specific position on the substrate, it is sufficient to localize the low lifetime layer at that position.
しかし、白金拡散技術による場合は、基板３０１表面か
らの拡散領域に、電子線照射技術による場合には基板３
０１全体に欠陥を形成することとなるために、キャリア
のあまり存在しない位置にまで欠陥を生じさせ、その分
、無駄に基板の抵抗率を高めることとなっており、結局
、スイッチング速度がその分制限されることとなってい
る。However, when using platinum diffusion technology, the diffusion region from the surface of the substrate 301, when using electron beam irradiation technology,
Since defects are formed in the entire 01, defects are also generated in positions where there are few carriers, which unnecessarily increases the resistivity of the substrate, and in the end, the switching speed decreases by that amount. It is to be restricted.
また、プロトン照射技術による場合には、低ライフタイ
ム層を基板３０１の深さ方向の任意位置に局在化できる
が、照射ダメージによる欠陥しかできないため、電子及
び正孔の捕獲準位が決まってしまい素子の設計範囲が狭
くなるという問題がある。In addition, in the case of proton irradiation technology, the low lifetime layer can be localized at any position in the depth direction of the substrate 301, but since only defects are created due to irradiation damage, the trapping levels of electrons and holes are not fixed. There is a problem that the design range of the closing element becomes narrow.
（発明が解決しようとする課題）
このように従来の低ライフタイム層の形成技術では、そ
の局在化を犠牲にすればいたずらに基板の抵抗率を高め
てスイッチング速度が制限され、局在化を取ればプロト
ン照射によるはかなく電子・正孔の捕獲準位が決まって
しまい素子の設計範囲が狭くなるという問題がある。(Problem to be solved by the invention) In this way, with the conventional formation technology of a low lifetime layer, if the localization is sacrificed, the resistivity of the substrate is unnecessarily increased, which limits the switching speed. If it is removed, the capture level of electrons and holes will be fixed temporarily due to proton irradiation, which will narrow the design range of the device.
本発明は、このような問題点に鑑みてなされたもので、
その目的とするところは、様々な電子・正孔の捕獲準位
を形成し素子の中に低ライフタイム層を局在化させるこ
とができる半導体装置の製造方法を提供することにある
。The present invention was made in view of these problems, and
The purpose is to provide a method for manufacturing a semiconductor device that can form various electron/hole trapping levels and localize a low lifetime layer within the device.
（課、題を解決するための手段）
本発明の半導体装置の製造方法は、不純物元素を半導体
基板に付着あるいは拡散させる工程と、半導体基板に軽
元素の荷電粒子を照射し、この半導体基板における荷電
粒子の停止領域にゲッタ層を形成し且つその半導体基板
を熱処理してゲッタ層に上記不純物元素を集中させて低
ライフタイム層を形成する工程とを含んでいる。(Means for Solving Issues and Problems) The method for manufacturing a semiconductor device of the present invention includes a step of attaching or diffusing an impurity element to a semiconductor substrate, and irradiating the semiconductor substrate with charged particles of a light element. The method includes the steps of forming a getter layer in the charged particle stopping region and heat-treating the semiconductor substrate to concentrate the impurity elements in the getter layer to form a low lifetime layer.
上記不純物金属元素としては、Ａｕ（金）、ｐｔ（白金
）、Ｃｕ（銅）、Ｓ（硫黄）、Ａｇ（銀）、Ｍｎ（マン
ガン）、Ｆｅ（鉄） 、Ｚ ｎ（亜鉛）、ＴＩ（タリウ
ム）、Ｉｎ（インジウム）、Ｇａ（ガリウム）、ＡＩ（
アルミニウム）のうち少なくとも一つを使用する。The above impurity metal elements include Au (gold), pt (platinum), Cu (copper), S (sulfur), Ag (silver), Mn (manganese), Fe (iron), Zn (zinc), TI ( thallium), In (indium), Ga (gallium), AI (
aluminum).
（作 用）
半導体基板中に荷電粒子を照射した場合、その粒子の停
止領域に不純物のゲッタ層が形成され、熱処理により容
易に重金属等の不純物を荷電粒子の停止領域に集中させ
ることができる。(Function) When charged particles are irradiated into a semiconductor substrate, a getter layer of impurities is formed in the region where the particles stop, and impurities such as heavy metals can be easily concentrated in the region where the charged particles stop by heat treatment.
本発明は、このような現象を利用したものであり、本発
明によれば、不純物元素を半導体基板に付着あるいは拡
散させておき、軽元素の荷電粒子を照射して不純物のゲ
ッタ層を形成し、熱処理によって上記不純物元素を集中
させることにより低ライフタイム層を形成するため荷電
粒子の照射エネルギの調整により基板中の希望の深さに
低ライフタイム層を形成することができ且つその低ライ
フタイム層を形成する不純物の種類を選択することで希
望のデイ−プレベルを形成することができるので素子の
設計範囲か限定されず、電子・正孔の様々な捕獲準位と
素子の中に局在化させることができ、低オン電圧の高速
スイッチング素子を形成することができる。The present invention utilizes such a phenomenon, and according to the present invention, an impurity element is attached or diffused onto a semiconductor substrate, and a getter layer of the impurity is formed by irradiating the semiconductor substrate with charged particles of a light element. Since a low lifetime layer is formed by concentrating the impurity elements through heat treatment, the low lifetime layer can be formed at a desired depth in the substrate by adjusting the irradiation energy of charged particles. The desired depth level can be formed by selecting the type of impurity that forms the layer, so it is not limited to the design range of the device, and it can be applied to various trapping levels of electrons and holes and localization within the device. It is possible to form a high-speed switching element with a low on-voltage.
また、荷電粒子として軽元素（例えば、Ｈ，Ｄ、Ｈｅ等
）のもの（Ｈ＋、Ｄ＋、Ｈｅ２＋等）を利用しているた
め、熱処理によってその粒子を容易に基板中から放出さ
せることができ、照射粒子による素子の劣化を軽減する
ことができる。In addition, since light elements (for example, H, D, He, etc.) (H+, D+, He2+, etc.) are used as charged particles, the particles can be easily released from the substrate by heat treatment. Deterioration of the element due to irradiated particles can be reduced.
（実施例）
以下に本発明の実施例について図面を参照しつつ説明す
る。(Example) Examples of the present invention will be described below with reference to the drawings.
第１図（ａ）において、１０１はｎ型、２Ω・ｍのシリ
コン基板である。この基板１０１上にはｐｔ膜１０２が
形成されている。In FIG. 1(a), 101 is an n-type, 2Ω·m silicon substrate. A PT film 102 is formed on this substrate 101.
このｐｔ膜１０２が形成されている状態で、基板１０１
を４８０°ＣのＮ２雰囲気中で２０分の熱処理を行った
後、ｐｔ膜１０２を剥離する。その後、さらに８８０°
ＣのＮ２雰囲気中で６０分の熱処理を行う。これにより
、ｐｔは基板１０１の表面部から内方へと拡散される。With this PT film 102 formed, the substrate 101
After performing heat treatment for 20 minutes in a N2 atmosphere at 480° C., the PT film 102 is peeled off. Then another 880°
Heat treatment is performed for 60 minutes in a N2 atmosphere of C. As a result, pt is diffused inward from the surface of the substrate 101.
第１図（ｂ）はそのｐｔが拡散された状態を示しており
、符号１０３はその拡散された範囲を示している。FIG. 1(b) shows the state in which the pt has been spread, and reference numeral 103 indicates the range in which it has been spread.
その状態で、基板１０１にプロトンを、例えば、ドーズ
量５Ｘ１０”、エネルギＩＭｅＶの条件で照射してゲッ
タ層を形成する。このプロトン照射条件は、基板１０１
におけるキャリアの集中する位置に応じて選定する。In this state, a getter layer is formed by irradiating the substrate 101 with protons at a dose of 5 x 10'' and an energy of IMeV, for example.
The selection will be made according to the location where careers are concentrated.
その後、基板１０１について、１０００°ＣのＮ２雰囲
気中で６０分の熱処理を行い、拡散ｐｔをゲッタ層に集
中させ、このｐｔによる低ライフタイム層を形成する。Thereafter, the substrate 101 is subjected to a heat treatment for 60 minutes at 1000° C. in an N2 atmosphere to concentrate the diffused PT in the getter layer and form a low lifetime layer of this PT.
なお、かかるプロトン照射と熱処理とは並行して行って
もかまわない。Note that such proton irradiation and heat treatment may be performed in parallel.
第１図（Ｃ）はこの低ライフタイム層が形成されている
状態を示しており、符号１０４で示す範囲に低ライフタ
イム層が形成されている。FIG. 1C shows a state in which this low lifetime layer is formed, and the low lifetime layer is formed in the range indicated by reference numeral 104.
第３図はｐｔ濃度のプロファイルをｐｔ拡散終了時と、
その次のプロトン照射および熱処理後との両時点につい
て示すものである。Figure 3 shows the pt concentration profile at the end of pt diffusion, and
This figure shows both the subsequent proton irradiation and the heat treatment.
従来のｐｔ拡散技術においては、第３図のプロトン照射
前の状態に対応し、基板の表面からその付近のＰｔ濃度
が高く基板の深さ方向に局在化されていない。この場合
、数〔μｍ〕の深さでシムスと呼ばれる質量分析器の検
出限界に達してしまう。In the conventional pt diffusion technique, corresponding to the state before proton irradiation shown in FIG. 3, the Pt concentration is high from the surface of the substrate to the vicinity thereof and is not localized in the depth direction of the substrate. In this case, the detection limit of a mass spectrometer called SIMS is reached at a depth of several μm.
本発明のプロセス（ｐｔ拡散十プロトン照射十熱処理）
の場合、第３図のプロトン照射及び熱処理（１０００（
’ Ｃ） 、２時間）を行った後の状態に対応する。こ
の図に示されるように、Ｐｔの濃度プロファイルがプロ
トンの停止領域（深さ２０〔μｍ〕付近）で局在化する
ことになる。Process of the present invention (pt diffusion, proton irradiation, heat treatment)
In the case of , proton irradiation and heat treatment (1000 (
' C) corresponds to the state after 2 hours). As shown in this figure, the Pt concentration profile is localized in the proton stopping region (at a depth of around 20 [μm]).
このｐｔの局在化される幅はプロトンのドーズ量で制御
することができ、また基板表面からの深さは加速エネル
ギで制御することができる。The width of this localized pt can be controlled by the proton dose, and the depth from the substrate surface can be controlled by the acceleration energy.
よって、本実施例によれば、拡散させる不純物（例えば
、ＡＵＳＰｔＳＣＬ１％ 、ＡｇＳＭｎ。Therefore, according to this embodiment, the impurity to be diffused (for example, AUSPtSCL1%, AgSMn.
Ｆｅ、ＺｎＳＴｌ、Ｉ ｎ ％ Ｇ ａ ｓ Ａ １等
）とプロトン照射条件（ドーズ量、加速電圧）を選ぶこ
とにより、任意のデイ−プレベルを任意の領域に形成す
ることができるため、半導体装置の設計範囲が広がり、
電子・正孔の様々な捕獲準位素子の中に低ライフタイム
層を局在化させることができ、低オン電圧の高速スイッ
チング素子を形成することができる。By selecting the proton irradiation conditions (dose amount, accelerating voltage) and the proton irradiation conditions (dose amount, accelerating voltage), it is possible to form any deep level in any region. The design scope has expanded,
A low lifetime layer can be localized in various trapping level devices for electrons and holes, and a high-speed switching device with a low on-voltage can be formed.
また、プロトン照射の際に照射する荷電粒子としてＨ，
Ｄ等の軽元素を利用しているために、この荷電粒子は１
０００ ［’ Ｃ） 、６０分の熱処理を加えることで
基板外へ容易に放出させることができ、照射粒子による
素子の劣化が軽減されることとなる。In addition, as charged particles irradiated during proton irradiation, H,
Because light elements such as D are used, this charged particle is 1
000['C), by applying heat treatment for 60 minutes, it can be easily released to the outside of the substrate, and deterioration of the element due to irradiated particles can be reduced.
つまり、荷電粒子のゲッタ効果については、従来、幾つ
かの文献に記されている。例えば、（１） Ｈ，Ｗｏ
ｎｇ ａｎｄ Ｎ、Ｗ、Ｃｈｅｕｎｇ。In other words, the getter effect of charged particles has been described in several documents. For example, (1) H,Wo
ng and N, W, Cheung.
Ａｐｐｌ、Ｐｈｙｓ、Ｌｅｔｔ、５２（１１）、１４
Ｍａｒｃｈ ８８９（１９８８）、（２） Ｈｊｌ
ｏｎｇ ａｎｄ Ｎ、Ｗ、Ｃｈｅｕｎｇ。Appl, Phys, Lett, 52(11), 14
March 889 (1988), (2) Hjl
ong and N, W, Cheung.
Ａｐｐｌ、Ｐｈｙｓ、Ｌｅｔｔ、５２（１２）、２１
Ｍａｒｃｈ １０２１（１９８８）、がある。Appl, Phys, Lett, 52(12), 21
March 1021 (1988).
しかし、この論文のように酸素や炭素を注入してゲッタ
を起こした場合、基板中に注入した原子か残ってしまい
、素子の特性や信頼性を劣化させることがある。However, if gettering is caused by implanting oxygen or carbon as in this paper, the implanted atoms may remain in the substrate, deteriorating the characteristics and reliability of the device.
この点に関し、本実施例によれば上述したように照射粒
子として軽元素を用い、これを基板か、ら放出させるよ
うになっているために、素子の劣化を軽減することがで
きるものである。Regarding this point, according to this embodiment, as described above, light elements are used as irradiation particles and are emitted from the substrate, so that deterioration of the element can be reduced. .
なお、上記したように基板１０１に低ライフタイム層１
０４を形成した後のスイッチング素子の形成プロセスは
第２図に示すようなものとなる。Note that, as described above, the low lifetime layer 1 is provided on the substrate 101.
The process for forming the switching element after forming 04 is as shown in FIG.
この図において、まず、基板１０１上に酸化膜を堆積さ
せ、その上にフォトレジスト塗布によるパターニングを
行ってエツチングすることにより、基板１０１がｎ型で
あるとした場合、Ｐ型層を形成する領域を開孔する。１
０７はその孔である。In this figure, first, an oxide film is deposited on a substrate 101, and then patterned by photoresist coating and etched to form a region where a P-type layer is to be formed, assuming that the substrate 101 is an n-type. Drill a hole. 1
07 is the hole.
そして、例えば硼素を熱拡散させて、Ｐ型層１０５を形
成する。第２図（ａ）は、その直後の状態を示している
。Then, for example, boron is thermally diffused to form a P-type layer 105. FIG. 2(a) shows the state immediately after that.
次に、基板１０１上に真空蒸着によりアルミニウム膜を
成長させ、このアルミニウム膜をフォトレジストにより
写真蝕刻法を使ってパターンを形成しエツチングする。Next, an aluminum film is grown on the substrate 101 by vacuum evaporation, and a pattern is formed on this aluminum film using a photoresist using a photolithography method and then etched.
これにより第２図（ｂ）に示すように上部電極１０８が
形成される。As a result, the upper electrode 108 is formed as shown in FIG. 2(b).
その後、基板１０１の裏面側にアルミニウム膜を上記と
同様に真空蒸着により被着させ、これが下部電極１０９
とされる。Thereafter, an aluminum film is deposited on the back side of the substrate 101 by vacuum evaporation in the same manner as described above, and this coats the lower electrode 109.
It is said that
これにより、第２図（ｃ）に示すような高速スイッチン
グ素子が形成されるものである。As a result, a high-speed switching element as shown in FIG. 2(c) is formed.
以上説明したように本発明によれば、不純物元素を半導
体基板に付着あるいは拡散させておき、軽元素の荷電粒
子を照射して不純物のゲッタ層を形成し、熱処理によっ
て上記不純物元素を集中させることにより低ライフタイ
ム層を形成するようにしたから、荷電粒子の照射エネル
ギの調整により基板中の希望の深さに低ライフタイム層
を形成することができ且つその低ライフタイム層を形成
する不純物の種類を選択することで希望のデイ−プレベ
ルを形成することができるので素子の設計範囲が限定さ
れず、電子・正孔の様々な捕獲準位素子の中に低ライフ
タイム層を局在化させることができ、低オン電圧の高速
スイッチング素子を形成することができる。As explained above, according to the present invention, impurity elements are attached or diffused onto a semiconductor substrate, a getter layer of impurities is formed by irradiating charged particles of a light element, and the impurity elements are concentrated by heat treatment. Since the low lifetime layer is formed by adjusting the irradiation energy of charged particles, the low lifetime layer can be formed at a desired depth in the substrate, and the impurities forming the low lifetime layer can be formed by adjusting the irradiation energy of the charged particles. The desired deep level can be formed by selecting the type, so the design range of the device is not limited, and the low lifetime layer can be localized in the device with various trap levels for electrons and holes. Therefore, a high-speed switching element with a low on-voltage can be formed.
また、荷電粒子として軽元素（例えば、Ｈ，Ｄ等）を利
用しているため、熱処理によってその粒子を容易に基板
中から放出させることができ、照射粒子による素子の劣
化を軽減することができる。Furthermore, since light elements (for example, H, D, etc.) are used as charged particles, the particles can be easily released from the substrate through heat treatment, and the deterioration of the element due to irradiated particles can be reduced. .
第１図は本発明の一実施例に係る低ライフタイム層形成
プロセスを示す工程別断面図、第２図はその低ライフタ
イム層形成後のスイッチング素子形成プロセスを示す工
程別断面図、第３図はＰｔ濃度プロファイルを示す曲線
図、第４図は従来の半導体装置の断面図である。
１０１・・・シリコン基板、１０２・・・ｐｔ膜、１０
３・・・ｐｔ拡散層、１０４・・・低ライフタイム層。
出願人代理人 佐 藤 −雄
為
図
穿、２図
深 さ（Ｐｍ）
第３図FIG. 1 is a cross-sectional view showing a process for forming a low lifetime layer according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a switching element forming process after forming the low lifetime layer, and FIG. The figure is a curve diagram showing a Pt concentration profile, and FIG. 4 is a cross-sectional view of a conventional semiconductor device. 101... Silicon substrate, 102... PT film, 10
3...PT diffusion layer, 104...Low lifetime layer. Applicant's agent Sato - Yutai Zukan, Figure 2 Depth (Pm) Figure 3
Claims (1)
工程と、 前記半導体基板に軽元素の荷電粒子を照射し前記半導体
基板における該荷電粒子の停止領域にゲッタ層を形成し
且つ該半導体基板を熱処理して該ゲッタ層に前記不純物
元素を集中させ低ライフタイム層を形成する工程と、 を含む半導体装置の製造方法。 ２、前記不純物金属元素としてＡｕ、Ｐｔ、Ｃｕ、Ｓ、
Ａｇ、Ｍｎ、Ｆｅ、Ｚｎ、Ｔｉ、Ｉｎ、Ｇａ、Ａｌのう
ち少なくとも一つ使用した請求項１記載の半導体装置の
製造方法。[Claims] 1. A step of attaching or diffusing an impurity element to a semiconductor substrate; irradiating the semiconductor substrate with charged particles of a light element to form a getter layer in a region of the semiconductor substrate where the charged particles stop; A method for manufacturing a semiconductor device, comprising: heat-treating the semiconductor substrate to concentrate the impurity element in the getter layer to form a low lifetime layer. 2. The impurity metal elements include Au, Pt, Cu, S,
2. The method of manufacturing a semiconductor device according to claim 1, wherein at least one of Ag, Mn, Fe, Zn, Ti, In, Ga, and Al is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24644690A JPH04125933A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24644690A JPH04125933A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04125933A true JPH04125933A (en) | 1992-04-27 |
Family
ID=17148570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24644690A Pending JPH04125933A (en) | 1990-09-17 | 1990-09-17 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04125933A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007055352A1 (en) * | 2005-11-14 | 2007-05-18 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method for manufacturing same |
| US7242037B2 (en) | 1998-08-05 | 2007-07-10 | Memc Electronic Materials, Inc. | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices |
| JP2009239269A (en) * | 1998-08-05 | 2009-10-15 | Memc Electron Materials Inc | Non-uniform minority carrier lifetime distribution in high performance silicon power device |
| US7781294B2 (en) | 2006-07-31 | 2010-08-24 | Infineon Technologies Austria Ag | Method for producing an integrated circuit including a semiconductor |
| US9064711B2 (en) | 2011-06-09 | 2015-06-23 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method for fabricating semiconductor device |
| JP2015149346A (en) * | 2014-02-05 | 2015-08-20 | 三菱電機株式会社 | Method of manufacturing semiconductor device, and semiconductor device |
| US9337282B2 (en) | 2012-09-12 | 2016-05-10 | Fuji Electric Co., Ltd. | Semiconductor device with point defect region doped with transition metal |
| CN107112327A (en) * | 2014-10-10 | 2017-08-29 | 高丽大学教产学协力团 | Utilize the manufacture method of the non-volatile holographic storage thin-film device of eutral particle beam generating means |
-
1990
- 1990-09-17 JP JP24644690A patent/JPH04125933A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7242037B2 (en) | 1998-08-05 | 2007-07-10 | Memc Electronic Materials, Inc. | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices |
| JP2009239269A (en) * | 1998-08-05 | 2009-10-15 | Memc Electron Materials Inc | Non-uniform minority carrier lifetime distribution in high performance silicon power device |
| US7618879B2 (en) | 1998-08-05 | 2009-11-17 | Memc Electronics Materials, Inc. | Non-uniform minority carrier lifetime distributions in high performance silicon power devices |
| US7799662B2 (en) | 2005-11-14 | 2010-09-21 | Fuji Electric Systems Co., Ltd. | Power semiconductor device with soft switching characteristic and manufacturing method for same |
| WO2007055352A1 (en) * | 2005-11-14 | 2007-05-18 | Fuji Electric Device Technology Co., Ltd. | Semiconductor device and method for manufacturing same |
| DE102006035630B4 (en) * | 2006-07-31 | 2012-12-06 | Infineon Technologies Austria Ag | Method for producing a semiconductor component |
| US7781294B2 (en) | 2006-07-31 | 2010-08-24 | Infineon Technologies Austria Ag | Method for producing an integrated circuit including a semiconductor |
| US9064711B2 (en) | 2011-06-09 | 2015-06-23 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method for fabricating semiconductor device |
| US9337282B2 (en) | 2012-09-12 | 2016-05-10 | Fuji Electric Co., Ltd. | Semiconductor device with point defect region doped with transition metal |
| US9680034B2 (en) | 2012-09-12 | 2017-06-13 | Fuji Electric Co., Ltd. | Manufacturing method for semiconductor device with point defect region doped with transition metal |
| JP2015149346A (en) * | 2014-02-05 | 2015-08-20 | 三菱電機株式会社 | Method of manufacturing semiconductor device, and semiconductor device |
| CN107112327A (en) * | 2014-10-10 | 2017-08-29 | 高丽大学教产学协力团 | Utilize the manufacture method of the non-volatile holographic storage thin-film device of eutral particle beam generating means |
| CN107112327B (en) * | 2014-10-10 | 2019-03-15 | 高丽大学教产学协力团世宗校区 | Utilize the manufacturing method of the non-volatile holographic storage thin-film device of eutral particle beam generating device |
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