JPH04123668U - Integrated circuit for image display - Google Patents

Abstract

(57) [Summary] [Structure] Includes a counter 17 that counts horizontal synchronization signals for one frame. A frequency conversion circuit 10 that generates first to third reference frequency signals is provided. A detection circuit 16 is provided for detecting which of the first, second, and third reference frequency signals corresponds to the horizontal synchronization signal that the count value of the counter corresponds to. [Effect] It is possible to automatically switch to correspond to standard television video signals, double-speed television video signals, and high-definition television system character display, so the burden on the software of the control microcomputer can be reduced. Further, only one reference signal oscillation circuit is required. moreover,
Fully compatible with high-definition television formats,
The font size does not change.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to an integrated circuit for image display, and in particular to an integrated circuit for displaying multiple types of television images. The present invention relates to an image display integrated circuit having a function of controlling character display.

0002

[Conventional technology]

A conventional image display integrated circuit 2 of this type has an oscillation circuit 15 and an oscillation circuit 15, as shown in FIG. , horizontal size counter 18, horizontal position counter 19, and horizontal address counter 20, a vertical size counter 21, a vertical position counter 22, and a vertical address counter. It was configured to include a counter 23, a control circuit 24, and a display control circuit 25.

0003 This image display integrated circuit 2 includes a control microcomputer 3 and a standard television. Reference signal oscillator 5 for vision video signals and standard for double-speed television video signals It was used in combination with the signal oscillator 6 and the switch circuit 7. Next, the operation will be explained.

0004 Using this image display integrated circuit 2, standard television video signals and double-speed television In order to support the character display of the John video signal, the following steps have been taken.

[0005] First, from microcomputer 3, standard television format and double speed television A method switching command for switching between the two methods is input to the image display integrated circuit 2. here First, select the standard television format. Then, the switch circuit 7 , the reference signal oscillator 5 for standard television video signal is selected, and 15.734K A Hz signal is applied to the oscillation circuit 15 as a reference signal. Frequency of oscillation circuit 15 and the value set by the control signal from the control circuit 24. The counter 18, the horizontal position counter 19, and the horizontal address counter 20 are arranged in the horizontal direction. Decide the display position and character width. Similarly, the control signal from the control circuit 24 Based on the set values, the vertical size counter 21, the vertical position counter 22, and the vertical A dress counter 23 determines the vertical display position and character size. this Based on these data, characters are displayed on the screen via the display control circuit 25.

[0006] Next, a case where the double speed television system is selected will be explained.

[0007] In this case, the switch circuit 7 switches the reference signal for the double-speed television video signal. Oscillator 6 is selected and generates a 31.5KHz signal, twice that of the standard television system. is applied to the oscillation circuit 15 as a reference signal. The frequency of the oscillation circuit 15 and the control circuit horizontal size counter 18 based on the value set by the control signal from path 24; , the horizontal position counter 19 and the horizontal address counter 20 indicate the horizontal display position and and character width. Similarly, the value set by the control signal from the control circuit 24 Based on this, the vertical size counter 21, vertical position counter 22, and vertical address counter The printer 23 determines the vertical display position and character size. At this time, Sara Then, select the divider by 2 that constitutes the vertical address counter 23 and set the vertical position counter. The horizontal synchronizing signal frequency, which is the output of the converter 22, is set to be divided by two. these Based on the data, via the display control circuit 25, the same as in the case of standard television system. The idea was to display letters of the same size on the screen at the positions of the characters.

[0008]

[Problem that the idea aims to solve]

The conventional image display integrated circuits described above are compatible with standard television video signals and double-speed television. In order to support character display of vision video signals, a microcomputer for control is required. System switching for switching between standard television system and double-speed television system in a computer Since this was done using commands, the control microcomputer software The disadvantage was that it placed a heavy burden on A. Also available for standard television format and double speed format. It had the disadvantage of requiring two reference signal oscillation circuits, one for the revision method and one for the revision method. . Furthermore, it is not fully compatible with high-definition television formats, and the font size The drawback was that the sharpness changed.

[0009]

[Means to solve the problem] The image display integrated circuit of the present invention uses a horizontal synchronization signal for one frame of television. a counter that counts The first reference frequency signal with a predetermined frequency is divided and multiplied to generate the second and second reference frequency signals. a frequency conversion circuit that generates a third reference frequency signal; The count value of the counter is the frequency of the first, second and third reference frequency signals. Any of the first, second and third horizontal synchronization signal frequencies of predetermined values corresponding to a detection circuit that detects whether the The output of the detection circuit determines which of the first, second and third reference frequency signals. a first switch circuit for selecting one of the two; a frequency dividing circuit that divides the frequency of the horizontal synchronization signal to generate a frequency-divided synchronization signal; Depending on the output of the detection circuit, either the horizontal synchronization signal or the frequency-divided synchronization signal is detected. and a second switch circuit for selecting one of the two.

0010

【Example】

Next, embodiments of the present invention will be described with reference to the drawings.

[0011] FIG. 1 is a block diagram showing an embodiment of the image display integrated circuit of the present invention.

0012 As shown in FIG. 1, the image display integrated circuit 1 of this embodiment includes a frequency divider 11 and a multiplier. 12, 13 and a switch circuit 14, and an oscillation circuit 15. , the detection circuit 16, the horizontal synchronization counter 17, the horizontal size counter 18, and the water horizontal position counter 19, horizontal address counter 20, and vertical size counter 21 , a vertical position counter 22 , a vertical address counter 23 , a control circuit 24 , The display control circuit 25 is configured to include a display control circuit 25.

[0013] The image display integrated circuit 1 is supplied with a reference signal R1 from an external reference signal oscillator 4. It will be done.

[0014] FIG. 2 is a block diagram showing details of the vertical address counter 23.

[0015] In FIG. 2, the vertical address counter 23 includes a frequency divider 231 with a frequency division ratio of 2 and a detection A switch circuit 232 that selects the input signal and frequency divider 231 based on the output of the circuit 16 and a horizontal synchronization counter 233 that counts the output of the switch circuit 232. It is.

[0016] Next, the operation of this embodiment will be explained.

[0017] When displaying text on a television image, the horizontal width of the text is determined by the horizontal synchronization signal. It is set by the ratio of the signal frequency and the reference frequency. Therefore, the standard circumference as shown in Table 1 A wavenumber source is required.

[0018]

[0019] The frequency of the reference signal R1 input from the external reference signal oscillator 4 is If X corresponds to the revision system, standard television system and double speed television To obtain the respective reference signals R2 and R3 of the John system, a frequency divider 11 and a multiplier are used. A frequency conversion circuit 10 consisting of 12 and 13 is used. Here, the frequency division ratio of the frequency divider 11 is is 214, multiplier 12 should be multiplied by 100, and multiplier 13 should be multiplied by 200. It is set as follows.

[0020] First, a horizontal synchronizing signal H and a vertical synchronizing signal V are respectively input. horizontal synchronization The signal is processed one frame by the horizontal synchronization counter 17 which is reset by the vertical synchronization signal V. horizontal synchronization signals for each frame are counted. The count value of the horizontal synchronization counter 17 is 16, where the high-definition television system, standard television system and the value of the horizontal synchronization signal for double-speed television systems is detected. Ru. For example, in the standard television system, 525 is output as the detected value. Ru. This detected value signal controls the switch circuit 14 of the frequency conversion circuit 10 and outputs the detected value. A reference signal output circuit corresponding to the signal, in this case a multiplier that outputs the reference signal R2 Select 12. Similarly, in the case of double-speed television system, output the reference signal R3. Select the multiplier 13 to be used. Also, if you are using a high-definition television system, the input The selected reference signal R1 is output as is.

[0021] Next, the output of the frequency conversion circuit 10 is input to the oscillation circuit 16. Below mentioned above Characters are displayed on the image by the same operation as described in the conventional example.

[0022] Here, the vertical display position and vertical character size are the number of horizontal scanning lines. That is, it is set by the count value of horizontal synchronization signals per frame. child Therefore, in the case of standard television system, 1R of displayed characters per horizontal scanning line. In contrast to outputting OM addresses, high-definition television format or double-speed television In the case of the revision method, one ROM address of the displayed character is set for two horizontal scanning lines. Output. A selection circuit for this purpose is provided in the vertical address counter 23. They are a frequency divider 231 and a switch circuit 232. In other words, the standard television system In this case, the switch circuit 232 is controlled by the detection value signal of the detection circuit 16 and the input signal is is selected to be input directly to the horizontal synchronization counter 233. Also, high-definition television In the case of a television system or a double-speed television system, the detection value signal of the detection circuit 16 controls the switch circuit 232 and converts the output signal of the frequency divider 231 into a horizontal synchronous counter. 233. As a result, high-definition television formats, standard Both the revision system and the double-speed television system are almost the same. It becomes possible to display characters in the same size at one position.

[0023]

[Effect of the idea]

As explained above, the image display integrated circuit of the present invention has one frame of horizontal synchronization. A counter that counts signals and a frequency converter that generates the first to third reference frequency signals circuit, and the count value of the counter is one of the first, second and third reference frequency signals. and a detection circuit that detects whether the horizontal synchronization signal corresponds to the horizontal synchronization signal. Standard television video signals, double-speed television video signals, and high-definition television video signals It can be automatically switched to correspond to the character display of the control method. This has the effect of reducing the burden on microcomputer software. Another advantage is that only one reference signal oscillation circuit is required. In addition, high-definition television Fully compatible with vision methods, with the effect that the font size does not change have.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an image display integrated circuit of the present invention.

FIG. 2 is a block diagram showing details of the vertical address counter of FIG. 1;

FIG. 3 is a block diagram showing an example of a conventional image display integrated circuit.

[Explanation of symbols]

1,2 Integrated circuit for image display 3 Microcomputer 4-6 Reference signal oscillator 7,14,232 Switch circuit 10 Frequency conversion circuit 11,231 Frequency divider 12,13 Multiplier 15 Oscillation circuit 16 Detection circuit 17,233 Horizontal synchronization counter 18 Horizontal size counter 19 Horizontal position counter 20 Horizontal address counter 21 Vertical size counter 22 Vertical position counter 23 Vertical address counter 24 Control circuit 25 Display control circuit

Claims (1)

[Scope of utility model registration request] Claim 1: A counter that counts horizontal synchronization signals for one frame of television, and a first reference frequency signal having a predetermined frequency that is divided and multiplied to generate second and third reference frequency signals. a frequency converting circuit that performs a frequency conversion circuit, and a count value of the counter is one of the first, second, and third horizontal synchronizing signal frequencies having predetermined values corresponding to the frequencies of the first, second, and third reference frequency signals; a detection circuit for detecting whether the first,
a first switch circuit that selects one of the second and third reference frequency signals; a frequency divider circuit that divides the frequency of the horizontal synchronization signal to generate a frequency-divided synchronization signal; and a second switch circuit for selecting either the horizontal synchronization signal or the frequency-divided synchronization signal.