JPH04122132A - Timer device - Google Patents

Abstract

PURPOSE:To avoid non-execution of interrupt processing when the capacity of a central processing unit of a base station is exceeded and no task is generated or the central processing unit is destroyed till an interrupt reply is returned and a task is executed by giving an interrupt request to the central processing unit of the base station when timeout processing is not terminated within the specified time. CONSTITUTION:Let an initial setting value of a counter circuit 11 be, e.g. 3, then a count is decremented by 1 to be 2 by a initial clock signal CLKa and further decremented by 1 to be 1 by a succeeding clock signal CLKb, and an interrupt request circuit 13 outputs an interrupt request (d). When timeout processing is not terminated within a preset time such as 1sec, an interrupt request (e) is set again by a clock signal CLKc. In this case, when a CPU 21 returns an interrupt acknowledge IACK, since the CPU 21 sets the counter circuit 11 to 0, then the operation is stopped. Thus, even in the case of a deficient capacity of a storage device in a base station equipment or destruction of the central processing unit from the return of the interrupt acknowledge till the execution of a task, interrupt processing is implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer device, and particularly to a timer device used in a radio base station device of a vehicle.

[Conventional technology]

The operation of a conventional timer device will be explained with reference to the drawings.

FIG. 4 is a flowchart showing an example of the operation of a conventional timer device.

In FIG. 4, in the conventional timer device, when the counter value goes from 1 to 0 (step 24), a timeout occurs and an interrupt request is sent out. When an interrupt request is received, an interrupt response is sent back, so when the interrupt response is received, the operation is stopped.

[Problem to be solved by the invention]

In the conventional timer device described above, when receiving an interrupt response from the central processing unit of the base station device, it is assumed that the central processing unit of the base station device always executes the interrupt process. There is a problem in that if the device capacity is insufficient or if the central processing unit breaks down between returning an interrupt response and executing a task, interrupt processing will not be executed.

[Means to solve the problem]

In the timer device of the present invention, a central processing unit in a base station device subtracts a counter value set in a counter circuit by 1 at regular intervals, and when the value reaches a certain preset value, an interrupt request is sent to the central processing unit. In the sending timer device, when the counter value of the counter circuit is 1, the countdown is stopped and an interrupt request is sent to the central processing unit, and when an interrupt response to the interrupt request is received from the central processing unit. Control means for canceling the interrupt request, checking the counter circuit after a preset certain period of time, sending out the interrupt request again if the counter value is 1, and stopping the operation when the counter value becomes O. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an example of application of an embodiment of the present invention;
FIG. 2 is a flowchart showing an example of a control procedure of the control circuit of this embodiment, and FIG. 3 is a time chart showing an example of the operation of this embodiment.

In FIG. 1, this application example includes a base station device 2 and a timer device 1 operated by a tarlock signal CLK from the base station device 2, and the base station device 2 has a memory 22.
The timer device 1 has a central processing unit W (hereinafter referred to as CPU) 21 that processes the entire base station device 1 according to a program stored in the CPU 21. Sends interrupt request signal INT and receives interrupt response IACK from CPU 21
an interrupt request circuit 13 that receives the interrupt request circuit 13; and a control circuit 12 that controls the entire timer device 1 and causes the counter circuit 11 to subtract.
It is composed of:

Next, the operation of this application example will be explained using FIGS. 1, 2, and 3.

When executing a certain task (timeout processing), the CPU 21 of the base station device 2 stores data in the memory 2 corresponding to the task to be executed.
The counter value from 2 is set in the counter circuit 11.

The control circuit 12 reads the counter value of the counter circuit 11 in step 11, and the counter value becomes "0" in step 12.
If the counter value is "0", the process proceeds to step 13, and if the counter value is "l", the process proceeds to step 1.
4, the interrupt request signal INT is sent from the interrupt request circuit 13 to the CPU 21. If the counter value is not I\1, the process proceeds to step 15, where "-1" is subtracted from the counter value. If there is an interrupt response IACK from the CPLI 21 (step 16), the CPU 21 sets the counter value to "0" and stops the operation (step 18). If there is no interrupt response IACK, the CPU 21 waits for a preset period of time. After that (step 17), if the counter value of the counter circuit 11 is "1", the interrupt request signal INT is sent to the CPU 21 again, and the same process is repeated until the counter value of the counter circuit 11 is "1".
When it reaches "O", the operation stops.

For example, as shown in FIG. 3, the initial setting value of the counter circuit 11 is set to 3. The counter value is "-1" and becomes "2" by the first clock signal CLKa. next clock signal C
Further "-1' in LKb.

The counter value becomes "1", and the interrupt request circuit 13 issues an interrupt request d. If the timeout process does not end within a preset time, for example, one second, the tarlock signal CLKc
Then issue the interrupt request e again.

At this time, when the CPU 21 returns an interrupt response IACK, the CPU 21 sets the counter circuit 11 to "0" and the operation is stopped.

〔Effect of the invention〕

As explained above, the present invention stops the countdown when the counter value of the counter circuit is 1, sends an interrupt request to the central processing unit, and interrupts when an interrupt response to the interrupt request is received from the central processing unit. By having a control means that cancels the interrupt request, checks the counter circuit after a preset period of time, and if the counter value is 1, sends the interrupt request again, and stops the operation when the counter value becomes 0. If the timeout processing is not completed within the specified time, an interrupt request will be sent to the base station central processing unit again, so if the base station central processing unit is over capacity and cannot create a task, or the task will be executed after returning an interrupt response. This has the effect of eliminating the possibility of interrupt processing not being executed even if the central processing unit is broken before the processing is completed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of application of an embodiment of the present invention;
FIG. 2 is a flowchart showing an example of the control procedure of the control circuit in this embodiment, FIG. 3 is a time chart showing an example of the operation of this application example, and FIG. 4 is an example of the control procedure of the conventional timer device. FIG. 1... Timer device, 2... Base station device, 11...
- Counter circuit, 12... Control circuit, 13... Interrupt request circuit, 21... Central processing unit (CPtJ), 22
-9. memory.

Claims (1)

[Claims] In the timer device, the central processing unit in the base station device subtracts a counter value set in a counter circuit by 1 at regular time intervals and sends an interrupt request to the central processing unit when the value reaches a preset constant value. When the counter value of the counter circuit is 1, the countdown is stopped and an interrupt request is sent to the central processing unit, and when an interrupt response to the interrupt request is received from the central processing unit, the interrupt request is canceled. , a timer characterized in that it has a control means that checks the counter circuit after a preset certain period of time, sends out an interrupt request again if the counter value is 1, and stops the operation when the counter value reaches 0. Device.