JPH04120609A - Speed controller - Google Patents

Abstract

PURPOSE:To widen the controlling range of a speed controller without adding hardware by performing predictive arithmetic processing and high-band gain characteristic compensation on predicted outputs by means of software operation. CONSTITUTION:This speed controller is provided with a counter 4 which detects the average speed of a rotating body in each measuring section by measuring the period of speed detecting signals corresponding to the speed of the rotating body, reference value generator and subtractor which calculate the error of the average speeds from the output of the counter 4 and reference period data of the rotating body, speed error predicting block 17 which predicts an instantaneous speed error from the average speed error in each measuring section and average speed errors prior to the average speed error in each section, and a motor drive circuit 16 which drives the rotating body based on the output of the block 17. Since the occurrence of a phase lag in a counter section can be eliminated, the controlling range of this speed controller can be widened, with the stability of the controller being maintained at the double of the conventional frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a speed control device that drives a rotating body based on a speed detection value obtained by periodic measurement of a speed detection signal of the rotating body.

2. Description of the Related Art Conventionally, digital speed control devices for rotating bodies have been widely used in magnetic recording and reproducing devices.

FIG. 8 shows a schematic block diagram of a rotational speed control system of a capstan motor in a conventional magnetic recording/reproducing device.

In FIG. 8, a frequency generator 2 attached to the motor 1 outputs a sine wave signal as shown in FIG. 9a. This signal has a period dependent on the rotational speed of the motor 1, and is further amplified and waveform-shaped by the FG signal amplifier 3 to become a square wave signal as shown in FIG. The output of the FG signal amplifier 3 is input to a speed error detector 19, and the period of the input signal is quantized by a counter 4. Subtractor 6
Then, from the quantized count value, the reference value generator 5
The reference cycle data outputted from the subtracter is subtracted, and the speed error is outputted. The detected speed error is subjected to gain compensation in the speed control region by the digital filter 14, and then output to the D/A converter 15, and the output of the D/A converter 15 is supplied to the motor drive circuit 16, which controls the rotation. The speed of the body is controlled.

Problems to be Solved by the Invention By the way, a block diagram including the transfer functions of each part in the above configuration is shown in FIG. 10, and the control limit frequency in the speed control system of the rotating body will be explained based on this.

In Fig. 10, the motor transfer function is torque constant Kt
(g-cm/A) and moment of inertia J (g-cm@
Represented by sec@sec/radL and Laplace operator S. The rotational speed of the motor 1 is determined by a frequency generator 2 (FG in Fig. 10) having two teeth per rotation.
It is abbreviated as. ) is converted into a speed detection signal,
The input/output sampler, counter 4 and moving average element measure the period of the input signal.

Fck the frequency of the reference clock supplied to counter 4.
(Hz), and the sampling period is T (seC),
The transfer function Gc of the counter 4 is expressed by the following formula: % However, the reference value is subtracted from the cycle measurement value of the speed detection signal quantized by the counter 4, and the speed error is calculated. The calculated speed error is input to a digital filter 14 having a transfer function Gf, where gain compensation is performed in the speed control region, and then supplied to a zero-order holder constituted by an input buffer of a D/A converter 15.

The transfer function Gh of the zero-order holder is expressed by the following equation.

The output of the T0-order holder is converted into an analog voltage by a D/A converter 15 having a conversion gain Kx, and its output is supplied to a motor drive circuit 16 having a transfer conductance gm (A/V), and its output is The current controls the speed of the motor.

The conversion gain Kx of the D/A converter 15 is given by the number of converted bits (nl) and the supply voltage Vcc. , the counter part and the holder, and the phase characteristic θC9θh of both at an arbitrary frequency f is (1),
From equation (3), it is expressed as follows, θC=-π・f・T
...(5) θh=-π-f-
T...(6) Now, in order for the control system to operate stably on the -film surface, a phase margin of 40 to 60 degrees is required at the frequency where the open loop gain is OdB, but at that frequency The inertial term in the inertial block shown in FIG. 10 becomes dominant, resulting in a 90 degree phase lag at this frequency. Therefore, the necessary conditions for obtaining a phase margin of 60 degrees at this frequency are expressed by the following equation.

1 θC + θh 1≦−... (7) The control limit frequency Flff at which the motor can be stably controlled is calculated using the following formula using the FG frequency Ffg.As mentioned above, the motor can be stably controlled. The control limit frequency is regulated by the FG frequency.

Therefore, by providing a multiplier circuit before inputting the speed detection signal to the speed error detector and halving the sampling period T, the control limit frequency can be set to one-sixth of the FG frequency.
It is possible to expand to

However, the multiplication method cannot be used unless the time for one cycle of the speed detection signal is at least twice the time required from speed error detection to output to the D/A converter. That is, when the FG frequency is relatively high, the theoretical limit value of the control limit frequency is 1/12 of the FG frequency, as shown by equation (8).

The present invention solves the above-mentioned conventional problems, and aims to provide a speed control device that can stably control speed even when the multiplication method cannot be used.

Means for Solving the Problems To achieve this object, the speed control device of the first invention calculates the average speed of the rotating body in each measurement section by measuring the period of a speed detection signal according to the speed of the rotating body. A speed detection means for detecting, a speed error calculation means for calculating an average speed error from an output of the speed detection means and reference period data of the rotating body, an average speed error for each measurement section, and an average speed error for each measurement section. and a driving means for driving the rotating body based on the output of the predicting means.

Further, in addition to the first invention, the speed control device of a second invention is provided with compensation means for compensating the output of the prediction means, and the drive means drives the rotating body based on the output of the compensation means. It is structured as follows.

Effects The present invention can provide a speed control device with the above-described configuration, which can provide a larger phase margin than the conventional example and can expand the speed control range.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a speed control device in an embodiment of the first invention, and the same reference numerals are used for parts having the same functions as in FIG. 8.

In FIG. 1, the output signal of the FG signal amplifier 3 is supplied to a counter 4 and quantized using a reference clock. The count data of the counter 4 and the reference data of the reference value generator 5 are supplied to a subtracter 6, the reference value data is subtracted from the count data of the counter 4, and the calculation result data is supplied to the first memory 7. .

The first predictor 9 includes a first memory 7 and a second memory 8.
After the data in the first memory 7 is supplied and a predictive calculation is performed, the data in the first memory 7 is supplied to the second memory 8.

The data of the fourth memory 11 and the first memory 7 are supplied to the second predictor 12, and after a prediction operation is performed, the data of the third memory 10 is supplied to the fourth memory 11. Ru.

The third predictor 13 is supplied with the output data of the second predictor 12 and the first predictor 9, and performs a prediction calculation. The prediction calculation result is supplied to the digital filter 14.

The speed error prediction block 17 is composed of the second memory 8 to the third predictor 13, and receives the output signal from the FG signal amplifier 3 as a control signal.

Further, the output signal of the FG signal amplifier 3 is also input to the digital filter 6 as a sampling signal.

Furthermore, the flowchart in FIG. 3 is assumed to be realized by software installed in a microprocessor, and the subtracter 6, calculations in the speed error prediction block 17, and digital filter 14 in FIG. It can be easily implemented using an arithmetic logic unit (ALU).

The operation of the speed control device configured as described above will be explained based on FIGS. 1 to 4.

FIG. 4 shows the relationship between the FG multiplication signal and the speed error C of the motor 1, and shows a state where the rotational speed of the motor 1 is becoming slower.

First, when the leading edge of FIG. 4 arrives, the contents of the first memory 7 are transferred to the second memory 8, and the contents of the third memory 10 are transferred to the fourth memory 11. That is, the second memory 8 and the fourth memory 11 always store the previous data input to the first memory 7 and third memory 10. This is in preparation for the prediction operations of the first predictor 9 and the second predictor 12.

Next, in the first predictor 9, the contents of the second memory 8 are subtracted from the data three times the contents of the first memory 7, and then divided by two. This calculation result is stored in the third memory 1
Stored at 0. In the second predictor 12, the contents of the fourth memory 11 are subtracted from twice the data of the first memory 7.

Finally, in the third predictor 13, a weighted average value of the output data of the second predictor 12 and the output data of the first predictor 9 is calculated and output.

The above series of processing will be explained based on FIG. 4.

It is assumed that at time t7, the leading edge shown in FIG. 4 has arrived and the processing of the speed detector I9 has been completed. At this point, the first memory 7 stores speed error data that depends on the average speed of the motor 1 in the section from time t5 to time t7. Similarly, the second memory 8 stores speed error data that depends on the average speed of the motor 1 in the section from time t3 to time t5. Here, if we assume that the instantaneous speed between two pulses of the speed detection signal of the motor 1 from time t3 can be approximated by a straight line, then the content stored in the first memory 7 is from time tI11, that is, from time t5 to represents the instantaneous velocity error e2 at the midpoint of time t7, and the contents of the second memory 8 are at time t4. In other words, it represents the instantaneous speed error e at the midpoint of time T, 3''''j'-.

Therefore, the predicted instantaneous speed error value RO at time tl is expressed by the following equation.

That is, the first predictor 8 outputs the instantaneous speed error predicted value Re expressed by equation (9). By the way, the instantaneous speed error predicted value R at time t5 is stored in the fourth memory 11.
4 is stored.

The second predictor 12 outputs an instantaneous speed error predicted value R2 expressed by the above equation from the instantaneous speed error predicted value RIN at time ts and the instantaneous speed error e2 at time t6.

R2= 82+ (e2-R+)
−・(x O) In other words, according to equation (9), the previous time (
The instantaneous speed error predicted value R1 calculated at time ts is reflected in the current calculation.

The third predictor 13 weights and averages the instantaneous speed error predicted values R11 and R2 calculated as described above, and outputs the final instantaneous speed error predicted value R.

From the above, if the transfer function Prl of the first predictor 9 is expressed using the Z operator, similarly, the transfer function Pr2 of the second predictor 12 is 4-32
−1+Z−2 Pr2= (12) Therefore, the transfer function Pr3 of the third predictor is (Prl+Pr2) Pr3=.

In other words, by performing the process shown in equation (13),
The processing of the speed error prediction block 17 in FIG. 1 can be performed. Accordingly, the velocity error prediction block 17 of FIG. 1 is simplified and illustrated in FIG.

A flowchart for realizing the processing shown in the block diagram of FIG. 2 is shown in FIG. 3, and the processing will be explained.

Here, the count value used is the output of counter 4 in FIG. 1, the reference value is the output of reference value generator 5 in FIG. 4
It corresponds to

In addition, in order to simplify the calculation, equation (13) is transformed into (
14) It shall be realized in the form of Eq.

First, in the processing branch 30, it is determined whether the leading edge of the output signal of the FG signal amplifier 3 shown in FIG. 1 has arrived. If it has arrived at this time, the reference value is subtracted from the count value in processing block 31,
The subtraction result is transferred to memory 1. If it arrives and there is no 5, the process ends. In processing block 32, memory 1
The contents of the memory 2 are subtracted from the subtraction result 1, which is transferred to the memory 4, and then 2. In the processing block 33, data three times the contents of the memory 1 is transferred to the register.

In this process, by transferring the contents of memory 1 to the register and adding the contents of memory J to the register twice, data three times the contents of memory 1 is transferred to the register without using a multiplication instruction. 1. In processing block 34, the contents of memory 3 are added to the value of l/jister and transferred to l/jister again.

In processing block 35, the value of the register is shifted to the right twice and transferred to the register again. In processing block 36, the contents of memory 4 are added to the value in the register, and the result is stored in the register again.

The processing block 37 outputs the value of the register, that is, the predicted instantaneous velocity error value R, to the digital filter 14 of FIG.

The processing blower 38 transfers the contents of memory 2 to memory 3 and the contents of memory 1 to memo U2 in preparation for the next calculation.

Note that in the series of arithmetic operations, the processing is performed by addition, subtraction, and shift operations without using multiplication instructions, so the processing time is very short, and there are almost no dead time elements.

The process of the speed error prediction block 17 in FIG. 1 can be executed by the above series of simple arithmetic operations.

FIG. 11 shows a conventional counter 4+holder and a speed error prediction pro 1. This is the result of simulating the phase characteristics of the 17+ holder, and the sampling period T is 1 ms. Here, the amount of phase delay in the first invention is one half of that in the conventional example.

Therefore, according to this embodiment, by executing the prediction calculation shown in equation (14) by software calculation, it is possible to theoretically make the phase delay amount of the filter counter part zero, as shown in equation (5). can.

The phase characteristic in the first invention is expressed by the following equation.

θC=O...(5) Therefore, from equations (5), (8), and (7), the control limit frequency F11 at which the motor can be stably controlled is the FG frequency F.
It is expressed by the following equation using fg.

Therefore, it is theoretically possible to extend the control limit frequency at which the motor can be stably controlled to one-sixth of the FG frequency without using the multiplication method.

FIG. 5 shows a block diagram of a speed control system according to an embodiment of the second invention, and the same reference numerals are used for parts having the same functions as those in FIG. 1, and the explanation thereof will be omitted.

In FIG. 5, a third predictor 1 is stored in a third memory 0.
3 output data is input. 2nd pre-cho 1 19
The output data of the taa memory 11 and the f (whistle 1 memory 7) are supplied to the memory 11, and after a predictive calculation is performed, the output data of the third memory 10 is input to the fourth memory 11.

The output data of the third predictor 13 is supplied to a third memory 10 and a compensator 18. The output of the compensator 18 is input to the digital filter 14.

Note that the speed error prediction block 17 is stored in the second memory 8 to the third memory.
FG signal amplifier 3
The output signal from is input as a control signal.

Further, the output signal of the FG signal amplifier 3 is also input to the digital filter 14 and the compensator 18 as a sampling signal.

Furthermore, the flowchart in FIG. 7 is assumed to be realized by software installed in a microprocessor, and the calculations in the subtracter 6, speed error prediction block 17, compensator 18, and digital filter 14 in FIG. , the arithmetic and logic unit (AL) of the microprocessor
U) by Yong, Huge! 7. The operation of the speed control device configured as described above will be explained based on the block diagram shown in FIG. 5 and the time chart shown in FIG. 4.

FIG. 4 is an output signal waveform diagram of the FG signal amplifier 3 of FIG. 5. First, when the leading edge of FIG. 4 arrives, the contents of the first memory 7 are transferred to the second memory 8, and the contents of the third memory 10 are transferred to the fourth memory 11. That is, the second memory 8. Fourth memory 11
The previous data input to the first memory 7 and the third memory 10 is always stored. This is in preparation for the prediction operations of the first predictor 9 and the second predictor 12.

Next, in the first predictor 9, the contents of the second memory 8 are subtracted from the data three times the contents of the first memory 7, and then divided by two. This calculation result is sent to the third predictor 1
3 is input. In the second predictor 12, the contents of the fourth memory 11, that is, the previous data input to the third memo IJ 10, are subtracted from twice the data of the first memory 7.

Finally, in the third predictor 13, a weighted average value of the output data of the second predictor 12 and the output data of the first predictor 9 is calculated and output.

The meaning of the above series of processing will be explained based on FIG. 4. It is assumed that at time t7, the leading edge shown in FIG. 4 has arrived and the processing in the speed detector 19 has ended. At this point, the first memory 7 stores speed error data that depends on the average speed of the motor 1 in the section from time t5 to time t7. Similarly, the second memory 8 stores speed error data that depends on the average speed of the motor 1 in the section from time t3 to time t.

Here, assuming that the instantaneous speed error between two cycles of the speed detection signal of the motor 1 from time t3 to t7 can be linearly approximated, the contents stored in the first memory 7 are
v In other words, it represents the instantaneous speed error e2 at the midpoint between times t5 and t7, and the contents of the second memory 8 represent the instantaneous speed error e at the time t4, that is, the midpoint between times t3 and t6. . Therefore, the predicted instantaneous speed error value R9 at time t7 is expressed by equation (9). That is, the first predictor 9 outputs the instantaneous speed error predicted value RII expressed by equation (9), as in the first embodiment.

By the way, the instantaneous speed error predicted value R1 output from the third predictor 13 is stored in the fourth memory 11 at time t6.
is stored. The second predictor 12 calculates the instantaneous speed error predicted value R+ at time t6, that is, the fourth memory 1
1 and the instantaneous speed error e2 at time t6, (10
) outputs an instantaneous speed error predicted value R2 expressed by the equation. That is, according to equation (10), the instantaneous speed error predicted value R actually output from the third predictor 13 last time (time ts)
+ will be reflected in this calculation. The third predictor 13 uses the instantaneous speed error predicted value R calculated as described above.
2 and R2 to output a final instantaneous speed error predicted value R. From the above, the transfer function Pr3 of the third predictor 13 is expressed using the Z operator.

In other words, by performing processing to realize equation (15),
The velocity error prediction block of FIG. 5 is simplified and illustrated in FIG. Note that FIG. 6 also shows filtering processing in the compensator 18.

A flowchart for realizing the processing shown in the block diagram of FIG. 6 is shown in FIG. 7, and the processing will be explained.

The count value used here is counter 4 in Figure 5.
The outputs and reference values are the outputs of the reference value generator 5 in FIG. 5, and memories 1 to 4 correspond to memories 1 to 4 in FIG. 6.

The processing of the processing branches 70 to 77 results in the fifth
The processing of the speed error prediction block 17 shown in the figure is executed.

First, in the processing branch 70, it is determined whether the leading edge of the output signal of the FG signal amplifier 3 shown in FIG. 5 has arrived. If it has arrived at this time, the reference value is subtracted from the count value in processing block 71, and the subtraction result is MeU++W*=Sumitsubo 1 Piece 1±1
(p) - φ ship - Douami IJ' finishing. In processing block 72, the contents of memory 2 are transferred to memory 3. In processing block 73, the value of one half of the contents of memory 2 is transferred to a register. Furthermore, processing block 74 subtracts the value of the register from the contents of memory 1 and transfers the result to memory 2. In processing block 75, a value seven times the contents of memory 2 is transferred to a register.

Processing block 76 subtracts the contents of memory 3 from the value in the register and transfers the result to the register. In processing block 77, one quarter of the value of the register is transferred to the register.

The value in the register at this point represents the predicted instantaneous speed error value R.

The processing in the velocity error prediction block 17 is executed through the processing branches 70 to 77 described above.

Next, processing blocks 78 to 80 implement the processing of the compensator 18 in FIG.

This compensator 18 is constituted by the simplest first-order low-pass filter, and its transfer function Hp is expressed by the following equation.

Hp”...(16
)-aZ In processing block 78, the contents of memory 4 are added to the value in the register, and the result is transferred to the register. Processing block 79 sets the value of the register to a pre-calculated constant a.
After multiplying by , the result is transferred to memory 4. In the processing block 80, a pre-calculated constant (b/a) is stored in the memory 4.
After multiplying by , the value is transferred to a register.

Here, it is assumed that the constant al (b/a) is selected to have an arbitrary value so that the processing in processing blocks 79 to 80 can be executed by a shift operation.

In processing block 81, the value of the register is output to digital filter 4 in FIG.

Note that in the series of arithmetic operations, the processing is performed by addition, subtraction, and shift operations without using multiplication instructions, so the processing time is very short, and there are almost no dead time elements.

The processing of the velocity error prediction block 17 and the compensator 18 shown in FIG. 5 can be realized by the above series of simple arithmetic operations.

FIG. 12 shows the results of simulating the phase characteristics of the conventional counter + holder and the speed error prediction block 17 + holder of the second invention, and the sampling period is 1 ms.
It is said that Here, the phase delay amount of the second invention is one half of that of the conventional example.

Therefore, according to this embodiment, assuming that the amount of phase delay of the compensator 18 is negligible, by executing the prediction calculation shown by equation (14) by software calculation,
Theoretically, the phase delay amount of the counter section expressed by equation (5) can be made zero.

The phase characteristic in the present invention is expressed by the following equation.

θc=0...(5)
``Therefore, from equations (5)'', (8), and (7), the control limit frequency F11. that allows stable control of the motor is determined. is expressed by the following equation using the frequency Ffg of FG.

fg F day, = ... (8)"
Therefore, it is theoretically possible to extend the control limit frequency at which the motor can be stably controlled to one-sixth of the FG frequency without using the multiplication method.

As described above, according to this embodiment, by executing the prediction calculation and compensation calculation shown by equations (15) and (16) by software, the amount of phase delay of the conventional counter section shown by equation (7) can be zeroed out. It can be done.

Therefore, it is theoretically possible to extend the control limit frequency at which the motor can be stably controlled to one-sixth of the FG frequency without using the multiplication method.

Effects of the Invention As described above, the first invention includes a speed detection means (counter 4) that detects the average speed of the rotating body in each measurement section by periodic measurement of a speed detection signal corresponding to the speed of the rotating body; A speed error calculation means (a reference value generator 5 and a subtractor 6) that calculates an average speed error from the output of the speed detection means and reference period data of the rotating body, and calculates the average speed error for each measurement section and the previous one. It is equipped with a prediction means (speed error prediction block 17) that predicts an instantaneous speed error from an average speed error, and a drive means (motor drive circuit 16) that drives the rotating body based on the output of the prediction means, and a counter. Since it is possible to remove the phase delay caused by parts, it is possible to expand the control band while maintaining stability up to twice the frequency of the conventional one.

Furthermore, since the predictive calculation process is performed by software calculation, no additional hardware is required, and its practical effects are extremely large.

Further, a second invention includes a speed detection means (counter 4) for detecting the average speed of the rotary body in each measurement section by periodic measurement of a speed detection signal corresponding to the speed of the rotary body, and an output of the speed detection means. and a speed error calculation means (reference value generator 5 and subtractor 6) that calculates an average speed error from the reference period data of the rotating body, and an instantaneous speed from the average speed error for each measurement section and the previous average speed error. A prediction means (speed error prediction block 17) for predicting an error, a compensation means (compensator 18) for compensating the output of the prediction means, and a drive means (motor) for driving the rotating body based on the output of the compensation means. Since the drive circuit 16) can eliminate the phase delay caused by the counter section, it is possible to expand the control band while maintaining stability up to twice the frequency of the conventional one.

Furthermore, since the prediction calculation process and the compensation of the high-frequency gain characteristics of the prediction output are performed by software calculation, no additional hardware is required, and its practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a speed control device according to an embodiment of the first invention, FIG. 2 is a block diagram of a speed error prediction block 17 of the embodiment, FIG. 3 is a flowchart of the embodiment, and FIG. is a time chart for explaining the operation of the same embodiment and an embodiment of the second invention, FIG. S is a block diagram of the speed control device in an embodiment of the second invention, and FIG. 6 is the same embodiment. 7 is a flowchart of the same embodiment, FIG. 8 is a block diagram of the speed control device in the conventional example, FIG. 9 is a time chart of the conventional example, and FIG. 10 is the same. A block diagram showing the transfer function of each part of the speed control system of the conventional example, Fig. 11 is a characteristic diagram showing a comparison of phase characteristics between the first invention and the conventional example, and Fig. 12 shows the comparison between the second invention and the conventional example. FIG. 2 is a characteristic diagram showing a comparison of phase characteristics of 1... Motor, 2... Frequency generator, 14
River digital filter, 15...D/A converter,
16... Motor drive circuit, 17... Speed error prediction block, 18... Compensator, 19... Speed error detector. Name of agent: Patent attorney Akira Okaji Haga 2 people, Ami Ward, Daizu Ward

Claims (5)

[Claims] (1) Speed detection means for detecting the average speed of the rotating body in each measurement section by periodic measurement of a speed detection signal corresponding to the speed of the rotating body; and the output of the speed detecting means and reference period data of the rotating body. a speed error calculation means for calculating an average speed error from the above; a prediction means for predicting an instantaneous speed error from the average speed error for a specific measurement section and the previous average speed error; and a prediction means for predicting an instantaneous speed error based on the output of the prediction means. A speed control device comprising a drive means for driving the rotating body. (2) The speed control device according to claim 1, wherein the prediction means predicts the instantaneous speed error from the average speed error of each of three consecutive measurement sections. (3) A speed control device according to claim 1, further comprising compensation means for compensating the output of the prediction means, and wherein the drive means drives the rotating body based on the output of the compensation means. (4) The speed control device according to claim 3, wherein the prediction means predicts the instantaneous speed error from the average speed error of each of two consecutive measurement sections. (5) The speed control device according to claim 3, wherein the compensation means is constituted by a low-pass filter.