JPH0412004U

JPH0412004U -

Info

Publication number: JPH0412004U
Application number: JP5297090U
Authority: JP
Priority date: 1990-05-23
Filing date: 1990-05-23
Publication date: 1992-01-31
Anticipated expiration: 2005-05-23
Also published as: JP2513220Y2

Description

[Brief explanation of drawings]

第１図は、本考案の一実施例のブロツク図であ
る。３……「自動」スイツチ、４……「手動」スイ
ツチ、５……「切」スイツチ、６……「入」スイ
ツチ、７……「バイパス」スイツチ、８……第１
のＦＦ、９……第２のＦＦ、１０−１，１０−２
，１０−３……ＡＮＤ回路、１１……ＯＲ回路、
１２……ワンシヨツトタイマ、１３……ＡＮＤ回
路、１４−１，１４−２，１４−３……ＳＳＭ用
ＯＲ回路、１５−１，１５−２，１５−３……Ｓ
ＳＭ用ＦＦ、１６−１，１６−２，１６３……Ｐ
ＣＭ用ＡＮＤ回路、１８−１，１８−２……ＰＣ
Ｍ用ＦＦ、２２−１，２２−２……シーケンス制
御機器（ドライブ類）。 FIG. 1 is a block diagram of one embodiment of the present invention. 3... "Auto" switch, 4... "Manual" switch, 5... "Off" switch, 6... "On" switch, 7... "Bypass" switch, 8... First
FF, 9...Second FF, 10-1, 10-2
, 10-3...AND circuit, 11...OR circuit,
12...One shot timer, 13...AND circuit, 14-1, 14-2, 14-3...OR circuit for SSM, 15-1, 15-2, 15-3...S
FF for SM, 16-1, 16-2, 163...P
CM AND circuit, 18-1, 18-2...PC
M FF, 22-1, 22-2...Sequence control equipment (drives).

Claims

[Scope of utility model registration request]

The "Auto" switch for the group level operation switch and the "Auto" switch for the simulation test switch.
OFF, ON, and BYPASS switches;
A flip-flop receives signals from the ``off'' and ``on'' switches and outputs a set output and a reset output, respectively; a one-shot timer receives signals from the ``bypass'' switch and outputs an output for a predetermined time; and an output from the ``auto'' switch. a plurality of group-level AND circuits into which a plurality of automatic drive operating conditions are input, an AND circuit into which the reset output of the flip-flop and the output of the one-shot timer are input, and an output of the AND circuit. a plurality of OR circuits for group-level SSM, into which the outputs of the plurality of AND circuits are respectively input;
A plurality of group-level SSM flip-flops that receive outputs from a plurality of OR circuits for M and sequentially output set outputs are input, and set outputs of the plurality of flip-flops for the same SSM are respectively inputted, and set outputs of the above-mentioned flip-flops are inputted. Multiple AND circuits for PCM and multiple AN
A group level online simulation device comprising a plurality of PCM flip-flops each receiving the output of a D circuit and sending a set output to a predetermined sequence control device.