JPH04119046A - Data transmission control method - Google Patents

Abstract

PURPOSE:To attain high speed transfer by stopping the input of a transmission data from a line control section to an FIFO buffer and restarting the input of the transmission data to the FIFO buffer 15 when a common control section publicates a command with respect to a request. CONSTITUTION:An FIFO control section 17 sets an FIFO input control signal 22 to '1'. As a result, a clock higher than a Line speed is fed to a line control section 11 and a buffer 15 via an FIFO input control AND gate 19. The input to the buffer 15 is started by using the signal as a shift-out clock at the control section 11 and using the signal as a shift-in clock at the buffer 15. The control section 11 recognizes the transmission of a transmission control character SOH, and publicates a 'command requests' to a control section 14 via a control bus 20. An FIFO control section 17 monitors the bus 20 to recognize the publication of the command. The control section 17 sets an FIFO input control signal and an FIFO output control signal to '0'. As a result, the input to the buffer 15 and the output from the buffer 15 are stopped.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is located between a higher-level processing device and a line termination device, drives the line termination device according to instructions from the higher-level processing device, and transmits data via a communication line. The present invention relates to a data transmission control method for a device that realizes data transfer between a plurality of terminal devices, etc. connected to an upper-level processing device, and is particularly suitable for reducing the probability of underrun occurrence at the peak of the required processing amount of the common control section. The present invention relates to a data transmission control method.

[Conventional technology]

Data transmission control refers to messages that are requested to be transferred from a higher-level processing device to a terminal device, etc., using specific characters such as various transmission control characters stipulated in the transmission control procedure agreed upon with the other device in advance. According to the meaning of the character group,
This is control for disassembling transmission blocks, adding information for error detection, etc. 5YN (independent) If the control is delayed and an underrun occurs on a line using the synchronous basic transmission control procedure, a time fill (SYN or DLE-3YN) is usually inserted on the transmitting side, and a time fill is inserted on the receiving side. By removing , it is possible to transfer data without retransmitting the block, but time fill insertion between the last character of the block and BC3, and between DLE and the next character in a transparent block is An error occurs on the side, and the block needs to be retransmitted, resulting in a decrease in data transfer efficiency.

Conventionally, SYN synchronization basic data transmission control has been performed using the following method (a) or (b).

(b) A method in which a common control unit possessed by a communication control device or a terminal device intervenes every time one character is transmitted, and instructs transmission block disassembly and transmission control and creation of additional information for error detection.

(b) If the bit pattern comparison section in the line control section of the communication control device or terminal device
The bit patterns of the transmitted and received characters are always compared with the transmission control characters specified in accordance with the character type (characters specified in 201) and the transmission control procedure type, and the above is performed only when it is necessary to change the processing content according to the transmission control procedure specification. A method that performs transmission block disassembly and transmission control, addition of error detection information, etc. by activating the common control unit.

Note that the main cause of underrun occurring in the communication control device is a processing delay in the common control unit.

Related methods of this type include, for example, the patent application
There are No. 2-102023 and Japanese Patent Application No. 62-228545.

[Problems to be Solved by the Invention] The above-mentioned conventional technology has the following problems from the viewpoint of the load on the common control section.

That is, in method (a), since the transmission process is performed one character at a time for all characters, there is a problem that the load on the common control section is always heavy. In addition, (b) is an improved method of (b), and the load on the common control unit during normal times is small compared to this, but the load at specific occasions such as when transmitting transmission control characters is reduced by method (I). ), and the good luck remains that the probability of underrun occurring at its peak is high.

Therefore, both methods have problems when accommodating high-speed lines using the SYN synchronization basic procedure.

The purpose of the present invention is to improve such problems, suppress the occurrence of underruns, increase the accommodable line speed regarding the SYN synchronous transmission control procedure, and increase the number of high-speed lines that can be accommodated. The object of the present invention is to provide a data transmission control method.

[Means for Solving the Problems] In order to achieve the above object, the data transmission control method of the present invention uses a communication control device that realizes data transmission based on a SYN synchronization basic transmission control procedure in accordance with the type of transmission control procedure. a common control unit that performs message assembly/disassembly processing and instructions for creating/inspecting additional information for error detection;
A line control unit that performs assembly and disassembly processing of characters according to the line type, detection of transmission control characters, and creation and inspection of additional information for error detection, a FIFO buffer, and the FIFO
Controls the buffer and sends data from the line controller to F
It consists of a circuit (FIFO control unit) that inputs data into the IFO buffer and outputs the transmitted data to the line termination device, and the line control unit transmits data to the FIFO buffer, such as transmission control characters, that are meaningful in terms of transmission control procedure regulations. When you send a character,
Triggered by an instruction request issued to the common control unit, input of transmission data from the line control unit to the FIFO buffer is stopped, and when the common control unit issues an instruction corresponding to the request, transmission data to the FIFO buffer is stopped. It is characterized by restarting input.

[Effect]

In the present invention, the FIFO control section is configured such that the line control section
When sending transmission control characters etc. to the IFO buffer,
In response to an instruction request issued to the common control unit, input of transmission data from the line control unit to the FIFO buffer is stopped, and when the common control unit issues an instruction corresponding to the request, transmission data to the FIFO buffer is stopped. Resume input.

In addition, the high-speed clock generator is
By generating a lock faster than the transmission element timing to the IFO buffer, it is possible to transfer data from the line control unit faster than transfer from the FIFO buffer to the line termination device.

This absorbs temporal fluctuations in the required processing amount of the common control unit and suppresses the occurrence of underrun.

[Example 1 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a configuration diagram of a communication control device in an embodiment of the present invention.

In FIG. 2, 1 is a communication control device, 2 is a line terminating device (DCE), and 3 is a higher-level processing device.
is connected to the line termination device 2 and the upper processing device 3.

The communication control device 1 also includes a line control unit 11, a buffer memory 1lFjl12 that stores transmitted and received data, a higher-level processing unit communication processing unit 13 that controls the interface with the higher-level processing unit, a common control unit 14, a FIFO buffer 15, and a line control unit. 11 to the FIFO buffer 15 is transferred from the FIFO buffer 15 to the line termination device 2. , l In order to achieve high speed, a high-speed glock generator 16 that generates a glock faster than the transmission element timing from the DCE 2, a FIFO control unit that controls the stop and restart of input/output of the FIFO buffer 15] 7. DC
By ANDing the transmission element timing signal from E2 and the FIFO output control signal 26 of the FIFO control unit 17,
The shift ink of the FIFO buffer 15 is generated by the AND gate 18 for FIFO output control that creates a shift out clock for the FIFO buffer 15, the high speed clock from the high speed clock generator 16, and the FIFO input control signal 22 of the FIFO controller 17. A AND gate 19 for FIFO input control that creates a lock, a control bus 20 that transmits commands and startup requests between various parts, and a high-speed clock transfer line 2
1. FIFO input control signal transfer line 22, FIFO input control transmission element timing signal line 23, transmission data signal line 25, FIFO output control signal transfer line 26, transmission element timing signal line 27. F”rFO output control transmission element timing signal line 28, FTF○ status information transfer line 29 for transferring the state of the FrF○ buffer 15,
and a transmission/reception information transfer line 30 for transferring transmission/reception data.

FIG. 1 is an explanatory diagram showing an overview of the operation of a data transmission control method in an embodiment of the present invention, and FIG.
FIG. 4 is an explanatory diagram showing an overview of the operational logic of the O control section 17, and FIG. 4 is an explanatory diagram showing the required processing amount of the common control section in one embodiment of the present invention.

In FIG. 3, OUT is the FIFO output control signal 26
0UT=O indicates the stop of transmission from the FIFO buffer 15 to the line (the line is marked), and 0UT=1 indicates the start of transmission (resume). Further, IN indicates the state of the FIFO input control signal 22, IN=O indicates the stop of input from the line control unit 11 to the FIFO buffer 15, and IN=1 indicates the start (resumption) of input. Furthermore, FIFO empty is F
When the IFO buffer 15 becomes completely empty, the FIFO
This is when an underrun occurs that cannot be avoided even if you use .

Further, in FIG. 1, (1) to (10) indicate each step 1 to 10 of the data transmission control method of this embodiment.

Next, according to FIGS. 1 and 3, the FIFO buffer 1
5 has a capacity of 4 bytes, SOH, A, BC, D, STX
, . . , will be described below.

(1) Step 1 This step 1 is performed in the following processing steps 101 to 103.

101: The common control unit 14 instructs the line control unit 11 to “start transmission” via the control bus 20.

102: The FIFO IJ# unit 17 constantly monitors the control bus 20 and recognizes that the instruction has been issued.

103: The FIFO control unit 17 controls the FIFO control unit 17 based on the operation logic (transition from “initial state” to “start time”) shown in FIG.
Set the IFO input control signal 22 to '1'. As a result, F
If the speed is higher than the line speed via the AND gate 19 for IFO input control, the line control i11'1 is transferred via the transmission element timing signal line 23 for FIFO input control.
1111 and FIFO buffer 15. The line control unit 11 uses the signal as a shift-out clock, and the FIFO buffer 15 uses the signal as a shift-in clock, and input to the FIFO buffer 15 is started. Similarly, the FIFO output control signal is set to “O” and the FIFO
Output from buffer 15 is stopped.

(2) Step 2 This step 2 is performed by the following processing procedures 201 to 203.

201 - The line control unit 11 recognizes that the transmission control character SOH has been transmitted, and in order to receive an instruction regarding the creation of additional information for error detection from the common control unit 14, the line control unit 11 transmits the transmission control character SOH to the common control unit via the control bus 20. 14, an "instruction request" is issued.

20:2: The FIFO control unit 17 recognizes that the instruction has been issued by monitoring the control bus 20.

203: The FIFO control unit 17 sets both the FIFO input control signal and the FIFO output control signal to '○' based on the operation logic (instruction: 1) shown in FIG. As a result, the input to and pressure from the FIFO buffer 15 is stopped.

(3) Step 3 This step 3 is performed by the following processing procedures 301 to 303.

301: The common control unit 14 issues an instruction corresponding to step 2 to the line control unit 11 via the control bus 20.

302: The FIFO control unit 17 recognizes that the instruction has been issued by monitoring the control bus 20.

303: The FIFO control unit I7 sets the FIFO input control signal to "1" and the FIFO output control signal to "o" based on the operation logic (instruction time 2) shown in FIG. 3. As a result, the FIFO buffer Input to 15 is resumed.

(4) Step 4 This step 4 is performed by the following processing procedures 401 and 402.

401: The FIFO buffer 15 notifies that the FIFO is full via the FIFO status information transfer line 29.
The FIFO control unit 17 is notified.

The 401 FIFO control unit 17 sets the FIFO input control signal to °'O' and the FIFO output control signal to '1' based on the operation logic (FIFO full) shown in FIG.

As a result, input to the FIFO buffer 15 is stopped,
Output is started and the first character is sent to the line termination device 2.

(5) Step 5 This step 5 is performed by the following processing procedures 501 and 502.

501: The FIFO buffer 15 notifies the FIFO control unit 17 via the FIFO status information transfer line 29 that a free space has been created in the FIFO and input is now possible.

502: The FIFO control unit 17 sets both the FIFO input control signal and the FIFO output control signal to "l" based on the operation logic (input allowed) shown in FIG. As a result, input to the FIFO buffer 15 is restarted.

(6) Step 6 is performed by the following processing procedures 601 and 602.

6o1: The FUFO buffer 15 notifies the FUFO that the FIFO is full via the FIFO status information transfer line 29.
The IFO control unit 17 is notified.

602: The FIFO control unit 17 sets the FIFO input control signal to "0" and the FIFO output control signal to "II II II" based on the operation logic (FIFO full) shown in FIG.
shall be. As a result, input to the FIFO buffer 15 is stopped.

(7) Step 7 This step 7 is performed by the following processing procedures 701 and 702.

701: The FIFO buffer 15 notifies the FIFO control unit 17 via the FIFO status information transfer line 29 that a free space has been created in the FIFO.

702. The FIFO control unit 17 sets both the FIFO input control signal and the FIFO output control signal to 1''' based on the operation logic (input allowed) shown in FIG. Input resumes.

(8) Step 8 This step 8 is performed by the following processing steps 801 to 805.

801: The line control unit 11 recognizes that the transmission control character STX has been transmitted, and in order to receive an instruction regarding the creation of additional information for error detection from the common control unit 14, the line control unit 11 transmits the transmission control character STX to the common control unit via the control bus 20. 14, an "instruction request" is issued.

The 802-FIFO control unit 17 recognizes that the instruction has been issued by monitoring the control bus 2o.

803. The FIFO control unit 17 inputs the FIFO input control signal based on the operation logic (instruction time 3) shown in FIG.
0'', the FIFO output control signal is set to II II II. As a result, input to the FIFO buffer 15 is stopped.

The 801 FIFO buffer 15 notifies the FIFO that the FIFO is full via the FIFO status information transfer line 29.
The FO control unit 17 is notified.

805: The FIFO control unit 17 maintains the states of the FIFO input control signal and the FIFO output control signal based on the operation logic (instruction time 2) shown in FIG.

(9) Step 9 This step 9 is performed by the following processing procedures 901 and 902.

901: The FIFO buffer 15 notifies the FIFO control unit 17 via the FIFO status information transfer line 29 that a free area has been created in the FIFO and input is now possible.

902: The FIFO control unit 17 maintains the states of the F input control signal and the FIFO output control signal based on the operation logic (instruction time 3) shown in FIG. During this time,
Since the data stored in the FIFO buffer 15 is sent to the line termination device 2, no underrun occurs.

(10) Step 10 This step 10 is performed according to the following processing steps l○01 to 1.003.

1001: The common control unit 14 issues an instruction corresponding to step 8 to the line control unit 11 via the control bus 20.

1002: The FIFO control unit 17 recognizes that the instruction has been issued by monitoring the control bus 20.

1003: The FIFO control unit 17 sets both the FIFO input control signal and the FIFO output control signal to a value based on the operation logic (input possible) shown in FIG. As a result, input to the FIFO buffer 15 is restarted.

Data transmission control is performed by repeating these operations.

Therefore, when performing transmission control processing of the SYN synchronous basic transmission control procedure, the processing amount of the common control section 14 is as shown in FIG. That is, when transmitting STX, start the block transmission monitoring timer and perform character transfer processing, when transmitting the first character data, start BC3 calculation and perform character transfer processing, and when transmitting character data, perform only character transfer processing. , At the time of ETX transmission, block transmission monitoring is stopped in the evening/immediately, BC3 calculation is stopped, and character transfer processing is performed.
At the time of BC8 transmission, only BC3 transfer processing is performed. Then, the average of these processing amounts is applied to the common control unit 14.

[Effects of the Invention] According to the present invention, by installing a FIFO buffer and a simple control circuit for controlling it, the time required for the processing amount of the common control unit in the transmission control processing of the SYN synchronous basic transmission control procedure can be reduced. By absorbing the fluctuations, it is possible to reduce the probability of underrun occurrence at the peak of the required processing amount of the common control unit.

This makes it possible to increase the line speed that can be accommodated regarding the SYN synchronization basic transmission control procedure and to increase the number of high-speed lines that can be accommodated.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an overview of the operation of a data transmission control method in an embodiment of the present invention, FIG. 2 is a configuration diagram of a communication control device in an embodiment of the present invention, and FIG. FI
FIG. 4 is an explanatory diagram showing an outline of the operational logic of the FO control section I7, and FIG. 4 is an explanatory diagram showing the required processing amount of the common control section in one embodiment of the present invention. l: Communication control bag! , 21 circuit terminating equipment (DCE). 3: Upper processing device, 11: Line control section, 12: Buffer memory section, 13: Upper processing device communication processing section. 14. Common control unit, 15: FIFO buffer, 16 High-speed clock generator, 17. FIFO control unit, 18: FIF
AND gate for O output control, 19:, 20: control bus,
21. High-speed clock transfer line, 22: FIFO input control signal transfer line, 23: FIFO input control transmission element timing signal line, 24. Internal transmission data signal line, 25.
Transmission data signal line. 26: FIFO output control signal transfer line, 27: Transmission element timing signal line, 28: FIFO output control transmission element timing signal line, 29 FIFO status information transfer line, 30. Transmission/reception information transfer line.

Claims (1)

[Claims] (1) A common control unit that performs message assembly/disassembly processing according to the transmission control procedure type and processing including instructions for creating/inspecting additional information for error detection, and character assembly/inspection according to the line type. Data of a device that transfers data based on the SYN synchronization basic transmission control procedure between a terminal device and a higher-level processing device connected via a line termination device and a communication line. In the transmission control method, a FIFO buffer and a circuit for controlling transmission data input from a line control unit to the FIFO buffer and stop/resumption of output to a line termination device are provided, and the line control unit controls the FIFO buffer When a character that is significant according to the transmission control procedure regulations is transmitted, an instruction request is issued to the common control unit, and the line control unit sends a message to the corresponding FIF.
Data transmission characterized by stopping the input of transmission data to the O buffer and restarting the input of transmission data to the FIFO buffer at the time when the common control unit issues an instruction corresponding to the instruction request to the line control unit. Control method.