JPH04119006A - Decision feedback type line equalizer with tap coefficient for precursor equalization - Google Patents

Abstract

PURPOSE:To extract an optimum phase by employing a decision feedback type line equalizer having a tap coefficient for precursor equalization so as to decide a value of a precursor accurately thereby operating an evaluation function of impulse response. CONSTITUTION:A line equalizer 45 wave-shapes a reception signal distorted through a transmission line to adjust its peak to a prescribed value such as the unity. An A/D converter(ADC) 46 uses a sample timing control signal outputted from a PLL circuit 49 to sample an output of the line equalizer 45 and converts the reception signal into a digital signal. A decision feedback type line equalizer (DFE) 47 having a tap coefficient for precursor equalization receives the reception signal sample value Xn and outputs a current correct reception symbol value an. An evaluation function section 48 uses the reception signal sample value Xn outputted from the ADC 46 and the equipment data symbol value an outputted from a decider in the DFE 47 to calculate an evaluation function in order to change a sample timing control signal outputted from the PLL circuit 49. When the DFE 47 is converged, impulse response sets h-1, h1-hN are coincident with C-1, C1-CN.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a decision feedback line equalizer with tap coefficients for precursor equalization that is incorporated in a data transceiver in a digital subscriber line transmission line and removes intersymbol interference of a received signal. , Accurately estimate the value of the precursor h-+ using a decision feedback line equalizer with tap coefficients for precursor equalization, and use that value to calculate the evaluation function of the impulse response.
The purpose is to perform timing recovery with the optimal phase, and the current value of the periodically transmitted code is an, the transmitted code value 1 to N cycles ago is an-1 to a n-N, and the transmission one cycle later is an. The code value is a−+, the impulse response sequence is ho,
h+ ~hN, and when the precursor is h-+, Xn=h-+a-, +ho a, due to intersymbol interference.

+h+ a,, -t + ...+tLs 'an-
In a decision feedback line equalizer that receives a received signal sample value represented by The residual error from a certain period before is used as an intermediate value for residual error estimation, and the result of subtracting the product of the tap coefficient C-+ for precursor equalization and the output of the current symbol value determiner from the intermediate value, and the current Using the output afi of the symbol value determiner and an-1 to an-N-I, equalization layer tap coefficients 01 to CN corresponding to the coefficients h1 to hN of the impulse response, respectively, and precursor equalization Update the evening knob coefficient C, C+ an-I +C2
an2 + 1. .

"C) tap coefficient updating means for outputting tan-N; subtraction means for taking the difference between the received sample value and the output of the tap coefficient updating means; and the output of the subtraction means is input, and and the symbol value determiner that outputs a symbol value.

[Industrial application field]

The present invention relates to an equalizer as a filter for compensating for intersymbol interference in a transmission path and deterioration of a transmission signal due to noise, and more specifically, the present invention relates to an equalizer that is incorporated in a data transceiver in a digital subscriber line transmission path and is used to compensate for received signals. This invention relates to a decision feedback line equalizer with tap coefficients for precursor equalization that eliminates intersymbol interference.

[Conventional technology]

When transmitting signals using, for example, the baseband transmission method in a cable transmission path, as the data transfer rate increases or the transmission distance increases, the waveform gradually becomes smoother due to attenuation in the high frequency region and the cutting of the DC component by a transformer. It has a long hem. In other words, the impulse response of the transmission path becomes gentle. Particularly in baseband transmission, interference from preceding and succeeding pulses, that is, intersymbol interference, which occurs due to waveform distortion, is an important problem.

A filter for compensating for such intersymbol interference and deterioration of the transmission system due to noise is generally called an equalizer.

FIG. 11 is an example of an impulse response of a cable transmission line. All communication systems are causal, and when time t is negative, the impulse response h (B is 0 and the impulse response is the 11th
The result is as shown in Figure (a), but by moving the time axis on the receiving side as shown in Figure (b), the peak occurrence time of the impulse response is set to 1 =
It is often set to 0.

In general, time-series human power ao is applied to a certain system at regular intervals.

For al, . . . a, the output at time n is the impulse response sequence ho, h+, . . . h, of the system.

It is generally given by convolution using the following equation.

When this is expressed in a block diagram using Z transformation, it becomes as shown in FIG.

FIG. 13 is an example of a non-recursive transversal filter for compensating for deterioration in the transmission system. In this other world, instead of the impulse response sequences ha, hl, . . . in the block diagram of FIG.
, C+, . . . are used. In such an isothermal world, the function of block z-1 corresponds to a shift register for realizing a one-cycle delay of the input signal sequence.

FIG. 14 shows a conventional example of a timing recovery circuit that detects the peak value of a received signal from a transmission path and generates a recovered clock with an optimal phase. In the figure, the received signal is input to a sample value detection and data symbol identification circuit 2 via a line 1 that performs waveform shaping of the received signal. The sample value detection circuit detects the sample value expressed in convolutional form as in equation (1), and the data symbol identification circuit detects the symbol value aO,a of the received signal.

...Identify the value of a. These sample values and data symbols are input to the evaluation function calculation circuit 3, from which the peak value of the impulse response is calculated. The estimated value of is output.

When the peak value ho of the impulse response is correctly detected, the reproduced clock is output with the optimum phase as shown in FIG. In Fig. 15, when the peak value of the impulse response is correctly detected, the value of the impulse response one cycle before is called the precursor h-+, and the value of the impulse response one cycle later is called the bost cursor. Ideally these values would be zero.

In FIG. 14, the estimated value of the peak value of the impulse response as the output of the evaluation function calculation circuit 3 is shown.

and a preset threshold value h o smaller than 1.
th is compared by the comparator 4, and as shown in FIG. 16, if the estimated value is larger than the threshold value, the recovered clock control circuit 5 advances the phase of the recovered clock, and if the estimated value is smaller than the threshold value, the recovered clock is advanced in phase. control is performed in the direction where the phase lags. By bringing the threshold value closer to the peak value 1 at the optimum phase (0), the phase of the recovered clock is controlled to approach the optimum phase.

[Problem to be solved by the invention]

In the peak detection type timing recovery circuit explained in FIG. 14, in order to detect the peak value of the impulse response, when the precursor h-+ is not O, this precursor causes intersymbol interference, and this interference is caused by line equalization. There is a problem in that the data symbol discrimination circuit cannot remove it by a device or the like, resulting in a judgment error in the data symbol identification circuit.

In addition, as a conventional timing reproduction method, the position of the precursor h-+ is detected on the assumption that it becomes 0,
There is also a precursor type in which the peak position of the impulse response is set one cycle later, but there is a problem that when the intersymbol interference is large, the precursor cannot be estimated accurately and timing cannot be recovered.

The present invention accurately estimates the value of the precursor h-+ using a decision feedback line or the like having tap coefficients for precursor equalization, calculates the evaluation function of the impulse response using the value, The purpose is to perform timing recovery with the optimal phase.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention. In the figure, the current value of the periodically transmitted code is an, the transmitted code values 1 to N cycles ago are an-1-an-N, the transmitted code value one cycle later is a-1, and the impulse response sequence. ho, hl
-hN, when the precursor is h-+, XI, = h-+a-1+hoa due to inter-symbol interference.

+h+an-+ +...+hNan-s is a principle block diagram of a decision feedback type line with tap coefficients for precursor equalization that receives received signal sample values represented by +hNan-s.

In FIG. 1, the Knob coefficient updating means 10 generates a current residual value, which is the difference between the output and input of the symbol value determiner for determining the symbol value of the current received signal within the decision feedback line equalizer. The error is delayed by one cycle, and the delayed residual error in the next cycle is used as an intermediate value for estimating the residual error of one cycle before, and from that intermediate value, the tap coefficient C-+ for precursor equalization and the current symbol value determiner are calculated. The result of subtracting the product with the output an and the outputs a n , a n of the symbol value judger
-1 to a n-N-1, equal substitute tap coefficients 01 to CN in the decision feedback equalizer and tap coefficients for precursor equalization corresponding to the above-mentioned impulse response sequences h1 to hN, respectively. Update C-I, C1an-10C2
Output a,, -2+...+CNa,, -N.

This output is, for example, a n-13n-2, .
..., a□8.

Further, the subtracting means 11 calculates the difference between the received signal sample value as input to the decision feedback line equalizer and the output of the tap coefficient updating means 10, and the symbol value determiner 12 calculates the difference between the output of the tap coefficient updating means 10 and the output of the subtracting means 11. and outputs the symbol value of the currently received code.

[Function] In the present invention, the basic concept is that the current value an. Xn = h in which the code value al-1-a1-N from 1 to N cycles before and the code value a-+ after 1 cycle are convolved
-, a-, +ha an+h+ an-l + . . . 10hNan-N are input to the decision feedback line equalizer. In order to correctly determine the symbol value a4 of the current received code, it is necessary to determine the received data symbol by setting all terms other than ho an of the received signal sample value Xn to 0.

However, the term including the precursor h-+ is determined by the transmitted code value one period later,
It is impossible to estimate this.

Therefore, in order to correspond to delaying the current judged received symbol by one period, the received symbol judgment value of one period before is set,
Similarly, in response to delaying the current residual error, which is the difference between the output and input of the symbol value judger, by one period,
The tamp coefficient is updated using the intermediate value for estimating the residual error before the cycle and using the estimated value of the tap coefficient C-+ for precursor equalization.

In Fig. 1, when the residual error becomes 0, the impulse response sequence h1 to hN will match the tap coefficients 01 to CN, so the value of C0 is set to 1 in advance as input to the symbol value judger. Therefore, approximately C-ta
, ta, and the intermediate value for residual error estimation is the output of the symbol value judger, that is, the judgment result is set as C-
,a,,+a,,-.

an-1', and an-1a as the result of the above subtraction
fl−+ (approximate value) is finally determined as the residual error,
Tap coefficient C-+, so that this residual error approaches 0,
And updates of C1 to CN are performed.

Then, when the residual error ideally becomes 0, the tap coefficient C-+ matches the precursor h-, and the input to the symbol value determiner takes the form h-, a-, +an, for example By setting the precursor h-+ to O in the calculation of the impulse response evaluation function, the input to the symbol value determiner completely matches the current transmission code value an.

As described above, in the present invention, it is possible to estimate the precursor h.

[Embodiment] FIG. 2 is an explanatory diagram of the basic concept of a decision feedback type line equalizer in the present invention. In the same figure, a decision feedback line equalizer (decision feedback line equalizer, DFE)
) is the input received signal sample value X. The current correct received symbol value an is output from the current correct received symbol value an.

In the same figure, a subtracter 1 inputs from the output of the determiner 15.
6 is used as a residual error for updating the tap coefficient, and this residual error is used as the residual error for updating the tap coefficient C-r for precursor equalization and the other tap coefficients C, (n=1 to N). The information is input to the update unit 18.

On the other hand, the received symbol value a, which is the output of the determiner 15, is -
T delay device 19 delays by -T, that is, one period T
Time is advanced by a. . 1, which is multiplied by C-1 output from the updating section 17 of C-1 by the multiplier 20, and the multiplication result is output to the subtracter 21.

Furthermore, the output an of the determiner 15 is the T delay device 21a...
21n sequentially, 1. . . , the symbol values a□−1, .
. Then, the subtracter 21 subtracts the output result of the multiplier 20 and the output result of the adder 23 from the received signal sample value X, , and inputs the result to the determiner 15 and the subtracter 16.

As a result, the impulse response sequences, , h, ~hN at the received signal sample values X, , are respectively changed to tap coefficients C-
+, C+ to C8, the input beam to the determiner 15. By setting only an and ho to 1, the determiner 15 outputs a correct received symbol value.

In Figure 2, the symbol to be received one period later is estimated in advance and multiplied by the tap coefficient C-1 as the estimated value of the precursor h-+, but in reality this is impossible. It is. FIG. 3 is a block diagram of an embodiment of a decision feedback line equalizer with tap coefficients for precursor equalization, and FIG. 4 is a flowchart of an embodiment of tap coefficient updating processing in this equalizer. The operation of the decision feedback line equalizer with tap coefficients for precursor equalization according to the present invention will be described with reference to FIGS. 3 and 4. FIG.

In step (S)25 in FIG. 4, first, each tap coefficient C-+ and C1 to CN are set to O as initial value settings, and an intermediate value ERR for residual error estimation, which will be described later, is set, for example, to a somewhat large value. be done. Thereafter, at 326, an echo replica YRFn of the equalizer is calculated.

This is to obtain the addition result by the adder 23, as explained in FIG.

In S27, the output signal of the subtracter 21 shown in FIG. 3 is calculated. That is, the difference between the current received signal sample (direct Here, it is assumed that there are four types of received symbol values, ±1 and ±3, and reception symbol value determination is performed by using, for example, +20 and -2 as slice levels (Sl).

Thereafter, in S29, residual error calculation for the equalizer section is performed. In other words, the current residual error register value ERR
o is the residual error ERR from one cycle ago.

After that, the subtracter 34 calculates the new current residual error ER as the difference between TMINO and the output of the determiner 15.
RO is obtained, and the result of multiplication by the multiplier 36 of the precursor equalization tap coefficient C,,1 and the output of the determiner 15 is subtracted from what is determined by the delay device 35 as the residual error ERR-E from one cycle before. 37 to obtain the final residual error value ERR. Then, (N+1) tap coefficients are updated at 330 using this residual error ERR, .

The precursor equalization tap coefficient C-+ is delayed by one period by the delay device 38. The delay result is added by the adder 41 to the product of the output of the determiner 15 and the residual error ERR-+ by the multiplier 39, for example, multiplied by a small negative constant α of the coefficient unit 40, and C-1 You can get the updated results. Here, +1 to the power of C-1 within the bronch of 830 represents the time at which the tap coefficient is updated.

In addition, in Fig. 4, C-+, C+~CN, YRF,..., a
o, etc. are all functions of the tap coefficient update time, and should be displayed, for example, as C-, but for the sake of simplicity, k is mostly omitted.

Other tap coefficients are updated in the same manner. For example, the tap coefficient 01 is delayed by one period by the delay device 38a, and the adder 41a multiplies the output of the determiner 15 by a n-2 and ERR as a result of the delay of two periods by the delay devices 21a and 42a. 39a is multiplied by α by the coefficient multiplier 40a, and a new Yu-Nbu coefficient 01 is obtained.

In FIG. 4, when the tap coefficient update process is completed in S30, a convergence determination is performed in S31. In the convergence determination, for example, when the value of the residual error ERR-1 becomes smaller than a predetermined threshold value, it is determined that it has converged, and if it has not become smaller than the threshold value, the value at the time when the tap coefficient update process is performed in S32 is determined. is set to +1, and the processing from 326 is repeated.

In FIG. 3, the explanation has been made assuming that all received symbol values are delayed by the sample period T of the received signal, but in the actual algorithm, this delay can be achieved by substituting ERRo into ERR−+ in S29 of FIG. 4, for example. carried out by
A delay of sample period T is not actually performed.

FIG. 5 is an explanatory diagram of tap coefficient updating based on the received impulse response waveform. In the figure, an impulse response that has a peak value at time A includes a precursor of the impulse response shown by a broken line that has a peak value one cycle later, that is, at time B.

The present invention utilizes the property that when the decision feedback line equalizer converges, the impulse response sequence h-+, h+ = hN matches the stamp coefficients C-1, C+ to CN.

First, the echo replica YRF of the decision feedback line equalizer is calculated at time, and then TMINo is calculated at time. Then, the TM containing the precursor h-+ at time B
Determine the received symbol value based on I No, subtract the product of the received symbol value and the precursor equalization tap coefficient CI from ERR-, and use that value as the new ERR-+ value. and update the tap coefficients.

FIG. 6 shows a first embodiment of a timing recovery circuit using a decision feedback line equalizer with tap coefficients for precursor equalization according to the present invention. In the figure, a line equalizer 45 shapes the waveform of a received signal distorted on the transmission path, and adjusts its peak value to a constant value, for example 1. An analog/digital converter (ADC) 46 samples the output of the line equalizer 45 using the sample timing control signal output from the PLL circuit 49, and converts the received signal into a digital signal. Decision feedback line equalizer with tap coefficient for precursor equalization (
DFE) 47 is exactly the same as that shown in FIG. The evaluation function unit 48 receives the received signal sample value X output from the ADC 46.
Using the received data symbol values a, .

FIG. 7 shows a second embodiment of the timing recovery circuit. In FIG. 7, instead of the received signal sample value Xfi as the output of the ADC 46, the evaluation function section 48 inputs the input signal to the determiner in the DFE 47, that is, the term from the received signal sample value X7 to the precursor h when the DFE converges. The configuration is exactly the same as that in FIG. 6, except that a signal from which intersymbol interference has been removed is output.

FIG. 8 is a configuration block diagram of an embodiment of the evaluation function section in FIGS. 6 and 7. In the figure, for the sake of simplicity, the value of N in the received signal sample value X1 is assumed to be 2. In Figure 8, the DF of Figures 6 and 7
Received data symbols a, I output by the determiner in E47
are sequentially input to delay devices 5o and 51, and an,
an-1, and a. -2 is the weighting function calculation circuit 52
is input.

On the other hand, the received signal sample value Xfi in FIG. 6 and the input signal to the determiner in FIG. , f, , -+, fn-2 are multiplied by multipliers 55, 56, and 57 with gn, g□r r gn-2 as the outputs of the weighting function calculation circuit, respectively, and the results are input to the adder 58. Then, as the addition result, the evaluation function Z,
, is obtained.

In FIG. 8, as mentioned above, N=2 and f n =
Xyl = hoan + h 1an-+ +hz a
n-z...(2) Zn ""gn fn +gn-+ fi-1+g
Using fi-, fn-z (3), the following equation is obtained as Z7.

・ ・ ・ ・ ・(4) Here, the peak value is determined by Zn. hl to estimate
By setting the coefficient of and h2 to 0, ・ ・ ・
(5) If the output g*+gn-+rgn-z of the weighting function calculation circuit 52 is determined so that this holds true, the peak value can be detected correctly.

The peak detection type evaluation function includes the precursor h-+ and is more generally defined by the following equation.

Here, E (an) is the expected value of afi, and E (
ao) is given as the average value of an, and E[a,, 2 is given as the variance of an, by the following equation.

Note that in (8) 2, an is random, and its average value is O.

In formula (6), f n” h−Ha −+ + ho afi+ h+
aIl-H+...+hHan-w
......(9), an'fn-h-1a-1an+hOaH" +h
) anan-1+...+hHanan-s...
Go) becomes. Assuming that the symbols an are temporally uncorrelated and random, then in general E (an-a, ,
-1)=O...-01) holds, and as a result, E (a,,・fn)=E (h-+a-+an)
+E[hoan2] 10E (h, a, an-1) + ・+ E (h
Nar, an-N) -E (ha an") -ho E (ar+") =h, a"・
・ ・ ・ ・The evaluation function of equation (6) is Z, =ho σ2 / σZ =h0.・, , −
It matches the peak value like α■. Therefore, as described above, Zfi is compared with a certain threshold value, and when Zfi is larger than the threshold value, timing control is performed to advance the phase, and when Zfi is smaller, to delay the phase. If comparison with a threshold is not performed, Z
What is necessary is to control in the direction of increasing fl.

Next, the precursor type evaluation function uses the timing extraction information as y(τ)=h(t-τ)-h(t+τ)...
・04 is used, it is given by Zn = E (a, f n-1ann ] ・05).

In formula 00, a6 fn-l = h-13,2+ha an an・
・+hNanan-N-+ + ・ ・ ・ ・ ・ (16) an-1fn =h-, a-, an-, tenho ana
.

+ h 1a n-12+・ ・ ・ ・ ・ ・ ・ ・q′7), and when we calculate the expected value of the equation 06) and (+7) in the same way as the equation Q2), the evaluation function of the zero equation is the following equation. becomes.

Zfi=h-1σ2HI σ2=(h-yo-hI)σ2
...08) If the side τ is determined so that the equation 08) is O, timing reproduction at the optimum phase is performed.

In addition, when using y(τ) = h (t-τ) ...09 as timing extraction information, the evaluation function of the precursor type is the following formula% z, = E Carrn-+; -・- --C
According to the formula D06), Z and l are as follows.

z,=h,, σ2...(21)
This formula is set to 0, that is, the precursor h-1 itself is set to 0.
If τ in equation 09) is determined as follows, timing reproduction at the optimum phase is performed.

As mentioned above, in the first embodiment of the timing recovery circuit shown in FIG. 6, the received data sample value Xn itself becomes the ffi input to the evaluation function section, but in the second embodiment shown in FIG. TM I N o as an input to f becomes an input. And in the case of peak detection type, T M I N
o is used as f in equation (6), and in the case of a precursor type, 051. In the ee formula, T M
I No is used as frI, and TMIN- is used as f n-1.

As explained in (Operation), the inputs to the symbol value determiner 12 in FIG. 1 and the determiner 15 in FIG. 3 are 71-+ an,l 0a when the residual error becomes O.

In the precursor type, when using the 12 (0 expression) as the evaluation function, the input to the determiner becomes only an. Also, when using the 05) expression, hl becomes 0 due to the action of the DFE. As it approaches, h-+ also converges to O at the side. Furthermore, in the case of the peak detection type, ±1. For symbol value determination of ±3, a certain degree of error can be tolerated for 7, and when the DFE converges, the value of C-+ becomes approximately O, so there is no problem in data symbol determination.

FIG. 9 is a flowchart of an embodiment of timing reproduction processing. In the same figure, steps 359 to S65 are almost the same as steps S25 to S30 in FIG. For the peak detection type, it is set to a somewhat large value, and to 0 for the peak detection type.
The difference is that the received signal sample value is calculated by the digital converter 46, and in 362, the current TMINo is set to the value of TMIN-+ one cycle before.

As in FIG. 4, after the tap coefficients are updated in S65, it is determined in 366 whether the number of tap coefficient updates k is greater than a certain constant value a. The value of a varies depending on the case, but is approximately several hundred to several thousand times. If it is determined in S66 that k is smaller than a, it is determined in S67 whether k is larger than the sum of a and b. Since k is naturally smaller than this sum, the value of time is incremented at 368, and S6
Processing is repeated from 0.

When the tap coefficient update number k becomes equal to or greater than a in S66, 36
At step 9, the evaluation function Zn is calculated. This calculation is performed in S67
until k becomes greater than or equal to the sum of a and b, that is, b times, 36
The process is repeated from 0, and the evaluation function calculation results b times are averaged in S69. b is ~120 times.

When k becomes greater than or equal to the sum of a and b in S67, the evaluation function Zfi is compared with the previous value (in the first case, the initial value) in S70, and the sampling phase of the analog/digital converter is changed to the precursor type in 371. Z in case. In the peak detection type, control is performed in a direction in which Zl becomes smaller, and in a peak detection type, in a direction in which Zl becomes larger. Here, in the precursor type, this phase control direction is the optimal timing phase when the evaluation function becomes O.
Further, in the peak detection type, the evaluation function is based on matching the peak value h0 of the impulse response.

After the sampling phase is controlled in step 371, step S7
At step 2, convergence determination is performed in the same manner as at 331 in FIG. If the convergence condition is not satisfied, the value of time is incremented in S73, and the processing from S60 is repeated.

As described above, in the present invention, when a received waveform having an impulse response with intersymbol interference is input, an evaluation function is used to reproduce the timing of the signal. In other words, among the impulse response sequences, h+, hz, . . .
·, an evaluation function is used to weaken the influence of hN.

In addition, due to other crimes such as judgment return type railway, J, ha,...
By accurately estimating h and l, the accuracy of the evaluation function can be further improved.

FIG. 10 shows a third embodiment of the timing recovery circuit.

In the figure, the precursor equalization tap coefficient C-1 as an estimated value of the precursor h in the DFE 47 is directly input to the evaluation function unit 48, and the evaluation function unit 48 uses the PLL to reduce this value. The configuration is the same as that shown in FIGS. 6 and 7, except that the sample timing signal output from the circuit 49 is controlled.

Furthermore, the processing in the timing regeneration circuit in FIG. 10 is as follows:
In the flowchart of FIG. 9, the evaluation function Zfi corresponds to the tap coefficient C-〇, the process of averaging 21 five times in S69 is eliminated, and the sampling phase is controlled in the direction of decreasing the tap coefficient C-+ in 371. The process is exactly the same as that shown in FIG. 9, except that .

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to estimate the precursor h-+ and perform line equalization, and the decision feedback type line equalizer with tap coefficient for precursor equalization of the present invention By installing this in the timing recovery circuit, it becomes possible to extract the optimal phase of the recovered clock quickly and reliably, which greatly contributes to improving the transmission performance in digital communication systems.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a diagram explaining the basic concept of the decision feedback line equalizer with tap coefficients for precursor equalization of the present invention. Figure 3 is for precursor equalization. A block diagram showing the configuration of an embodiment of a decision feedback line equalizer with tap coefficients, Fig. 4 is a flowchart of an embodiment of tap coefficient updating processing, and Fig. 5 shows tap coefficient updating processing using a received impulse response waveform. FIG. 6 is a block diagram showing the configuration of the first embodiment of the timing recovery circuit, FIG. 7 is a block diagram showing the configuration of the second embodiment of the timing recovery circuit, and FIG. 8 is the evaluation function. FIG. 9 is a block diagram showing the configuration of the third embodiment of the timing regeneration circuit; FIG. 9 is a flowchart of the timing regeneration processing example; FIG. 12 is a diagram showing an example of the impulse response of the transmission path, FIG. 12 is a diagram showing an example of a block diagram display by Z-transforming the output signal, FIG. 13 is a diagram showing an example of a non-recursive equalizer, and FIG. 14 is a diagram showing an example of a non-recursive equalizer. 15 is a diagram showing the relationship between the impulse response and the recovered clock, and FIG. 16 is a diagram explaining the phase control method of the recovered clock in the conventional example of FIG. 14. . 10... Tap coefficient updating means, 11... Power reduction means, C), - Symbol value determiner, - Determiner, - Update unit for C, - Update unit for Cn, - Line equalizer, - Analog/digital converter (AD)...Decision feedback line equalizer (DFE),...Evaluation function section,...PLL circuit.

Claims (1)

[Claims] 1) The current value of the periodically transmitted code is a_n, 1 to N.
The transmission code values before the cycle are a_n_-_1 to a_n, respectively.
When _-_N, the transmission code value after one cycle is a_-_1, the impulse response sequence is h_0, h_1 to h_N, and the precursor is h_-_1, Xn=h_- due to inter-symbol interference.
_1a_-_1+h_0a_n+h_1a_n_-_1
In a decision feedback line equalizer that receives received signal sample values represented by +...+h_Na_n_-_N,
The residual error from one cycle before, which is the difference between the output and the input of the symbol value determiner for determining the symbol value of the received signal in the decision feedback line equalizer, is used as an intermediate value for residual error estimation;
Pre-cursor equalization tap coefficient C_-_1 is calculated from the intermediate value.
The result of subtracting the product of and the output of the current symbol value determiner, the output a_n of the current symbol value determiner, and a_n
Update equalization tap coefficients C_1 to C_N and precursor equalization tap coefficients C_-_1 corresponding to the impulse response coefficients h_1 to h_N, respectively, using _-_1 to a_n_-_N_-_1; C_1a_n_-
_1+C_2a_n_-_2+...+C_Na_n_
-_N; a subtraction means (11) for taking the difference between the received sample value and the output of the tap coefficient update means; the output of the subtraction means (11) is input; The symbol value determiner (12) outputs the symbol value of the currently received code.
A decision feedback line equalizer with tap coefficients for precursor equalization, characterized by comprising: 2) In a timing recovery circuit that is built into a data transceiver in a digital subscriber line transmission line and extracts the optimum phase of a received signal, the received signal input is
An analog/digital converter that samples according to the sample timing control signal outputted by the LL circuit and converts it into a digital signal; and a received signal sample value outputted from the analog/digital converter is inputted to the tap for precursor equalization. A decision feedback line equalizer having coefficients, a receive signal sample value output from the analog/digital converter, and a decider that determines the symbol value of the current receive signal in the decision feedback line equalizer. an evaluation function unit which receives an output of the PLL circuit, calculates an evaluation function for the sample timing control, and controls an output signal of the PLL circuit according to the calculation result. . 3) A timing recovery circuit that is built into a data transceiver in a digital subscriber line transmission line and is used to extract the optimum phase of a received signal.
Analog/
A digital converter, a decision feedback line equalizer into which received signal sample values output from the analog/digital converter are input, and which has tap coefficients for precursor equalization; An input to a determiner that determines the symbol value of the current received signal and an output of the determiner are input, and an evaluation function for the sample timing control is calculated, and the PLL circuit is controlled according to the calculation result. A timing regeneration circuit comprising: an evaluation function section that controls an output signal. 4) Initialize all tap coefficients including those for precursor equalization of the decision feedback line equalizer, residual errors, and evaluation function average values, and update all tap coefficients of the decision feedback line equalizer. of,
The residual error from one cycle before, which is the difference between the output and input of the decider in the decision feedback line equalizer, is used as the intermediate value for residual error estimation, and the precursor equalization tap coefficient C_-_1 is calculated from the intermediate value. Iterates a number of times in the direction of decreasing the residual error as a result of subtracting the product of averaging the subtraction results, comparing the average value of the evaluation function with the average value of the previous evaluation function after the averaging, and controlling the sampling phase of the analog/digital converter in the direction of decreasing the evaluation function in the precursor type; Determine whether or not the residual error is smaller than a predetermined threshold, and if it is larger than the threshold, repeat the process after updating the tap coefficient, or repeat the process after the tap coefficient so that it is always 0. The timing regeneration method according to claim 2 or 3, characterized in that: 5) Initialize all tap coefficients including those for precursor equalization of the decision feedback line equalizer, residual errors, and evaluation function average values, and update all tap coefficients of the decision feedback line equalizer. of,
The residual error from one cycle before, which is the difference between the output and input of the decider in the decision feedback line equalizer, is used as the intermediate value for residual error estimation, and the precursor equalization tap coefficient C_-_1 is calculated from the intermediate value. and the output of the current symbol value determiner.
repeating the evaluation function a number of times, calculating the evaluation function b times after updating the tap coefficients a number of times, averaging the results of the b calculations, and comparing the average value of the evaluation function with the average value of the previous evaluation function after the averaging; controlling the sampling phase of the analog/digital converter in a direction to increase the evaluation function in the peak detection type; determining whether the residual error is smaller than a predetermined threshold; and if larger than the threshold, adjusting the tap coefficient; 4. The timing regeneration method according to claim 2, wherein the processing after the update is repeated. 6) A timing recovery circuit that is built into a data transceiver in a digital subscriber line transmission line and is used to extract the optimum phase of a received signal.
Analog/
A digital converter, a decision feedback line equalizer into which received signal sample values output from the analog/digital converter are input, and which has tap coefficients for precursor equalization; The input to a determiner that determines the symbol value of the received signal and the output of the determiner are input, and an evaluation function for the sample timing control is calculated, and the output signal of the PLL circuit is determined according to the calculation result. 1. A timing regeneration circuit comprising: an evaluation function section for controlling the timing regeneration circuit. 7) The timing recovery circuit according to claim 6, wherein the precursor value C_-_1 is used as the evaluation function.