JPH04117817A - Variable frequency divider - Google Patents

Abstract

PURPOSE:To increment a frequency division ratio by one with simple circuit constitution by substantially interrupting a variable frequency division output of a prescribed stage number of 2nd and succeeding stages attended with an AND output between a 1st logical level signal and a signal commanding to increment the frequency division ratio by one. CONSTITUTION:Variable frequency dividers 5, 6, 7, 8,... acting like 1/2 or 1/3 frequency dividers selectively are connected in cascade. Moreover, a NOR gate 1 is provided in place of a 1st stage inverter and an AND gate 10 controlling the pass of an output mod1 of a 2nd stage variable frequency divider 6 is provided. Then an output of the AND gate 10 is used as one input to an OR gate 11, and when a Q output of each variable frequency divider is all logic 0 and both a +1 signal and a setting input D0 are both logical 1, the variable frequency divider 5 act like 1/2 frequency dividers. When either the +1 signal or the setting input D0 is logical 1 and a Q output of the variable frequency dividers 6, 7, 8 is '000', the variable frequency divider 5 acts like a 1/3 frequency divider.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is suitable for a slip phase control PLL, etc., and is capable of selectively switching between frequency division by 2 and frequency division by 3. The present invention relates to a variable frequency dividing device for connecting and dividing the frequency of a human input signal.

[Prior art] This type of variable frequency divider has not existed in the past, but
It was proposed by the applicant in No. 276315. As shown in FIG.
5.47 and a buffer amplifier 43, the frequency division by 2 and the frequency division by 3 are set manually D i (D i - logic "1"
A desired frequency division ratio is obtained by cascading a plurality of variable frequency dividers that can be selectively switched depending on the level or logic "O" level, as shown in FIG.

The variable frequency divider described above has a logic 1f 11 at the OC terminal when the input signal at the MOD terminal is at the logic "1'" level.
The frequency of the signal input to the CP terminal is divided by two using a positive edge, and then sent to the Q terminal.

Also, when the input signal at the MOD terminal is at the logic "0" level, a signal with the same level as the 0 terminal is sent to the ○C terminal, and if the input signal at the D terminal is at the logic "1" level, the CP The input clock signal of the terminal is 3 with positive edge.
The frequency is divided and sent to the Q terminal. Furthermore, if the input signal at the D terminal is at the logic "o" level, the human input tarlock signal at the CP terminal is divided by two using a positive edge and sent to the Q terminal.

In a configuration in which multiple stages of variable frequency dividers are connected in series, the frequency division operation of the nth variable frequency divider is
When all the output signals of the terminals are zero, a frequency division operation of 2+D is performed only once according to the signal level of the D terminal, and then a frequency division operation of 2 is performed.

For example, when these variable frequency dividers are connected in cascade,
An example of a three-stage slave R connection will be described in which MOD2 in the third stage is grounded and set to the logic "o" level.

The input signal of the MOD2 terminal is always at the logic 1f 01 level, and when the D2 terminal (D2 signal) is at the logic '0' level, the CP2 signal is divided by two, and then the logic '1'
” level, performs frequency division operation by 3. That is, 2+
A frequency division operation of D2 is performed.

In the second stage variable frequency divider, 1
The frequency division operation is performed 2+DI times (D+ = 0 or 1), and the remaining frequency division operation is performed 1+D2 times. That is, in the second and third stage variable frequency dividers, IX (2+D+) + (1+D2) x2(2
+ D2 ) X 2 + D+ ...(
1) frequency division operation is performed.

Similarly, the divided output of the first stage variable frequency divider is (2+D2)
In order to send out 2+D clock signals, C(2+D2)x2+D+)x2+Do·(2) of the CPo signal is counted. In other words, the output from the third stage variable frequency divider in total is CPo 23+D2x22+D+
A frequency-divided output is obtained by dividing the frequency by x2' + Do x2° (3).

Similarly, in a variable frequency divider device in which n stages of variable frequency dividers are connected, 2" +Dn-I X 2"-' + +D2 X22+DI X2' +D[l
-(4) Frequency division operation is performed.

That is, 2″ to 2″ with n bits fixed to H-logic 1.
i...Continuous frequency division shown in (5) will be performed.

However, when a control signal is inputted to set the frequency division ratio to a frequency division ratio that is ``+1'l'' above the frequency division ratio, and the control signal for ``+1'' is manually inputted, the frequency division ratio becomes larger than the set frequency division ratio. There is no variable frequency dividing device that performs a frequency division operation with a frequency division ratio that is +1" higher.

[Problems to be Solved by the Invention] Therefore, for example, in order to divide the frequency with a frequency division ratio that is +1 higher than the set frequency division ratio using a programmable divider in a PLL, if the set value of the programmable divider is set to N bits, An N-bit adder is provided, and a signal for instructing a +1'' operation is added to the N-bit adder, so that the frequency dividing operation is performed at a rate ``+1'' more than the set frequency division ratio.

However, when using this configuration, an N-bit adder is required, which increases the circuit scale and signal processing scale.
There is a problem that the circuit configuration becomes complicated.

The present invention uses a simple circuit configuration to achieve a frequency division ratio of "-1-1".
``It is an object of the present invention to provide a variable frequency dividing device that can realize frequency dividing operation and solves the above problems.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a variable frequency divider that switches from a frequency division operation by two to a frequency division operation by three when the first signal and the second signal are at a predetermined logic level. In a variable frequency divider comprising multiple stages of frequency dividers connected in series, a signal instructing to increase the frequency division ratio by (+1) and a first signal at a logic level for operating the variable frequency divider by dividing the frequency by 3 are provided. and the variable frequency divider outputs of the second and subsequent stages constituting the variable frequency dividing device are substantially cut off in accordance with the output of the logic calculation means. The present invention is characterized in that it is detected that the output state of the frequency divider has become a predetermined pattern, and upon this detection, the second signal is set to the logic level when the first stage variable frequency divider performs the frequency division operation by three.

[Function] Since the variable frequency divider of the present invention is configured as described above, the signal instructing to increase the frequency division ratio by (+1) and the first logic level for operating the variable frequency divider by dividing the frequency by 3 are used. When the output of the variable frequency divider of the predetermined stages from the second stage onward is substantially cut off and the output state of the variable frequency divider from the second stage onward becomes the predetermined pattern. , the logic level of the second signal is the logic level when the first stage variable frequency divider performs the frequency division operation by three. As a result, the first stage variable frequency divider is switched to the frequency division operation by 3, and the frequency division ratio of the variable frequency divider is increased by +1).

[Example] The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of a first embodiment of the present invention.

Variable frequency divider for selectively dividing by 2 and 3 5.6.7.8
... to be connected subordinately.

As shown in FIG. 2, the variable frequency dividers 5,6,7,8,... Noah gate 3 using human power with 0 output of flip-flop 33
0, a D flip-flop 31 whose D input is the output of the NOR gate 30, and a Q output of the D flip-flop 31 and D
The D flip-flops 31 and 33 are equipped with an OR gate 32 whose output from the flip-flop 33 is human-powered, and a D-flip-flop 33 whose output is zero-powered. , read 0 manual force at the rising edge of the clock signal, and store it.

In addition, the variable frequency dividers 5,6,7,8...
The output of the OR gate that uses D(i) signal and rrlod(i-1) manually ○C(i-1) is the MOD of the previous stage.
OR gates 11, 12, 13, . . . are connected to provide a signal. In addition, (+1) signal and setting manual effort. is input to the NOR gate 1, and the output of the NOR gate 1 is the setting value d of the variable frequency divider 5. Binding, setting manual power D+ -D2, D3
. . . are each inverted by an inverter and then connected to the variable frequency divider 6.
．． 7.8...The setting manpower is d1, d2, d3.... Furthermore, (+1) signal and setting manual effort. is input to the Nant gate 9, the output of the Nant gate 9 and the mod1 output of the variable frequency divider 6 are input to the AND gate 10, and the output of the AND gate 10 is input to the OR gate 11 together with the MODI signal. In FIG. 1, the tarok pulse supplied to the variable frequency divider 5 is f. It is shown by .

In this embodiment configured as described above, the OR gate 4
8 corresponds to OR gate 11, 12, 13, OR gate 42 corresponds to OR gate 28, inverter 41 corresponds to NOAH gate 1 and Impark 2.3.4,
The variable frequency divider shown in FIG. The output mo of the second variable frequency divider 6
An AND gate 10 is provided to control the passage of dl, and the output of the AND gate 10 is used as one of the OR gates 11 instead of the output modl, so that the Q outputs of the variable frequency dividers 7, 8, etc. are all logical -"o 1) Signal and setting manual control. When both are logic ``1'' level, the variable frequency divider 5 is operated to divide the frequency by 2 regardless of the Q output of the variable frequency divider 6, and either the (+1) signal or the setting manually is the logic ``1'' level. When the Q output of the variable frequency divider 6.7.8 is "o o o", the variable frequency divider 5 is set to 3.
Operate frequency division.

In the first embodiment configured as described above, the clock pulse f. are sequentially divided by variable frequency dividers 5, 6, 7, . This frequency division operation is similar to the case of equation (4) described above.

The frequency dividing operation of the variable frequency divider 5 is as follows.

(When the +1> signal is at the logic "0" level, the Nant gate 9 outputs the H level, so the Nant gate 9)10 is m
Outputs the odl level as is. When the (Do) signal is at logic "1" level, NOR gate 1 is at logic "1" level.
o” level, and only when the Q outputs of the variable frequency divider 6.7.8 are all O, the clock pulse f. is divided by 3 using the positive edge and output to the Q. terminal. (D.) If the signal is at a logic level of 0°, then the NOR gate 1 is at a logic level of
1'' level, and divides the clock pulse f. by 2 using the positive edge and outputs it to the Q. terminal. (+1) signal is logic level 1'' level and (Do) signal is logic ``o'' level.
When the level is "1", the Nant gate 9 outputs the logic "1" level, so the AND gate 10 outputs the level of modl as it is.The NOR gate 1 outputs the logic "1" level.
clock pulse f only when the Q outputs of the variable frequency divider 6.7.8 are all 0. Divide the frequency by 3 with a positive edge and get Q. Output to the terminal.

When the (+1) signal is the logic level 1' and the (Do) signal is the logic LL11 level, the NOR gate 1 is the logic level.
o "Outputting level. Nantes gate 9 is logic"
o” level, so the AND gate 10 is mo
Outputs logic "O" level regardless of the level of dl. As a result, the Q terminal output of the variable frequency divider 6 becomes logic "0".
“At the level, the 0 terminal outputs of other variable frequency dividers are all logic.”
o” level, the clock pulse f. is divided by 3 by the positive edge and output to the Q. terminal. Also, the Q terminal output of the variable frequency divider 6.7.8 connected in multiple stages in cascade is 0.
(H, the same applies to hexadecimal novels)'' and '1 (H)''
When , the frequency is divided by 3 twice and the frequency is divided by +1.

The frequency dividing operation described above is shown in the timing charts of FIGS. 3a to 3c.

In FIG. 3a, (+1) signal, (Do>signal, (
Dl) signal and (D3) signal are at logic "o" level, and (D2) signal is at logic "1" level, output M
This is the case when OD3 is at the logic "o" level, and a 200 frequency divider is used. In Figure 3, the (Do) signal is changed to the logic ``1'' level from the state shown in Figure 3 a, and the (+1) signal is changed to the logic ``1'' level from the state shown in Figure 3 a. The variable frequency divider 5 divides the frequency by 3 once and operates as a 211 frequency divider when the Ql to Q3 terminal outputs are '0 (H)''. In Figure 3C, the third
This example shows the case where the (+1) signal and (Do) signal are changed to the logic "1" level from the state shown in Figure a, and Ql
When the Q3 terminal output is '1 (H)' and '0 (H)
) twice, the variable frequency divider 5 divides the frequency by 3, and the frequency becomes 22.
A 2 frequency divider is performed, and a (+1) frequency division operation is performed.

Next, a second embodiment of the present invention will be described.

FIG. 4 is a block diagram showing the configuration of a second embodiment of the present invention.

In this embodiment, instead of the AND gate 10 in the first embodiment, the output of the Nandt gate 9 and the output m of the variable frequency divider 7 are
An AND gate 24 whose input is 0d2 is provided, the output of the AND gate 24 is used as one input of the OR gate 12, and the output mocil of the variable frequency divider 6 is directly connected to the NOR gate 11.
It is composed of human resources. Furthermore, the output of the NOR gate 13 and the m0d2 output of the variable frequency divider 7 are input to the OR gate 22, and the output of the OR gate 22 is applied to the variable frequency divider 6 as MODI.

Therefore, as is clear from the above, in the second embodiment, both the (D.) signal and the (+1) signal are logic "
1'' level, the output m0d2 of the variable frequency divider 7 is prevented from being output by the AND gate 24, and the output m0d2 is
Regardless of the logic "o" level of o d 2 or the logic "1" level, the output of the AND gate 24 becomes the logic "0" level. Therefore, in the case of the first embodiment, "0"
Ql when the (+1) signal and (aO) signal are at the logic “1” level instead of “(H)” and “1(H)”
The variable frequency divider 5 performs frequency division by 3 twice when the Q3 terminal output is 0 (H) and 2 (H), and a (+1) frequency division operation is performed.

In each of the above-described embodiments, the operation is performed using the positive edge of the clock pulse fo, but the operation may be performed using the negative edge of the clock pulse fo.

Furthermore, the case where the (+1) frequency division operation is performed is the case where the output state of the variable frequency divider after the first stage is '2 (H)', and the case where the output state of the variable frequency divider after the first stage is '2 (H)', and
Although the case of H) "" has been described, the same configuration can be applied to other output states. Moreover, it can also be constructed using the frequency outputs of the variable frequency dividers 5, 6, 7, . . . .

[Effects of the Invention] As explained above, according to the present invention, the variable frequency divider is
The variable frequency division output of the predetermined stages from the second stage onwards is determined by the AND operation output of the first signal at the logic level for frequency division operation and the signal instructing to increase the division ratio by (+1). When it is detected that the output state of the second and subsequent stage variable frequency dividers has become a predetermined pattern by substantially cutting off, the first stage variable frequency divider divides the second signal by three. Therefore, when the predetermined pattern is set, the first stage variable frequency divider is switched to the frequency dividing operation by 3, and the frequency division ratio of the variable frequency divider circuit can be increased to (+1), and the configuration for this is also gated. It can be configured easily and easily.

In addition, if the present invention is applied to slip-phase PLL, a communication device in which the frequencies for transmission and reception are different and the frequency division ratio is set at any time when switching between transmission and reception, the present invention can be used to eliminate the setting time for switching the frequency division ratio and achieve high-speed operation. Frequency lock becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a block diagram showing an example of a variable frequency divider that can selectively switch between frequency division by 3 and frequency division by 2, and FIG. is a timing chart for explaining the operation of the first embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of the second embodiment of the present invention, and FIG. 5 is a variable frequency division diagram already proposed by the applicant. FIG. 2 is a block diagram showing the configuration of the device. 1.30...Nor gate 2.3.4...Inverter 5.6.7.8...Variable frequency divider 9...Nant gate 10.24...AND gate 11.12.13. 22...or gate

Claims (1)

[Claims] (1) In a variable frequency divider comprising multiple stages of variable frequency dividers connected in cascade, the frequency divider can be switched from frequency divider operation by two to frequency divider operation by three when the first signal and the second signal are at a predetermined logic level. Logic calculation means for a signal instructing to increase the ratio by (+1) and a first signal at a logic level for operating the variable frequency divider by dividing the frequency by 3; Detecting that the output state of the variable frequency divider from the second stage onwards has become a predetermined pattern by substantially cutting off the output of the variable frequency divider of the predetermined stage along with the output of the logic operation means, A variable frequency dividing device characterized in that the second signal is set to a logic level when the first stage variable frequency divider performs a frequency dividing operation by three.