JPH04117778A - Image pickup device - Google Patents

Abstract

PURPOSE:To improve the vertical resolution and to reduce flicker of a fluorescent light by generating a video signal by one field based on a charge resulting from an external signal generated and extracted for each period being an odd umber multiple of a 3-field period, storing tentatively the video signal and reading out the stored signal by an odd number of times corresponding to a prescribed number of fields. CONSTITUTION:A sample-and-hold circuit 2 and a signal processing circuit 3 are controlled by a timing generator 5 and operated for a period only when a video signal by one field is outputted from a CCD 1 to extract a video signal component. An A/D converter 8 is controlled by a memory control circuit 9 and operated for a period when the video signal is given from the signal processing circuit 3 and a data by the video signal by one field is outputted for one field period synchronously with the read pulse generated for each 3-field period. A 1st field memory 10 stores once the data and reads the data twice at an interval of one field period and gives it to a multiplexer 12. Thus, flicker of a reproduced picture is reduced and the vertical resolution is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an imaging device, and in particular, the present invention relates to an imaging device.
The present invention relates to an imaging device using a solid-state imaging device such as an e-coupled device.

[Prior Art] Most recent imaging devices such as video cameras and camera-integrated VTRs (video tape recorders) have CCDs as image sensors. In conventional imaging devices using CCD, the shutter speed used for photographing relatively slow-moving subjects under low illumination is usually (1/60 sec).
For example, it was 1/30 sec. That is, external light is irradiated onto the CCD for a period of 1/30 sec. FIG. 4 is a block diagram showing the configuration of such a low-speed shutter imaging device. Hereinafter, with reference to FIG. 4, a conventional low-speed shutter imaging device using COD will be described (a), taking as an example the case where the shutter speed is 1/3 Qsec.

In FIG. 4, the CCDI includes a photodiode section 1a and a vertical register section 1b. Photodiode section 1
a is a lens placed in front of the CCDI (not shown)
In response to external light that enters through the sensor, it generates and accumulates an amount of charge that corresponds to the intensity of this external light. The photodiode section 1a includes a large number of photodiodes arranged in a matrix to form a light receiving surface of the CCDI. External light is taken in by the lens and forms an optical image of the subject on this light receiving surface. Therefore, the optical image of the subject is converted into an electronic image by the photodiode section 1a. Charges accumulated in each of the photodiodes constituting the photodiode section 1a are transferred to the vertical register section 1b. The memory control circuit 9 controls this transfer timing via the timing generator 5 and the peripheral circuit 4.

In the following description, FIG. 5 will also be referred to.

FIG. 5 is a timing chart showing the operation timing of the imaging device shown in FIG. 4.

The peripheral circuit 4 is controlled by the timing generator 5 to generate a pulse (hereinafter referred to as a successive pulse) SG (see FIG. 5(b)) that instructs the CCDI to transfer charge from the photodiode section 1a to the vertical register section 1b. ), the vertical synchronizing pulse VD (Fig. 5(a)) is applied every two field periods.
Output in sync with. Therefore, the charges accumulated in the photodiode section 1a are transferred to the vertical register section 1b every two field periods. The charges accumulated in each of the photodiodes constituting the photodiode section 1a and transferred to the vertical register section 1b are given to the sample and hold circuit 2 as a voltage signal with a level corresponding to the amount thereof.

That is, the entire light receiving surface of the CCDI is scanned once every two field periods. Therefore, CCD1
If the light-receiving surface of is one screen, C
A voltage signal output from the CCDI corresponding to the charge transferred to the vertical register section 1b of the CDI includes a video signal component for one field.

The sample and hold circuit 2 samples the voltage signal given from the CCDI at a constant frequency under the control of the timing generator 5. By this, C
A video signal component is extracted from the output of the vertical register section 1b of the CD 1. The extracted video signal component is sent to the signal processing circuit 3
given to.

The signal processing circuit 3 is controlled by the timing generator 5 and performs special processing such as gamma processing and white balance processing on the given video signal component at a predetermined timing to create a normal analog video signal. do. This analog video signal is given to the A/D converter 8.

The A/D converter 8 is controlled by the memory control circuit 9 and converts the analog video signal provided from the signal processing circuit 3 into digital data over one field period. That is, the A/D converter 8 operates only during one field period synchronized with each read pulse SG applied to the CCD 1, as shown in FIG. 5(C). On the other hand, irradiation of external light onto the light receiving surface of the CCDI is interrupted every two field periods. Therefore, the charge transferred to the vertical register section 1b of the CCDI in response to an arbitrary readout pulse SG is accumulated in the photodiode section 1a during the two field period immediately before this arbitrary readout pulse SG is applied to the CCDI. Become something. Therefore, A
The digital data output from the /D converter 8 in one field period corresponds to the video signal obtained in two field periods before this one field period. Digital data output from A/D converter 8 is provided to field memory 10 and multiplexer 12.

The field memory 10 is controlled by the memory control circuit 9 to once store data corresponding to one field of video signals provided from the A/D converter 8 and then read it again and provide it to the multiplexer 12.

Specifically, the field memory 10 writes data when the write control signal FW given from the memory control circuit 9 is at the logic level "H", and when the successive control signal FR given from the memory control circuit 9 is at the logic level. Data is read when it is “H”. Write control signal F
W is the read pulse SG as shown in FIG. 5(d).
It becomes "H" level during one field period synchronized with . Therefore, one field of video signals outputted from the signal processing circuit 3 in response to any successive pulse SG is converted into digital data by the A/D converter 8 and temporarily stored in the field memory 10. On the other hand, as shown in FIG. 5(e), the successive control signal FR attains the "H" level in the next one field period after the write control signal FW attains the "H" level. Therefore, one field's worth of video signal data stored in the field memory 10 during any one field period is given to the multiplexer 12 during the next one field period.

As a result, the data of the video signal for one field outputted from the A/D converter 8 in any one field period is continuously sent to the multiplexer 12 in both this one field period and the next one field period. Given.

The multiplexer 12 is controlled by the memory control circuit 9 and transfers the output data of the A/D converter 8 to the D/A converter 1 during the period when the write control signal FW is "H level".
3, and during the period when the read control signal FR is at the "H" level, the read 8 data of the field memory 10 is given to the D/A converter 13. The D/A converter 13 is controlled by the memory control circuit 9, converts the digital data provided from the multiplexer 12 back to the original analog video signal, and outputs the converted signal. Therefore, the video signal output from the D/A converter 13 is as shown in FIG. 5(f).
For each field period, the data corresponding to the output data of the A/D converter 8 (A/D) and the field memory 1o
It switches to the one (M) corresponding to the read a data.

In this way, each of the video signals for one field extracted by the sample and hold circuit 2 is outputted from the D/A converter 13 as video signals for two fields forming one frame. The video signal output from the D/A converter 13 is passed through an LPF (low pass filter).
14 removes excess noise components, and then the signal is applied to the encoder 6. The LPF 14 removes, for example, a sampling frequency component (clock component) mixed into the video signal due to the sampling operations of the A/D converter 8 and the D/A converter 13.

The encoder 6 superimposes a predetermined synchronization signal, such as a horizontal synchronization pulse and a vertical synchronization pulse, supplied from a 5SG (synchronization signal generator) 7 on the video signal supplied from the LPF 14 to create a composite video signal.

This composite video signal becomes the output of this imaging device.

The 5SG7 generates a synchronization signal to be superimposed on the video signal in the encoder 6 and various timing pulses for controlling the operations of the timing generator 5 and the memory control circuit 9, and connects the encoder 6 and the memory control circuit 9 to each other.
It is output to the timing generator 5 and memory control circuit 9.

The timing generator 5 receives various timing pulses from the 5sG7 and a memory control circuit 9.
Based on the control signal given from the sample and hold circuit 2. Controls the signal processing circuit 3° and the peripheral circuit 4.

The memory control circuit 9 controls the timing generator 5.5 based on various timing pulses given from the 5SG7. A/D converter8. Field memory 10. and controls multiplexer 12.

Now, in the case of a normal imaging device where the shutter speed is one field period, that is, 1/60 sec,
The charge accumulation time in the CCDI required to obtain one field's worth of video signals is one field period. On the other hand, in the case of the above-mentioned low-speed shutter imaging device, the CCD required to obtain one field's worth of video signals is
The charge accumulation time in I is two field periods, which is twice that of a normal imaging device. Therefore, according to the low-speed shutter imaging device, the sensitivity of the CCD is twice that of a normal imaging device.

[Problems to be Solved by the Invention] As described above, in a conventional imaging device using a low-speed shutter, a video signal corresponding to the charge accumulated in a CCD during a two-field period is divided into two fields in which one frame consists of nt. , that is, video signals in each of an odd field and an even field. This is because a conventional imaging device using a low-speed shutter is only equipped with a memory that can store one field's worth of video signals.

Referring to FIG. 4, it is assumed that a CCDI that performs scanning based on interlaced scanning is used. In this case, in response to the read pulse SG, in the CCDI,
During one field period immediately after this readout pulse SG, the charges accumulated in the photodiodes constituting the odd-numbered scanning lines on the light-receiving surface of the CCD 1 are transferred to the vertical register section 1b.

Furthermore, the storage capacity of the field memory 10 corresponds to the amount of digital data of one field's worth of video signals. Therefore, the data that can be stored in the field memory 10 is
It is only the video signal for one field that is initially applied to the A/D converter 8 in response to the successive pulses SG. Therefore, in the composite video signal output from the encoder 6, the video signals of the odd and even fields constituting each frame are both obtained from the odd scanning lines on the light receiving surface of the CCDI.

As described above, when the signal components of the odd and even fields constituting one frame in the final composite video signal are the same, the following problem occurs.

That is, when this final composite video signal is applied to a receiver that reproduces images in an interlaced manner, the vertical resolution of the reproduced image deteriorates. This phenomenon will be explained in more detail below.

An interlaced receiver scans the odd scanning lines of the display in response to the odd field of the received composite video signal, and scans the even scanning lines of the display in response to the even field of the video signal. Display images. However, if the video signals of the odd-numbered field and the video signal of the even-numbered field are the same, an image will be displayed on the even-numbered scanning line of the display using the same video signal as the video signal of the previous scanning line (odd-numbered scanning line). It is done.

That is, in the receiver, an image for one screen is reproduced using video signals for half the actual number of scanning lines on the display. Therefore, the vertical resolution of the image reproduced by the final composite video signal is half of the standard.

Furthermore, according to a conventional imaging device using a low-speed shutter, flickering occurs in a reproduced image when an image of a subject illuminated by a lighting device driven by a commercial power supply with a frequency of 50 Hz is captured. This phenomenon will be specifically explained below.

For example, the light intensity of a fluorescent lamp fluctuates at a frequency twice as high as the frequency of the power source that drives the fluorescent lamp.

Therefore, if you image a subject under fluorescent light in an area where the commercial power frequency is 50 Hz, the COD
The intensity of the external light irradiated onto the light-receiving surface varies at a frequency of 100 Hz as shown in FIG. 5(g). On the other hand, in a conventional imaging device using a low-speed shutter (see Fig. 4), charge is accumulated in the COD every two field periods in response to external light, so the COD is used to obtain video signals for one field. The charge accumulation time is two field periods (1/30 sec). Therefore, the average value of the signals for l fields output from the CCDI in response to any read pulse SG is the 2 fields immediately before this read pulse SG.
It is proportional to the total amount of light irradiated to the photodiode section 1a of the CCD 1 during the field period. Therefore, in order for the average values of the video signals of each field output from the encoder 6 to be equal to each other, it is necessary to
The amount of light incident on the CCDI during the field period must be constant. For example, when external light causes flicker with a frequency of 100 Hz, if the charge accumulation time of one charge of the CCD is an integral multiple of the flicker period (1/100 sec) of the external light, the image of each field output from the encoder 6 The average value of the signal remains constant. However, C.C.
Since the amount of charge stored in D1 at one time is 1/30 sec,
In the composite video signal outputted from the encoder 6, 2
The average values for each field are different from each other. The average value of each field of the video signal corresponds to the brightness of the entire image reproduced thereby. Therefore, if the average value of the final composite video signal is non-uniform between fields, flicker will occur in the reproduced image.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above-mentioned problems and provide a low-speed shutter imaging device that can obtain reproduced images with excellent vertical resolution and reduced fluorescent lamp flicker. be.

[Means for Solving the Problems] In order to achieve the above-mentioned objects, an imaging device according to the present invention includes a charge generation and accumulation means that generates and accumulates charges in response to external light, and a charge generation and accumulation means that generates and accumulates charges in response to external light. a charge taking 8 means for taking out the charge accumulated in the storage means in response to an external signal; an external signal providing means for generating the external signal every odd multiple of three field periods and applying it to the taking 8 means; The apparatus includes a video signal creation means for creating one field's worth of video signals based on the charge extracted by the extraction means, and a storage means capable of simultaneously storing at least two fields' worth of video signals. This storage means stores each of the video signals for one field created by the video signal creation means.
It is configured to temporarily store the data and read and output the odd number of times at intervals corresponding to a predetermined number of fields. The imaging device according to the present invention further includes a linking unit that links the output of the video signal generating unit and the output of the storage unit at a predetermined timing.

[Operation] Since the imaging device according to the present invention is configured as described above,
An external signal instructing the charge extraction means to extract the charge from the charge generation and storage means is generated every odd multiple of the three field periods. As a result, the charge extraction means extracts the charge from the charge generation and accumulation means every odd multiple of the three field periods.
The charges accumulated during the period of odd number times immediately before the external signal is applied are taken out. As a result, each of the video signals for one field created by the video signal creation means has 3
It has a level corresponding to the amount of charge generated and accumulated in the charge generation and accumulation means during a period that is an odd multiple of the field period.

Further, since the storage means can simultaneously store at least two fields worth of video signals, each of the one field worth of video signals created by the video signal creation means can be temporarily stored in the storage means, thereby providing a predetermined amount of data. is applied to the splicing means multiple times at intervals corresponding to the number field. Therefore, if the splicing timing of the splicing means is set appropriately, two temporally adjacent video signals (for one field) created by the video signal creation means are always arranged alternately at the output of the splicing means. You can do it like this.

[Embodiment] FIG. 1 is a block diagram showing the configuration of a low-speed shutter imaging device according to an embodiment of the present invention.

Referring to FIG. 1, this imaging device has functions for storing digital data output from an A/D converter 8 in addition to the functional units included in the conventional low-speed shutter imaging device shown in FIG. As a functional part of the second field memory 1
1 is newly included. The first field memory 10 in FIG. 1 corresponds to the field memory 10 in FIG. Furthermore, peripheral circuits 4 in this imaging device. Timing generator 5. The memory control circuit 9 includes a CCDI, a sample hold circuit 2. Signal processing circuit 3. A/D converter8. First field memory 10. Multiplexer 12. And it operates so as to control the operation timing of the D/A converter 13 to a timing different from the conventional one. Hereinafter, the configuration and operation of the imaging device of this embodiment will be specifically described with reference to FIG. 2 as well. Figure 2 shows
FIG. 2 is a timing chart showing the operation timing of an internal circuit of the imaging device shown in FIG. 1; In this implementation (in this case, CC
It is assumed that the DI has a configuration capable of performing one image based on interlaced scanning.

In FIG. 1, the CCD 1 includes a photodiode section 1a that receives external light incident through a lens (not shown) and a vertical register section b, as in the conventional case. Charge transfer from the photodiode section 1a to the vertical L register section 1b is performed in response to a read pulse SG applied from the peripheral circuit 4.

However, unlike the conventional case, the peripheral circuit 4 is controlled by a six-timing generator 5 to vertically synchronize the readout pulse SG (FIG. 2(b)) every three yield periods, that is, every l/2 (lsec). Pulse VD (Fig. 2 (
Output in synchronization with a)). Therefore, charge transfer from the photodiode section 1a to the vertical register section 1b in the CCDI is performed every three field periods.

The vertical register section 1b supplies the charge transferred from the photodiode section 1a to the sample-and-hold circuit 2 as a voltage signal, so that the sample-and-hold circuit 2 receives a voltage signal containing one field's worth of video signal components from the CCDI every three field periods. is given. Therefore, the sample hold circuit 2 and the signal processing circuit 3 are each controlled by the timing generator 5, and the period during which one field worth of video signal is output from the CCD 1, that is, 3
It operates only during one field period immediately after the readout pulse SG is output from the peripheral circuit 4 for each field period, and performs general operations such as extraction of video signal components and gamma processing and white balance adjustment for the extracted video signal components. Process. The analog video signal processed by the signal processing circuit 3 is provided to an A/D converter 8.

The A/D converter 8 is controlled by the memory control circuit 9, operates only during the period when the video signal is supplied from the signal processing circuit 3, and converts the supplied video signal into digital data. Therefore, as shown in FIG. 2(c), the A/D converter 8 outputs 8 fields of video signal data in one field period synchronized with the successive pulses SG generated every three field periods. Powered.

This data is applied to a first field memory 10, a second field memory 11, and a multiplexer 12.

The first field memory 10 is controlled by the memory control circuit 9 to once store the data provided from the A/D converter 8, and then reads the data twice every one field period and provides the data to the multiplexer 12.

Specifically, the first field memory 10 receives the odd number write control signal FOW given from the memory control circuit 9.
Data is written only during the period when is at the "H" level, and stored data is read only during the period when the odd read control signal FOR applied from the memory control circuit 9 is at the "H" level. As shown in FIG. 2(d), the odd number write control signal FOW is at the "H" level for one field period synchronized with the read pulse SG every six field periods. On the other hand, as shown in FIG. 2(g), the odd number read control signal FOR becomes "H" level in one field period after one field period from the period in which the odd number write control signal FOW is "H" level. , Furthermore, in one field period one field period after this one field period, “
Therefore, the data of the video signal for 1 field output from the A/D converter 8 in response to each read pulse SG every 6 field periods is 1 field synchronized with this successive pulse SG. The data of the video signal for one field is directly applied to the multiplexer 12 during the field period.The data of the video signal for one field is applied to each of the one field period after one field period and the one field period after three field periods from this one field period. is given to the multiplexer 12 via the first field memory 10. That is, the same one field worth of video signal data is given to the multiplexer 12 three times every one field period.

On the other hand, the second field memory 11 is controlled by the memory control circuit 9, and the second field memory 11 is controlled by the memory control circuit 9.
It operates during a period when A/D converter 8 is not operating, and stores and continues to output data that is not stored in first field memory 10 among the data output from A/D converter 8.

Specifically, the second field memory 11 receives an even number write control signal FEW given from the memory control circuit 9.
Data is written during the period in which the even number read control signal FE given from the memory control circuit 9 is at “H” level.
The stored data is read during the period when W is "H". As shown in FIG. 2(e), the even number write control signal FEW is a 1 read pulse SG other than the read 8 pulse SG corresponding to each period in which the odd number write control signal FOW is at the "H" level. It becomes "H" level only during the field period.

On the other hand, as shown in FIG. 2(h), the even number read control signal FER is set to 1 field period after one field period when the even number write control signal FEW is at the "H" level.
It becomes "H" level during the field period and one field period after three field periods. Therefore, one field is output from the CCDI in response to each of the eight read pulses SG before and after the read pulse SG corresponding to an arbitrary one field period in which one field worth of video signal is stored in the first field memory 10. The data of the video signal for 10 minutes is written in the second field memory 11 during one field period synchronized with the preceding and succeeding pulses SG,
Thereafter, it is read out twice every one field period. As a result, the same one field worth of video signal data is given to the multiplexer 12 three times every one field period.

As a result, the data given to the multiplexer 12 is
In a period of 6 fields, output data of A/D converter 8 → read data of second field memory 11 → read a data of first field memory 10 output data of A/D converter 8 → read data of first field memory 10 The data is switched every one field period in the order of 8 data→read data of second field memory 11→. The multiplexer 12 is controlled by the memory control circuit 9 and receives the odd write control signal F.
During the period when the OR or even number write control signal FEW is at the "H" level, the output data of the A/D converter 8 is given to the D/A converter 13, and during the period when the odd number successive write control signal FOR is at the "H" level. The read data of the first field memory 10 is applied to the D/A converter 13, and the even number successive control signal FER is “
During the period when the second field memory 11 is at H'' level, the read data of the second field memory 11 is provided to the D/A converter 13.

The D/A converter 13 is controlled by the memory control circuit 9 as in the conventional case, and returns the applied data to the original analog video signal. Therefore, the video signal output from the D/A converter 13 is as shown in FIG. 2(i).
Data for one field (A/D
) → From second field memory 11 to multiplexer 12
1 field of data (FE) given to the first field memory 10 → 1 field of data (FO) given to the multiplexer 12 from the first field memory 10 → A/D converter 8
1 field of data (A/D) directly given to the multiplexer 12 from the 1st field memory 10 → 1 field of data (FO) given to the multiplexer 12 from the 1st field memory 10 → 2nd field memory 11 to the multiplexer 12 Data for one given field (F
E) is switched every one field period in this order. In other words,
Referring to FIG. 2, the video signal for one field obtained in response to successive pulses S61 is the first one of the six field periods from readout pulse SG1 to readout pulse SG3.
Third. and LPF in the fifth field period, respectively.
14 to the encoder 6. On the other hand, one field worth of video signals obtained in response to the successive pulse SG2 following the successive pulse SGI are provided to the encoder 6 during the fourth and sixth one field periods of the six field periods. Then, in the second one field period of the six field periods, the read pulse S
A video signal for one field obtained in response to the successive pulses (not shown) before 61 is applied to the encoder 6.

In this embodiment, the CCD 1 performs scanning based on interlaced scanning. The CCDI is controlled by the field discrimination signal Fl, and receives a voltage signal corresponding to the charge accumulated in the photodiodes forming the odd-numbered scanning lines on its light-receiving surface C, and a voltage signal corresponding to the charge accumulated in the photodiodes forming the even-numbered scanning lines. The paired voltage signals are output alternately.

Specifically, the level of the field discrimination signal FM is inverted every one field period, as shown in FIG. 2(f). During the period when the field discrimination signal Fl is at the "H" level, charges accumulated in the photodiodes constituting the odd-numbered scanning lines in the CCD 1 are transferred to the vertical register section 1b during one field period immediately after the read pulse SG. Conversely, during the period when the field discrimination signal FI is at the "L" level, the charges accumulated in the photodiodes constituting the even-numbered scanning lines on the light receiving surface are stored in the vertical register section 1b during one field period immediately after the readout pulse SG. be transferred.

On the other hand, the reading 8 pulse SG is generated every three field periods. Therefore, in response to any read pulse SG, CC
One field's worth of video signal outputted from DI and one field's worth of video signal outputted from CCD 1 in response to each of the readout pulses SG before and after this arbitrary successive pulse SGO are on different scanning lines. It is obtained from.

That is, for example, the read pulse SG in FIG. 2(b)
The video signal for one field obtained in response to I is CC
If it corresponds to the odd numbered scanning lines on the light receiving surface of D1, the video signal for one field obtained in response to the next read pulse SG2 corresponds to the even numbered scanning lines on the light receiving surface of CCDI. Then, the video signal for one field obtained in response to the next successive pulse SG3 corresponds to the odd-numbered scanning line. Therefore, read pulse SG1
In each of the three frames within the six field period from to SG3, video signals obtained from the odd and even scanning lines of the light receiving surface of the CCDI are applied to the encoder 6 in the even and odd fields, respectively.

The encoder 6 superimposes a predetermined synchronization signal provided from the 5SG 7 on the video signal provided via the LPF 14, as in the conventional case. As a result, unlike in the past, in the composite video signal output from the encoder 6, the even and odd fields of each frame are the video signal obtained from the odd scanning line on the light receiving surface of the CCDI and the even field on the light receiving surface of the CCD 1, respectively. It is composed of video signals obtained from scanning lines. Therefore, if the output of the encoder 6 is applied to an interlaced receiver, the vertical resolution of the image reproduced on the display of this receiver will be the same as that when the output of a conventional low-speed shutter imaging device is applied to the receiver. It will be doubled.

Further, in this embodiment, charge transfer from the photodiode section 1a to the vertical register section 1b in the CCD 1 is performed every three field periods, so the shutter speed is set for three field periods.

That is, charges are accumulated in the CCDI every three field periods synchronized with the read pulse SG in response to external light. Therefore, in this embodiment, the charge accumulation time in the CCDI to obtain one field's worth of video signals is three field periods. On the other hand, the average value of each field of the final composite video signal is proportional to the total amount of light irradiated onto the light receiving surface of the CCDI to obtain the video signal of that field. Therefore, if this total amount differs from field to field, the average value of the final composite video signal will differ from field to field. However, CC to obtain one field worth of video signal
The charge accumulation time in D1 is equal to the flicker period (1/100 sec) of a fluorescent lamp driven by a 50H2 commercial power supply.
; see Figure 2 (j)), that is, 1/100
(sec) x5 (=1/20 sec). Therefore, even if you use this imaging device to image a subject under illumination light such as fluorescent lighting in an area where the commercial power frequency is 50 Hz, the average level of each field in the final composite video signal will vary. becomes constant. Therefore, the flicker that conventionally occurs in reproduced images obtained by photographing under such an environment is sufficiently reduced.

In addition, a CCD 1 for obtaining a video signal for one field.
Since the charge accumulation time is 3 field periods, which is 1.5 times that of a conventional low-speed shutter imaging device, the sensitivity of the CCDI is effectively 1.5 times that of the conventional one.

In the above embodiment, one charge accumulation time of CCDI is 3 field periods, or n of 3 field periods.
A similar effect can be obtained if the period is doubled (n is any odd number) (for example, 9 field periods). Of course, in this case, charge is accumulated in the CCDI every (3Xn) field periods in response to external light.

FIG. 3 is a diagram showing an example of the configuration of a light-receiving surface of a CCD that is preferably used in the imaging device according to the present invention. Referring to FIG. 3, the light receiving surface of the COD includes, for example, rows in which magenta color separation filters Mg and green color separation filters G are arranged alternately, and cyan color separation filters Cy.
and yellow color separation filters ye are arranged in alternating rows. The columns containing color separation filters Mg and G and the columns containing color separation filters Cy and ye are arranged alternately. These color separation filters Mg.

One photodiode is provided corresponding to each of G, (4, and ye). In response to SG, the columns t1, 12, . and the charge accumulated in the photodiode constituting t5,
. . are sequentially transferred to the vertical register section 1b of the CCDI in FIG. 1 as eight outputs of odd-numbered scanning lines 1, 2, . Then, in response to the read pulse SG generated during the period when the frame discrimination signal FI is at the "L" level, the columns 11. 12. 13. . . . or two lines are simultaneously scanned in a different combination from the previous case in the arrangement order.

That is, the charges accumulated in the photodiodes forming columns t1 and t2, and the charges accumulated in the photodiodes forming scan lines L3 and 14.

. . are sequentially transferred to the vertical register section 1b as outputs of even-numbered scanning lines 1, 2, . . . , respectively. That is, one scanning line is formed by two color separation filter rows, and the combinations of these two color separation filter rows are made different between odd and even fields to obtain an interlaced video signal.

[Effects of the Invention] As described above, according to the present invention, the charge accumulation time in the COD to obtain one field of video signals is an odd multiple of three field periods, so flicker with a frequency of 100 Hz is generated. Flicker in a reproduced image obtained by imaging under bright external light is significantly reduced, and the apparent sensitivity of COD is improved. Furthermore, since it is possible to temporarily store one field worth of video signals obtained from each of the odd and even scanning lines on the light receiving surface of the CCD, the odd and even fields correspond to the odd scanning lines on the light receiving surface of the CCD. And a video signal composed of signal components obtained from even-numbered scanning lines can be derived. As a result, the vertical resolution of the reproduced image is significantly improved compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a low-speed shutter imaging device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of the imaging device shown in FIG. 1,
FIG. 3 is a diagram showing an example of the configuration of the light-receiving surface of the COD in FIG. 1, FIG. 4 is a block diagram showing the configuration of a conventional low-speed shutter imaging device, and FIG. 5 is the imaging device shown in FIG. 4. FIG. 2 is a timing chart diagram for explaining the operation of FIG. In the figure, 1 is a CCD, 2 is a sample and hold circuit,
3 is a signal processing circuit, 4 is a peripheral circuit, 5 is a timing generator, 6 is an encoder, 7 is an SSG, 8 is an A/D converter, 9 is a memory control circuit, 10 is a first field memory, 11 is a second field 12 is a multiplexer, 13 is a D/A converter, and 14 is an LPF. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] Charge generation/storage means for generating and accumulating charges in response to external light; means for extracting the charges accumulated in the charge generation/storage means in response to an external signal; external signal applying means that generates a signal every odd multiple of three field periods and applies it to the extracting means; and an image forming apparatus that creates a video signal for one field based on the charge extracted by the extracting means. a signal generating means; temporarily storing each of the video signals for one field generated by the video signal generating means, and reading the video signals a number of times according to the odd number at intervals corresponding to a predetermined number of fields; a storage means for outputting the output, the storage means being able to simultaneously store at least two fields worth of video signals, and further comprising means for connecting the output of the creation means and the output of the storage means at a predetermined timing. equipped with an imaging device.