JPH04114509A - Emitter coupled logic circuit - Google Patents

Abstract

PURPOSE:To realize a high speed operation through the use of a constant current circuit whose current capacity is small by temporarily changing a switching current supplied to transistors constituting a logic circuit only when the level of an input signal supplied to an input terminal is changed. CONSTITUTION:When the input signal SIN impressed on the input terminal 14 changes from a logical level 'L' which is lower than a reference voltage VREF1 impressed on a reference voltage terminal 16 to a higher logical level 'H', the emitter voltage of a transistor Q1 rises by the input signal SIN. The raised voltage is capacitance-coupled to the base of a transistor Q3 through a capacitor C1 and the base voltage of the transistor Q3 temporarily rises. Thus, a current IS1 flowing in a resistor R3 temporarily increases and the increased current flows from a ground terminal 12 through a load resistor R1 and the transistor Q1 as the switching current. Then, the voltage of an output terminal 18 is speedily dropped. Thus, the high speed operation can be realized by using the constant current circuit whose current capacity is small.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to emitter-coupled logic circuits, and is particularly concerned with suppressing the current in a steady state. The present invention relates to an emitter-coupled logic circuit that can transmit data.

[Conventional technology]

FIG. 3 shows an example of a conventionally known emitter-coupled logic circuit. In the same figure, transistor Q1
．． The emitters of Q2 are connected to each other and commonly connected to the constant current circuit 8. One end of the constant current circuit 8 is connected to a negative voltage Ve.
It is connected to the negative power supply terminal 10 which is supplied with power. The collector of the transistor Ql is connected to the ground terminal 12 via a first load resistor R1, and the collector of the transistor Q2 is also connected to the ground terminal 12 via a second load resistor R2. The base of the transistor Ql is connected to the input terminal 14 supplied with the input signal SIN, and the base of the transistor Q2 is connected to the reference voltage terminal 16 supplied with the reference voltage RI. The collector of transistor Ql is connected to output terminal 18.

An input signal applied to input terminal 14 or a reference voltage terminal 16
When the reference voltage V applied to is higher, that is, when the input signal is at "H" level, the transistor Ql is turned on, the transistor Q2 is turned off, and the current I flowing through the constant current circuit 8 is entirely the first load. Since the current flows through the resistor R1, a voltage drop occurs in the first load resistor R1, and the voltage is applied to the output terminal 18.
The input signal applied to the input terminal 14 or the reference voltage V. If it is lower than 1, that is, the output is "L" level.
``When the level is high, the transistor Ql is off and the transistor Q2 is on, and the current I.

flows through the second load resistor R2, so there is no voltage drop at the first load resistor R1, and the output terminal 18 has a "H" voltage.
This causes the circuit of FIG. 3 to operate as an inverter.

[Invention or problem to be solved]

In the conventional logic circuit as described above, a relatively large constant current I5 always flows from the constant current circuit 8 even in a steady state regardless of the level of the input signal, so the disadvantage is that the power consumption is large. In addition, in order to speed up the operation of the circuit, it is necessary to rapidly charge the junction capacitance and wiring capacitance of the transistor, so it is necessary to increase the current capacity of the constant current circuit 8 itself, which reduces power consumption. It was a hindrance.

This invention was made in order to eliminate the drawbacks of conventional logic circuits as described above, and it is an emitter-coupled logic circuit that can operate at high speed using a constant current circuit with a relatively small current capacity. The purpose is to obtain.

[Means to solve the problem]

In the emitter-coupled logic circuit of the present invention, the emitters are connected in common, and the collectors are connected to the first
and a current source connected between the emitter common connection point and the second power supply terminal, the current source being connected to the first power supply terminal.
and a constant current source that supplies a constant current to the second transistor, and (1) a current that is supplied to the first and second transistors only when the logic level of the input signal applied to the base of the first transistor changes. and a control circuit for temporarily changing the first and second transistors so that they respond quickly to changes in the level of the input signal.

(Function) In the emitter-coupled logic circuit of the present invention, the transistor is configured such that the transistor responds quickly to a change in the level of the input signal only when the level of the input signal supplied to the input terminal changes. By temporarily changing the current supplied to the transistor, high-speed operation is obtained, and in steady state, the current supplied to the transistor is kept relatively low.

(Example) An emitter-coupled logic circuit of the present invention will be described below with reference to FIG.

FIG. 1 shows a first embodiment of an emitter-coupled logic circuit according to the present invention, and elements equivalent to those of the conventional circuit shown in FIG. 3 are designated by reference numbers. In the same figure, transistors Q1, Q2
The emitters of are interconnected and commonly connected to a current source 28. One end of the current source 28 is connected to the negative power supply terminal 10 to which, for example, a negative voltage Vee is applied. The collector of the transistor Ql is connected to, for example, the ground terminal 12 via a first load resistor R1, and the collector of the transistor Q2 is also connected to the ground terminal 12 via a second load resistor R2. Further, the base of the transistor Ql is connected to the input terminal 14 to which the input signal SrN is supplied, and the collector is connected to the output terminal 18. The base of transistor Q2 is connected to a reference voltage terminal 16, which is supplied with a first reference voltage VREFI.

The current source 28 is connected to a transistor Q3 connected to the negative power supply terminal 10 of Vee through the emitter or resistor R3, and to the negative power supply terminal 10 of Vee also connected to the negative power supply terminal 10 of Vee through the emitter or resistor R4.
and a transistor Q4 connected to the transistor Q4. The collector of transistor Q3 is connected to transistor Q1. It is connected to the interconnected emitter common connection point of Q2, and its base is connected to the emitter of transistor Q4. The base of transistor Q4 is connected to the second reference voltage VFIEF2.
It is connected to a reference voltage terminal 20, which is supplied with a power supply voltage, and its collector is connected to a power supply terminal at a suitable level, such as a ground terminal. As a result, transistor Q4,
A constant current ■8□ flows through the resistor R4. Further, a capacitor C1 is connected between the collector and base of the transistor Q3. This capacitor C1 is a resistor R
4 constitutes a differentiating circuit, and the first and second transistors Q are activated only when the logic level of the input signal applied to the base of the first transistor Q changes.
It operates as a control circuit that temporarily changes the current supplied to the emitter common connection point of I and Q2.

Next, the operation of the circuit shown in FIG. 1 will be explained. Transistors Q3 and Q4 and resistors R3 and R4 in the current source 2ε constitute a constant current circuit, and the input signal SIN applied to the input terminal 14 is in a steady state of "H" level or "L" level. During this period, the base potential of transistor Q3 is the second reference voltage V applied to the base of transistor Q4. F2
and the base-emitter offset voltage Vbe of the transistor Q4, a constant voltage V, lEF□-
Clamped to Vbe, transistor Q3 passes a constant current ISI through resistor R3. The magnitude of the output voltage obtained from the output terminal 18 is determined by the magnitude of this current LSI and the value of the load resistor R1, so the current ts+ and the load resistor R1 are The value is preset.

When the input signal SIN applied to the input terminal 14 changes from a logic level "L" which is lower than the reference voltage VIIEFI applied to the reference voltage terminal 16 to a logic level "H" which is higher, the input signal SIN causes the transistor Ql to The emitter voltage of C increases, and this increased voltage is applied to the capacitor C.
1 and capacitively coupled to the base of the transistor Q3, and the base voltage of the transistor Q3 temporarily increases. Therefore, the current ISI flowing through the resistor R3 also temporarily increases. This increased current flows as a switching current from the ground terminal 12 through the load resistor R1 and the transistor Ql, and rapidly lowers the voltage at the output terminal 18.

The base voltage of the transistor Q3, which has increased over time, is reduced to a second constant voltage Vl11! applied to the base of the transistor Q4 by the action of the resistor R4. The constant voltage VREF2 Vbe determined by F2 and the base-emitter offset voltage Vbe of the transistor Q4 settles to a steady state.

Either the input signal SIN applied to the input terminal 14 or the reference voltage Vllll! applied to the reference voltage terminal 16. When the logic level ° higher than Fl changes from "H" to a lower logic level "L", the emitter voltage of the transistor Ql decreases, and this decreased voltage passes through the capacitor CI to the transistor Q.
The base voltage of the transistor Q3 is capacitively coupled to the base of the transistor Q3, and the base voltage of the transistor Q3 is temporarily lowered. Therefore, the current (1) flowing through the resistor R3 also temporarily decreases. Due to this decrease in current, the voltage drop across the load resistor R1 decreases rapidly, and the output terminal 1
8. Raise the voltage rapidly. The base voltage of the transistor Q3, which has decreased over time, settles to the constant voltage VREF2Vbe due to the action of the resistor R4, and enters the first steady state.

As mentioned above, the emitter-coupled logic circuit of the present invention is
Only when the level of the input signal applied to the input terminal 14 changes, the change in the current flowing through the load resistor R1 or R2 is changed to emphasize it, so that the switching speed becomes faster. Furthermore, the current rs+ in the steady state can be kept relatively low compared to conventional circuits.

FIG. 2 shows a second emitter-coupled logic circuit according to the present invention.
In the embodiment of transistor Q1. Three transistors Q3, Q serve as a current source 38 connected between the common emitter connection point of Q2 and the terminal 10 to which the negative voltage Vee is supplied.
4. Something consisting of Q5 is used. That is, the emitter of the transistor Q3 is connected to the negative power supply terminal lO through the resistor R3, and the collector is connected to the transistor Q1,
It is connected to the common emitter connection point of Q2, and its base is connected to the reference voltage terminal 22 to which the third reference voltage VREF:l is applied. As a result, a constant current 1,1 flows through the resistor R3. The base of transistor Q4 is connected to the second reference voltage v*! Reference voltage terminal 20 to which r2 is applied
The collector is connected to an electrical terminal at an appropriate level, such as a ground terminal, and the emitter is connected to a resistor R.
4 and is connected to the negative power supply terminal lO. This causes transistor Q4. A constant current I52 flows through resistor R4. Further, the collector of transistor Q5 is connected to the collector of transistor Q3, the emitter is connected to the negative power supply terminal lO, and the base is connected to the collector of transistor Q4.
is connected to the emitter of Also, transistor Q5
A capacitor C1 is connected between the collector and base of. Similar to the embodiment of FIG. 1, this capacitor C
I constitutes a differentiating circuit together with the resistor R4, and the first and second transistors Q1 . It operates as a control circuit that temporarily changes the current supplied to Q2.

Next, the operation of the circuit shown in FIG. 2 will be explained. Input signal S applied to input terminal 14. While in the steady state of N, "H" level or L level, the base potential of the transistor Q5 is equal to the second reference voltage VllEF2 applied to the base of the transistor Q4 and the base-emitter offset voltage Vbe of the transistor Q4. is clamped to a constant voltage V, lr+r2Vbe determined by , and transistor Q5 conducts a constant current 13.3.
The magnitude of the output voltage obtained from the output terminal 18 is determined by the total value of the constant current IS+ flowing through the transistor Q3 and the transistor Q3, and the value of the load resistor R1. Current 151, l5ff,
Each value of the load resistance R1 is set.

When the input signal SIN applied to the input terminal 14 or the reference voltage V applied to the reference voltage terminal 16 changes from a logic level "L" lower than 1EF1 to a logic level "H" higher, the transistor The emitter voltage of Q1 increases, and this increased voltage is applied to the capacitor CI.
is capacitively coupled to the base of transistor Q5, and the base voltage of transistor Q5 temporarily increases. Therefore, the current f1. flowing through the transistor Q5. Is
+ also increases temporarily. This increased current 1s3 is Is
1) flows as a switching current from ground terminal 12 through load resistor R1 and transistor Q1, rapidly pulling down the voltage at output terminal 18. Above - The base voltage of transistor Q5 which increased over time is due to the action of resistor R4.
The above-mentioned constant voltage VREF2 is determined by the second constant voltage VREF2 applied to the base of the transistor Q4 and the base-emitter offset voltage Vbe of the transistor Q4.
It settles down to Vbe and becomes a steady state.

When the input signal SIN applied to the input terminal 14 or the reference voltage VFIEFI applied to the reference voltage terminal 16 changes from a logic level ``H'' higher than that to a logic level ``L'' lower, the emitter voltage of the transistor Ql decreases. However, this reduced voltage passes through capacitor CI to transistor Q5.
The base voltage of the transistor Q5 is capacitively coupled to the base of the transistor Q5, and the base voltage of the transistor Q5 is temporarily lowered. Therefore, transistor Q5
The current Is3 flowing through it also decreases temporarily. Due to this decrease in current, the voltage drop across the load resistor R1 is rapidly reduced, and the voltage at the output terminal 18 is rapidly raised. The base voltage of the transistor Q5, which has been reduced poetically, settles to the constant voltage V*EF2Vbe due to the action of the resistor R4, and enters the first steady state.

This second embodiment also has an input terminal 1, similar to the first embodiment.
The switching speed is increased by emphasizing the change in the current flowing through the load resistor R1 or R2 only when the level of the input signal applied to the load resistor R1 or R2 changes. Moreover, the current ISl+IS3 in the steady state can be kept relatively low compared to the conventional circuit.

It goes without saying that various modifications may be made in addition to the above-mentioned embodiments. For example, another constant current source may be used in place of the emitter resistor R4 of the transistor Q4, or the transistor Q4 itself may be replaced with a diode.

Further, one end of the capacitor CI can be connected to any point that generates a signal in phase with the input signal applied to the input terminal 14, for example, to the input terminal 14 or the collector of the second transistor Q2. May be connected.

In addition to the inverter circuit, this invention also provides a 2NOR circuit, a 3N
It can be applied to any circuit that mainly generates an inverted output, such as an OR circuit, 4NOR circuit, etc.

〔Effect of the invention〕

As described above, in the emitter-coupled logic circuit of the present invention, only when the level of the input signal supplied to the input terminal changes, the transistors constituting the logic circuit respond quickly to the change in the level of the input signal. By temporarily changing the switching current supplied to the transistor, high-speed operation can be achieved, and in a steady state, the current supplied to the transistor can be kept relatively low, resulting in low power consumption. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of an emitter-coupled logic circuit of the present invention, FIG. 2 is a circuit diagram of a second embodiment of an emitter-coupled logic circuit of this invention, and FIG. 3 is a circuit diagram of a conventional emitter-coupled logic circuit. FIG. 2 is a circuit diagram showing an example of an emitter-coupled logic circuit. Ql...first transistor, Q2...second transistor, Q3...third transistor, R1...
First load resistance, R2...Second load resistance, R3...
・Resistance, CI...cono answer, lO...negative power supply terminal, 12...ground terminal, 14...input terminal, 16...
-Reference voltage terminal, 18...output terminal, 28...current source, 38...current source. 1st (2)

Claims (3)

[Claims] (1) First and second transistors whose emitters are commonly connected and whose collectors are connected to a first power supply terminal via a first load resistor and a second load resistor, respectively, and the emitter common connection point. and a second power supply terminal; the current source is a constant current source that flows a constant current through the emitter common connection point of the first and second transistors; These first and second transistors allow current to flow through the common emitter connection point only when the logic level of the input signal applied to the input terminal connected to the base of the first transistor changes. 1. An emitter-coupled logic circuit comprising: a control circuit that temporarily changes the logic level in a direction that responds quickly to changes in logic level. (2) The control circuit temporarily increases the current flowing through the emitter common connection point when the logic level of the input signal applied to the input terminal changes from a low logic level to a high logic level, and applies the current to the input terminal. Claim 1 characterized in that the current flowing through the emitter common connection point is temporarily reduced when the logic level of the input signal changed from a high logic level to a low logic level.
) emitter-coupled logic circuit. (3) The current source includes a third transistor whose collector is connected to the emitter common connection point, whose emitter is connected directly or through a resistor to the second power supply terminal, and whose base is applied with a constant reference voltage. Claim (1) characterized in that it consists of a constant current source and a control circuit including a capacitor connected between the base of the third transistor and a point where a signal in phase with the input signal appears. emitter-coupled logic circuit.