JPH0411432A - Digital signal reproducing circuit - Google Patents

Abstract

PURPOSE:To reproduce a digital signal from which noise is completely eliminated by setting a count means to an active state at one state, e.g. H level of a demodulated digital signal, counting a clock signal and comparing the result with a reference value. CONSTITUTION:When a signal shown in the Figure (a) is fed from a demodulation circuit 11, a counter circuit 13 counts clocks when an output from the circuit 11 is at an H level and its count is changed as shown in the Figure (d). The count is fed to a comparator circuit 14, where the count is compared with a reference value. The reference value is set to N/2 (fractions below decimal point are omitted) when number of times of generation of clock signals for data generating period is N. In this case, let N be 5 and the reference value be 3. When the count of clocks is advanced and the result reaches 3, the output of the circuit 14 goes to H (in the Figure (e)), the output is latched in a latch circuit 15 in response to the rising of the output of the 2nd clock source 16 (in the Figure (b)) and the circuit 13 is reset in response to the falling of the output of the 2nd clock source 16. The output of the circuit 15 is latched till a succeeding output of the source 16 is received.

Description

[Detailed description of the invention] (b) Industrial application fields The present invention relates to a digital signal reproducing circuit.

(B) Prior Art Conventionally, in the transmission of digital signals, in order to efficiently utilize the transmission medium, information signals are transmitted by applying digital modulation such as phase shift keying (PSK).

As described above, a Costas loop as shown in FIG. 3 is known as a circuit for demodulating a two-phase phase shift keying signal and reproducing an information signal.

In Figure 3, (1) is an input terminal, (2) is a voltage controlled oscillator (VCO) that oscillates a carrier signal, and (3) is a two-phase phase shift keying signal supplied from input terminal (1) and a VCO. The first multiplier (4) multiplies the oscillation signal supplied from the input terminal (1) with the oscillation signal supplied from the input terminal (1).
A second multiplier that multiplies the oscillation signal from the VCO (2) phase-shifted by 0 degrees, (6) a tenth bus filter connected to the output side of the first multiplier (3), (7) is the second multiplier (
4), the 20th bus filter connected to the output side of (8)
) is a third multiplier that multiplies the output of the 10th-pass filter (6) and the output of the 20th-pass filter (7); (9)
is a loop filter connected to the output side of the third multiplier (8) and supplies the low frequency signal component to the VCO (2) as a control signal.

Next, the operation will be explained.

Now, the input signal is ±Ac o s(ωt+φ), [where φ
is the phase difference between the output of vCO and the input signal, then the output of the first multiplier (3) that multiplies this input signal and the output signal cosωt from the VCO is ±A/2(cosφ+c
os(2ωt+φ), and the signal that has passed through the 10th pass filter (6) has the high frequency signal component removed and becomes ±A/2cosφ. Note that when the value of φ is small, the output of the 10th-pass filter (6) becomes ±A/2, that is, a two-phase phase shift key ink signal.

On the other hand, the output of the second multiplier (4) that multiplies the output sinωt of the phase shifter (5) and the input signal is ±A/2(sinφ
15 inches (2ωt+φ)), and the signal passed through the 20th bus filter (7) becomes ±A/2sinφ.

The output of the third multiplier (8) that multiplies the outputs of the first and 20th bus filters (6) and (7) is A''/4sjn
2φ=A2φ/2, which is proportional to the phase difference φ.

Therefore, by controlling the oscillation output of the VCO (2) so that the phase difference becomes O based on the output of the third multiplier (8), it is possible to demodulate the two-phase phase shift keying signal.

(c) Problems to be Solved by the Invention According to the above Costas Loop, when noise occurs on the signal transmission path, the noise is removed by an analog filter such as the 10th pass filter. The problem is that noise cannot be completely removed, and noise remains in the demodulated signal.

(d) Means for Solving the Problems In view of the above points, the present invention provides a demodulating means for demodulating an input digital modulated signal, and an active state in one state of the digital signal demodulated by the demodulating means. a counting means configured to count clock signals from a first clock source in said active state; and a counting means having a lower frequency than the clock signal from said first clock source and supplying a reset signal to said counting means. It is characterized by comprising two clock sources, a comparison means for comparing the output from the counting means with a reference value, and a holding means for holding the output of the comparison means.

(E) Effect According to the present invention, the counting means is set to the active state in one state of the digital signal demodulated by the demodulating means such as the Costas loop, for example, at H level, and the clock signal from the first clock source is set to the active state. Count.

Then, this counting result is compared with a reference value, and the value is output as a reproduced digital signal.

(F) Embodiment FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, (10) is an input terminal to which a digitally modulated signal is supplied, and (11) is a demodulation circuit that demodulates the digitally modulated signal to the original digital signal. If the supplied signal is a two-phase phase shift keying signal, it is configured with a Costas loop. (1
2) is the first clock source, and (13) is when the digital signal demodulated by the demodulation circuit (11) is in the H level state,
A counting circuit that counts clock signals from the first clock source (12), (14) a comparison circuit that compares the count value from the counting circuit (13) and a reference value, and (15) a comparison circuit (1
A holding circuit (16) holds the output signal from the holding circuit (16), which is a second clock source composed of a PLL that generates a signal synchronized with the edge of the digital signal based on the output of the holding circuit (15).

Note that the output signal from the second clock source (16) is supplied as a reset signal to the counting circuit (13), and the counting circuit (13) is reset in response to the fall of this signal. The output signal from the clock source (16) is also supplied to a holding circuit (15), and the holding circuit (16) holds the output signal of the comparison circuit (14) in response to the rise of this signal.

Next, the operation will be explained.

Now, the signal as shown in Fig. 2(a) is sent to the demodulation circuit (11).
When the counting circuit (13) is supplied from the demodulating circuit (
When the output signal from 11) is at H level, the clock signal [Figure 2 (C)] is counted, and the counted value is shown in Figure 2 (cl
).

Such a count value is supplied to a comparison circuit (14) and compared with a reference value. If the number of clock signal occurrences in one data generation period is N times, the reference value is N/2.
(rounded down to the nearest whole number). In this case, N=5 and the reference value is 3.

The counting of clock signals in each data period progresses, and when the counting result reaches 3, the output E2 of the comparator circuit (14)
Referring to figure (e), the clock becomes H level, and the second clock source (1
The H level output is held by the holding circuit (15) in response to the rising edge of the output signal from 6) [see FIG. 2(b)]. Thereafter, the counting circuit (13) is reset in response to the fall of the output signal from the second clock source (16).

The output of the holding circuit (15) is connected to the second clock source (16).
) until the next output is supplied.

In this way, a digital signal with noise removed is reproduced.

(G) Effects of the Invention According to the present invention, even if noise occurs on a signal transmission path, it is possible to reproduce a digital signal from which the noise has been completely removed.

[Brief explanation of drawings]

Figure 1 shows an embodiment of the present invention, Figure 2 (a) (
b)(c)(d)(e)(f) are waveform charts for explaining the present invention, and FIG. 3 is a diagram showing a conventional example. (10)...Input terminal, (11)...Demodulation circuit, (
12)...second clock source, (13)...counting circuit, (14)...comparison circuit, (15)...holding circuit,
(16)...Second clock source.

Claims (1)

[Claims] (1) A demodulation means for demodulating an input digital modulation signal, and a digital signal demodulated by the demodulation means, which is set to an active state in one state, and receives a clock signal from a first clock source in the active state. a second clock source having a lower frequency than the clock signal from the first clock source and supplying a reset signal to the counting means; and an output from the counting means and a reference value. A digital signal reproducing circuit comprising a comparison means for comparison and a holding means for holding the output of the comparison means.