JPH0411428Y2 - - Google Patents

Description

[Detailed description of the invention] Industrial application field The present invention relates to a video signal delay circuit, and in particular, an input horizontal transfer register, a plurality of columns of vertical transfer registers, and an output horizontal transfer register are arranged in a matrix. The present invention relates to a video signal delay circuit having at least a semiconductor delay circuit section and capable of visually reducing the influence of leakage of horizontal transfer pulses when outputting an input composite video signal after delaying it.

Prior Art Conventionally, in VTRs and other video signal reproducing devices, a noise reduction circuit for reducing noise contained in a reproduced composite video signal by utilizing so-called line correlation has been designed to reduce the noise contained in the reproduced composite video signal by one horizontal scanning period (1H). ) or one field delay circuit is provided, and the delay circuit is also used for dropout compensation and the like. As described above, video signal delay circuits have conventionally been used for various purposes. 1st
The figure shows a block system diagram of an example of this conventional video signal delay circuit. In the figure, a composite video signal as shown in FIG. 2A that has entered the input terminal 1 is supplied to the input horizontal transfer register 3 of the semiconductor delay circuit section 2, and is also supplied to the horizontal synchronization signal separation circuit 8. . The semiconductor delay circuit section 2 includes an input horizontal transfer register 3
It consists of an input vertical transfer gate 4, m columns of vertical transfer registers 5 ₁ to 5m, an output vertical transfer gate 6, and an output horizontal transfer register 7.

The above registers 3 and 5 ₁ to 7 are composed of a plurality of cells of a charge coupled device (CCD), for example, and the horizontal transfer registers 3 and 7 each have 455 cells in the horizontal direction for reasons described later. As a result, the number m of columns of vertical transfer registers 5 ₁ to 5m is 455. The number of stages (the number of cells arranged in the vertical direction) of each of the vertical transfer registers ₅₁ to 5m is 261 in one column, and one vertical transfer is performed in one horizontal scanning period (1H). , a delay time of 262H can be obtained.

On the other hand, the horizontal synchronization signal taken out from the horizontal synchronization signal separation circuit 8 is supplied to a horizontal transfer pulse generation circuit 9, a vertical transfer gate pulse generation circuit 10, and a vertical transfer pulse generation circuit 11, respectively. The horizontal transfer pulse generation circuit 9 generates a horizontal transfer pulse _{φ H} as shown in FIG. The signals are supplied to the horizontal transfer registers 7, respectively. Further, the vertical transfer gate pulse generation circuit 10 generates a gate pulse φ _G as shown in _{FIG .} A gate pulse φ _G shown in H in the figure is generated and supplied to the output vertical transfer gate 6.

Further, the vertical transfer pulse generating circuit 11 generates four-phase vertical transfer pulses φV ₁ , φV ₂ , φV ₃ and _φV4 as shown in FIG. 2D, E, F and G once every 1H, respectively. It is supplied to vertical transfer registers 5 ₁ to 5m.
Further, the output horizontal transfer register 7 is supplied with horizontal transfer pulses φ _H (shown in FIG. 2()) and _H from the horizontal transfer pulse generation circuit 9, respectively.

The input composite video signal is transferred horizontally within the horizontal transfer register 3 using the horizontal transfer pulses φ _{H and H} , and is held therein, so that the stored information in the register 3 is based on the input viewing video signal when the horizontal transfer pulse φ is used. _H ,
The result is a signal similar to that sampled at _φH . here,
Assuming that the input composite video signal band is 0 to 2.5MHz,
According to the sampling theorem, the sampling frequency (i.e. horizontal transfer frequency) must be 5MHz or higher. Here, the horizontal transfer frequency is set to 7.16MHz, which is 455 times the horizontal scanning frequency _H. on the other hand,
Vertical transfer is performed for approximately 1 us out of 1H (≈63.5 us), but horizontal transfer is not possible during this vertical transfer period, so horizontal transfer is not performed during the 1.4 us period during which the vertical transfer gates 4 and 6 are open.

Here _, as shown in FIG _. 3D, the vertical transfer gate pulse is located within the horizontal blanking period of the input composite video signal shown in FIG. As shown in C, the level is kept at a constant level during the 1.4 us period including the vertical transfer gate pulse generation period so that no horizontal transfer is performed. This 1.4us
is 10 periods (10 pulses) of horizontal transfer pulse φ _H , _H
minutes, so 445 (=455-10) horizontal transfer pulses φ _H , _H are generated and output within 1H. The number of stages (number of cells) of horizontal transfer registers 3 and 7 is 445.
Since it is sufficient to hold the input composite video signal to its full capacity with horizontal transfer pulses φ _H and _H , the number of stages is 445.

The input composite video signal is horizontally transferred in the input horizontal transfer register 3 using 445 horizontal transfer pulses φ _H and _H with a period of 1/(455f _H ), and then transferred by a vertical transfer gate pulse φ _G with a width of 1 us. The input vertical transfer gate 4 is opened, and the 445 pieces of sampling information held in the horizontal transfer register 3 are transferred in parallel to 445 columns of vertical transfer registers ₅₁ to 5m (here, m is 445).
is supplied to The vertical transfer registers 5 ₁ to 5m are
Every time a 4-phase vertical transfer pulse φ _V1 φ _V4 comes in, the input sampling information is transferred to the next stage (next row), and after 262 transfers, the output vertical transfer gate 6
The output horizontal transfer register 7 is supplied in parallel through the output horizontal transfer register 7. The output horizontal transfer register 7 outputs this parallel input sampling information in series within 1H based on the horizontal transfer pulses φ _H and _H , and takes it out to the output terminal 13 via the low-pass filter 12 . The reduction filter 12 is for removing frequency components of the horizontal transfer pulses φ _H and _H.

In this way, the input composite video signal is output to the output terminal 13 after being delayed by 262H.

Problems to be Solved by the Invention In the conventional circuit described above, a horizontal transfer pulse frequency component is mixed into the output composite video signal of the output horizontal transfer register 7, which deteriorates the reproduced image quality. This frequency component was removed to prevent deterioration of the reproduced image quality. However, this low-pass filter 12 sufficiently blocks the transmission of the above-mentioned horizontal transfer pulse frequency component since the frequency is slightly higher than twice the upper limit frequency of the band to which the input composite video signal is to be transmitted. To achieve this, a filter with a narrow band and steep cut-off frequency characteristics was required, which created the problem that a plurality of low-pass filter circuit configurations would be effective.

Therefore, this invention changes the phase of the horizontal transfer pulse to 1H.
It is an object of the present invention to provide a video delay circuit that solves the above problems by inverting each time.

Means for Solving the Problems The present invention causes a horizontal transfer pulse generation circuit to oscillate and output a signal having a frequency related to the horizontal transfer pulse frequency, and to be forcibly reset by a horizontal synchronization signal in an input composite video signal. oscillation means; and a circuit for generating a signal equal to the repetition frequency of the horizontal transfer pulse from the output signal of the oscillation means and whose phase is inverted every horizontal scanning period of the input composite video signal, and outputting the generated signal as a horizontal transfer pulse. Each of the embodiments thereof will be described below with reference to FIGS. 3 to 5.

Embodiment The present invention is based on a semiconductor delay circuit section 2 as shown in FIG.
The present invention relates to a horizontal transfer pulse generation circuit in a video signal delay circuit having a video signal delay circuit, and the overall block configuration itself is the same as that in FIG. FIG. 3 shows a circuit system diagram of a first embodiment of the main part of the circuit of the present invention (that is, the horizontal transfer pulse generation circuit). In the figure, the horizontal synchronizing signal in the input composite video signal to be delayed that has entered the input terminal 15 is frequency-divided by 1/2 by the 1/2 frequency divider 16, while being applied to the oscillator 17 as a reset pulse. Ru. Assuming that the input horizontal synchronization signal is indicated by a in FIG. 4, the output signal of the 1/2 frequency divider 16 has a 2H period, as indicated by b in the same figure, which is inverted every time a rising edge of the horizontal synchronization signal arrives. It becomes a nearly symmetrical square wave.

On the other hand, the oscillator 17 oscillates and outputs a pulse having the same repetition frequency as, for example, the horizontal transfer pulse, and when the rising edge of the horizontal synchronizing signal a is input to its reset terminal R, it is forced into a reset state, and its output signal For example, it is forced to a low level. The oscillator 17 generates and outputs pulses of a constant period again from this reset point. Therefore, the output signal of the oscillator 17 is always at a low level at all rising points of the horizontal synchronizing signal a, as shown by c in FIG. 4, and becomes a pulse train in phase synchronization with the horizontal synchronizing signal a. This pulse train c is supplied together with the output pulse b of the 1/2 frequency divider 16 to a two-input exclusive OR circuit 18, whereby a pulse train as shown by d in FIG. 4 is taken out.

As is clear from FIG. 4D, the above pulse train d has a waveform whose phase is inverted every 1H.
While the horizontal transfer pulse φ _H is output from the output terminal 19, it is also output from the output terminal 2 through the inverter 20.
1 and is output as a horizontal transfer pulse _H. Since the horizontal transfer pulses φ _H , _H have a phase inversion every 1H, they are in a frequency interleaving relationship with the horizontal scanning frequency f _H of the composite video signal, and therefore the horizontal transfer pulses φ _H , _H are delayed output composite video signals. Even if it leaks into the signal, the leaked frequency component becomes visually difficult to see on the playback screen. Therefore, as the low-pass filter 12, it is possible to use an inexpensive low-pass filter that has a broader band and a gentler slope than conventional filters.

Next, a second embodiment of the present invention will be described. Fifth
The figure shows a circuit system diagram of a second embodiment of the essential parts of the circuit of the present invention. In the figure, the same components as those in FIG. 3 are designated by the same reference numerals, and their explanations will be omitted. In FIG. 5, the output pulse train c of the oscillator 17 is a two-input AND
It is applied to one input terminal of each of the circuit 22 and the two-input NAND circuit 23, respectively. On the other hand, during the 1H period when the output pulse b of the 1/2 frequency divider 16 is at a high level, the output signal of the AND circuit 22 becomes the same pulse train as the output pulse train c of the oscillator 17, and
The output signal of the NAND circuit 23 is always at a low level. The next 1H when the above pulse b becomes low level
During the period, the output signal of the AND circuit 22 is always at a low level, and the output signal of the NAND circuit 23 is a pulse train having the opposite phase to the pulse train c.

The output signals of the AND circuit 22 and the NAND circuit 23 are logically summed by an OR circuit 24. Therefore, the output signal of the OR circuit 24 has the same repetition frequency as the pulse train c, as shown by d in FIG.
In addition, a pulse d whose phase is inverted every 1H is taken out and outputted to the output terminal 19 as a horizontal transfer pulse φ _H , while being outputted to the output terminal 21 as a horizontal transfer pulse _H through an inverter 20.

Application Example Note that the present invention is not limited to the above-described embodiments. For example, the oscillator 17 oscillates and outputs a signal with a frequency related to the horizontal transfer pulse frequency, and uses frequency division or frequency multiplication means to oscillate and output the signal. The configuration may be such that a required horizontal transfer pulse frequency is obtained, and the pulse d can also be generated using a microcomputer.

Effects As described above, according to the present invention, the phase of the horizontal transfer pulse is inverted every horizontal scanning period, so even if the horizontal transfer pulse leaks into the delayed output composite video signal, the horizontal transfer pulse component is in a frequency relationship that is interleaved with the horizontal scanning frequency in the playback screen, so it is less visually noticeable, and therefore the band of the low-pass filter for removing the horizontal transfer pulse frequency component can be made somewhat wider than before. This allows the above-mentioned low-pass filter to have a low-order filter circuit configuration with a gentler slope characteristic than the conventional one, so it can be constructed with a simpler circuit configuration and at a lower cost than the conventional one. It has certain characteristics.

[Brief explanation of drawings]

FIG. 1 is a block system diagram showing an example of a conventional circuit, FIG. 2 is a signal waveform diagram for explaining the operation of FIG. The circuit system diagram, FIG. 4, is a signal waveform diagram for explaining the operation of FIG. 1...Composite video signal input terminal, 2...Semiconductor delay circuit section, 3...Horizontal transfer register for input, 4...
...Vertical transfer gate for input, 5 ₁ to 5m... Vertical transfer register, 6... Vertical transfer gate for output, 7...
...Horizontal transfer register for output, 8...Horizontal synchronization signal separation circuit, 9, 26...Horizontal transfer pulse generation circuit, 15...Horizontal synchronization signal input terminal, 16...1/
2 frequency divider, 17... oscillator, 18... exclusive OR circuit, 19, 21... horizontal transfer pulse output terminal.

Claims (1)

[Scope of utility model registration request] An input horizontal transfer register to which an input composite video signal is supplied in series, a plurality of columns of vertical transfer registers to vertically transfer the output signal of the input horizontal transfer register, and after holding the parallel output signals of the vertical transfer register. An output horizontal transfer register that performs horizontal transfer and outputs delayed composite video signals in series, and a horizontal transfer register that generates and provides horizontal transfer pulses for horizontal transfer to both the input and output horizontal transfer registers, respectively. A transfer pulse generation circuit, a vertical transfer pulse generation circuit that generates and supplies a vertical transfer pulse for causing the vertical transfer register to perform vertical transfer, and a delayed composite video signal output in series from the output horizontal transfer register. In a video signal delay circuit comprising a filter circuit for removing unnecessary frequency components, the horizontal transfer pulse generation circuit oscillates and outputs a signal having a frequency related to the horizontal transfer pulse frequency, and also outputs a signal having a frequency related to the horizontal transfer pulse frequency. oscillation means that is forcibly reset by a synchronization signal;
A video signal delay circuit comprising circuit means for generating a phase-inverted signal every horizontal scanning period and outputting the signal as the horizontal transfer pulse.