JPH04113685A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04113685A JPH04113685A JP23291390A JP23291390A JPH04113685A JP H04113685 A JPH04113685 A JP H04113685A JP 23291390 A JP23291390 A JP 23291390A JP 23291390 A JP23291390 A JP 23291390A JP H04113685 A JPH04113685 A JP H04113685A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor layer
- mask
- stripe
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 21
- 230000007547 defect Effects 0.000 abstract description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 238000011109 contamination Methods 0.000 abstract description 3
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 18
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 14
- 238000000034 method Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- AXAZMDOAUQTMOW-UHFFFAOYSA-N dimethylzinc Chemical compound C[Zn]C AXAZMDOAUQTMOW-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910017401 Au—Ge Inorganic materials 0.000 description 1
- 101100002917 Caenorhabditis elegans ash-2 gene Proteins 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- WLQSSCFYCXIQDZ-UHFFFAOYSA-N arsanyl Chemical compound [AsH2] WLQSSCFYCXIQDZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 201000009310 astigmatism Diseases 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BLJHFCVPKWOHJX-UHFFFAOYSA-N ethylgallium Chemical compound CC[Ga] BLJHFCVPKWOHJX-UHFFFAOYSA-N 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体発光装置、特に、0゜6μm帯可視光
半導体レーザ装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor light emitting device, particularly a 0°6 μm band visible light semiconductor laser device.
上記0.6μm帯可視光半導体レーザ装置は、書込み密
度か波長の二乗に逆比例するため、光デイスク装置やレ
ーサプリンタ等の光情報処理装置の高性能化を実現する
デバイスとして期待されている。これらの用途における
半導体レーザ装置は、消費電力を低減するために低閾値
電流、高効率であることか必要であり、書込み、読取り
の特性を良好にするために低非点収差特性を有すること
が必要である。The above-mentioned 0.6 μm band visible light semiconductor laser device is expected to be a device that realizes higher performance of optical information processing devices such as optical disk devices and laser printers because the writing density is inversely proportional to the square of the wavelength. Semiconductor laser devices for these applications must have low threshold current and high efficiency to reduce power consumption, and must have low astigmatism characteristics to improve writing and reading characteristics. is necessary.
上記要求に答えるため、従来、横方向の屈折率差を大に
する構造として、基板上にメサストライプを形成してこ
の基板上に有機金属気相成長法(MOVPE法)て結晶
成長させて段差のある活性層を形成し、発光領域を段差
の先端部分にする半導体レーザ装置か提案されている。In order to meet the above requirements, conventional structures that increase the difference in refractive index in the lateral direction have been created by forming mesa stripes on a substrate and growing crystals on this substrate using metal organic vapor phase epitaxy (MOVPE). A semiconductor laser device has been proposed in which an active layer is formed and a light emitting region is formed at the tip of a step.
第2図は上記従来の半導体レーザ装置の製造工程図を示
す。同図(A)において、p形GaAs(ガリウム・ヒ
素)基板1に酸化シリコン等のストライプマスク2を形
成し、これをマスクにエツチングによってメサストライ
プ1aを形成する。FIG. 2 shows a manufacturing process diagram of the conventional semiconductor laser device. In the same figure (A), a stripe mask 2 of silicon oxide or the like is formed on a p-type GaAs (gallium arsenide) substrate 1, and mesa stripes 1a are formed by etching using this as a mask.
次に、同図(B)において、メサストライプ1aの両側
面にMOVPE法で電流狭窄用のn形GaAs層3を形
成し、ストライプマスク2を除去する。続いて、同図(
C)に示す如く、表面にMOVPE法でp形AlGa
InP (アルミニウム・ガリウム・インジウム・リン
)層4.Ga1nP(ガリウム・インジウム・リン)層
5. n形AlGa InP層6.n形GaAs層7
を成長する。Next, in FIG. 1B, n-type GaAs layers 3 for current confinement are formed on both sides of the mesa stripe 1a by MOVPE, and the stripe mask 2 is removed. Next, the same figure (
As shown in C), p-type AlGa is deposited on the surface using the MOVPE method.
InP (aluminum gallium indium phosphide) layer 4. Ga1nP (gallium indium phosphide) layer5. n-type AlGa InP layer6. n-type GaAs layer 7
grow.
上記従来の方法は、第2図(B)に示すn形GaAs層
3成長後の降温過程においてその表面か汚染され、この
表面に同図(C)に示すp形AIGaInP層4を成長
する時にn形GaAs層3の表面に欠陥か入り、これに
より、半導体レーザ装置として作動させた場合、電流狭
窄のためのn形GaAs層3をp形AlGa InPn
種層の逆接合界面において漏洩電流を生じ、閾値電流か
増大し、効率か低下する問題点かあった。In the above conventional method, the surface of the n-type GaAs layer 3 shown in FIG. 2(B) is contaminated during the cooling process after the growth, and when the p-type AIGaInP layer 4 shown in FIG. 2(C) is grown on this surface. When a defect occurs on the surface of the n-type GaAs layer 3 and the device is operated as a semiconductor laser device, the n-type GaAs layer 3 for current confinement becomes p-type AlGaInPn.
There were problems in that leakage current occurred at the reverse junction interface of the seed layer, increasing the threshold current and decreasing efficiency.
本発明は、電流狭窄のための半導体層とその表面の半導
体層との逆接合界面において漏洩電流を少なくし、閾値
電流を低減し、高効率を得ることかできる半導体装置の
製造方法を提供することを目的とする。The present invention provides a method for manufacturing a semiconductor device that can reduce leakage current at the reverse junction interface between a semiconductor layer for current confinement and a semiconductor layer on the surface thereof, reduce threshold current, and obtain high efficiency. The purpose is to
上記問題点は、一導電形の半導体基板上に珍成したスト
ライプマスクをマスクとして選択的なエツチングを行な
い、基板上にメサストライプを形成する工程と、メサス
トライプをマスクとして逆導電形の第1の半導体層、一
導電形の第2の半導体層、及び、第3の半導体層を、選
択的に半導体基板の表面から順に形成する工程と、スト
ライプマスク及び第3の半導体層を除去する工程と、メ
サストライプを含む基板上に、第4の半導体層、該第4
の半導体層よりも禁制帯幅の広い第5の半導体層とを順
に形成する工程とを含むことを特徴とする半導体装置の
製造方法によって解決される。The above problem is solved by the process of selectively etching a newly created stripe mask on a semiconductor substrate of one conductivity type to form a mesa stripe on the substrate, and the process of forming a mesa stripe on a semiconductor substrate of the opposite conductivity type using the mesa stripe as a mask. a step of selectively forming a semiconductor layer, a second semiconductor layer of one conductivity type, and a third semiconductor layer in order from the surface of the semiconductor substrate; and a step of removing the stripe mask and the third semiconductor layer. , a fourth semiconductor layer on a substrate including mesa stripes;
The present invention is solved by a method for manufacturing a semiconductor device, which includes a step of sequentially forming a fifth semiconductor layer having a wider forbidden band width than that of the semiconductor layer.
本発明では、メサストライプの両側面に第1回目成長で
第1〜第3の半導体層を積層し、第3の半導体層を除去
した後第2回目成長で第4.第5の半導体層を積層する
。第3の半導体層により、第2の半導体層の表面を降温
時における汚染から保護でき、又、第2の半導体層を形
成することによってその下地の第1の半導体層と共に予
め逆接合界面を作成してしまっているため、第2回目成
長によってこの逆接合界面に欠陥を生じることはない。In the present invention, the first to third semiconductor layers are stacked on both sides of a mesa stripe in the first growth, and after the third semiconductor layer is removed, the fourth semiconductor layer is deposited in the second growth. A fifth semiconductor layer is laminated. The third semiconductor layer can protect the surface of the second semiconductor layer from contamination when the temperature drops, and by forming the second semiconductor layer, a reverse junction interface is created in advance with the underlying first semiconductor layer. Therefore, the second growth will not cause defects at this reverse junction interface.
従って、第1.第2の半導体層でつくる電流狭窄のため
の逆接合界面における漏洩電流を低減でき、閾値電流を
低減てき、高効率を得ることかてきる。Therefore, the first. The leakage current at the reverse junction interface for current confinement created by the second semiconductor layer can be reduced, the threshold current can be reduced, and high efficiency can be obtained.
第1図は本発明の一実施例の製造工程図を示す。 FIG. 1 shows a manufacturing process diagram of an embodiment of the present invention.
同図(A)において、面方位(100)のp形GaAs
基板10にストライプマスク11を形成し、これをマス
クに硫酸と過酸化水素水との混合液を用いて化学エツチ
ングを行なってメサストライプ10aを形成する。次に
、成長温度690°CのMOVPE法を用い、SiH,
(モノシラン)のドーパント、TEG()リエチルガリ
ウム)、AsH,(アルシン)の原料ガスでn形GaA
s層(第1の半導体層)12を0.8μmの厚さに形成
し、その表面にDMZ (ジメチル亜鉛)のドーパント
、T E G 、A s H2の原料ガスてp形GaA
S層(第2の半導体層)13を0.2μmの厚さに形成
し、更にその表面にTEG、TMI (lリメチルイン
ジウム)、PH,(フォスヒン)の原料ガスてGa I
nP層14を0.2μmの厚さに形成する。以上の各工
程にて第1回目成長か終了し、降温する。In the same figure (A), p-type GaAs with plane orientation (100)
A stripe mask 11 is formed on the substrate 10, and using this mask as a mask, chemical etching is performed using a mixed solution of sulfuric acid and hydrogen peroxide to form mesa stripes 10a. Next, using the MOVPE method at a growth temperature of 690°C, SiH,
n-type GaA with (monosilane) dopant, TEG ()ethylgallium), AsH, (arsine) source gas
An s-layer (first semiconductor layer) 12 is formed to a thickness of 0.8 μm, and p-type GaA is coated on its surface with a dopant of DMZ (dimethylzinc), a source gas of TEG, and AsH2.
An S layer (second semiconductor layer) 13 is formed to a thickness of 0.2 μm, and Ga I is further formed on its surface using raw material gases such as TEG, TMI (l-lymethylindium), PH, and (phosphine).
The nP layer 14 is formed to a thickness of 0.2 μm. The first growth is completed through each of the above steps, and the temperature is lowered.
次に、ストライプマスク11をフッ酸で除去し、しかる
後Ga1nP層(第3の半導体層)14を塩酸で除去し
、同図(B)に示す形状とする。この場合、降温に際し
てGalnP層14表面か汚染されるか、これは除去し
てしまうので問題なく、これにより、p形GaAs層1
3の表面を汚染から保護できる。又、後の工程てこの表
面に第2回目成長を行なっていくか、p形GaAs層1
3を形成することによってその下地のn形GaAs層1
2と共に予めp−n逆接合界面を作成してしまっている
ので、この逆接合界面に欠陥を生じることはなく、n形
GaAs層3とp形AlGa1nP層4との逆接合界面
に欠陥を生じる第2図に示す従来例に比してこの逆接合
界面における漏洩電流を低減でき、閾値電流を低減でき
、高効率の半導体レーザ装置を得ることかできる。Next, the stripe mask 11 is removed with hydrofluoric acid, and then the Ga1nP layer (third semiconductor layer) 14 is removed with hydrochloric acid to obtain the shape shown in FIG. In this case, the surface of the GalnP layer 14 will be contaminated when the temperature is lowered, or this will be removed, so there is no problem.
3 surfaces can be protected from contamination. Also, whether a second growth is performed on the surface of the lever in a later step or the p-type GaAs layer 1
3, the underlying n-type GaAs layer 1
Since a p-n reverse junction interface is created in advance with 2, defects will not occur at this reverse junction interface, but defects will occur at the reverse junction interface between the n-type GaAs layer 3 and the p-type AlGa1nP layer 4. Compared to the conventional example shown in FIG. 2, the leakage current at this reverse junction interface can be reduced, the threshold current can be reduced, and a highly efficient semiconductor laser device can be obtained.
続いて、第1図(C)において、成長温度690°Cの
MOVPE法を用い、DMZのドーパント、PH,、T
EG、TMI、TMA (トリメチルアルミニウム)の
原料ガスてp形A]Ga1nP層(第5の半導体層)1
5を形成し、その表面にTEG、TMT、PH,の原料
ガスてGalnP層(第4の半導体層)16を形成し、
更にその表面にS iH4のドーパント、TEG、TM
I。Next, in FIG. 1(C), the DMZ dopant, PH, T
EG, TMI, TMA (trimethylaluminum) raw material gas p-type A] Ga1nP layer (fifth semiconductor layer) 1
5, and a GalnP layer (fourth semiconductor layer) 16 is formed on the surface using raw material gases of TEG, TMT, and PH,
Furthermore, SiH4 dopant, TEG, TM
I.
TMAの原料ガスてn形AlGa TnP層(第5の半
導体層)17を形成し、更にその表面にSiH4のドー
パント、T E G、 A s Hsの原料ガスでn形
GaAsJii18を形成する。この場合、p形A]G
aInP層15.n形AlGa InP層17はGal
nP層16よりも禁制帯幅か広いことか必要である。An n-type AlGaTnP layer (fifth semiconductor layer) 17 is formed using a TMA source gas, and an n-type GaAsJii 18 is further formed on its surface using a SiH4 dopant and TEG, As Hs source gases. In this case, p-type A]G
aInP layer 15. The n-type AlGa InP layer 17 is Gal
It is necessary that the forbidden band width be wider than that of the nP layer 16.
次に、p形GaAs基板10にAu−Zn(金・亜鉛)
層19及びAu層20を蒸着してp電極とし、n形Ga
As層18にAu−Ge (金・ケルマニウム)層21
を蒸着してn電極とし、共振器長300μmでへき関し
て完成する。Next, Au-Zn (gold/zinc) is applied to the p-type GaAs substrate 10.
A layer 19 and an Au layer 20 are evaporated to form a p-electrode, and an n-type Ga
Au-Ge (gold/kermanium) layer 21 on As layer 18
is vapor-deposited to form an n-electrode, and the resonator is separated at a cavity length of 300 μm to complete the process.
なお、n形GaAs層12はn形A]GaAs層てもよ
く、第1の半導体層の条件はA1.−、Ga、As (
0<x≦1)となる。又、Ga InP層14はAlG
alnP層でもよく、第3の半導体層の条件は(A I
+−8Ga、 ) o、s I no、s P(0
くX≦1)となる。又、GalnP層16はAlGa
InP層でもよく、第4の半導体層の条件は(A I
+−y Gay ) o、s I no、s P (
0<’1≦1)となる。又、p形AlGa InP層1
5及びp形AlGa InPIiil 7 (第5の半
導体層)の条件は(A I I−z Ga−) o、s
I no、s P O’<z<1)となる。Note that the n-type GaAs layer 12 may be an n-type A]GaAs layer, and the conditions of the first semiconductor layer are A1. -, Ga, As (
0<x≦1). Further, the Ga InP layer 14 is made of AlG
It may be an alnP layer, and the conditions for the third semiconductor layer are (A I
+-8Ga, ) o, s I no, s P(0
(X≦1). Further, the GalnP layer 16 is made of AlGa
It may be an InP layer, and the conditions for the fourth semiconductor layer are (A I
+-y Gay) o, s I no, s P (
0<'1≦1). Also, p-type AlGa InP layer 1
5 and p-type AlGa InPIiil 7 (fifth semiconductor layer) conditions are (A I I-z Ga-) o, s
I no, s P O'<z<1).
以上説明した如く、本発明によれば、メサストライプの
両側面に第1回目成長にて第1.第2゜第3の半導体層
を積層し、第3の半導体層を除去した後メサストライプ
上及び第1回目成長の積層構造上に第2回目成長にて第
4.第5の半導体層を積層しているのて、第1.第2の
半導体層でつくる電流狭窄のための逆接合界面か汚染さ
れて欠陥を生じることはなく、これにより、逆接合界面
における漏洩電流を低減でき、閾値電流を低減てき、
高効率を得ることかできる。As explained above, according to the present invention, the first growth is performed on both sides of the mesa stripe in the first growth. After laminating a 2nd third semiconductor layer and removing the third semiconductor layer, a 4th layer is grown on the mesa stripe and on the stacked structure of the first growth. Since the fifth semiconductor layer is laminated, the first. The reverse junction interface for current confinement created by the second semiconductor layer will not be contaminated and cause defects, thereby reducing leakage current at the reverse junction interface, reducing threshold current, and achieving high efficiency. I can do it.
第1図は本発明の一実施例の製造工程図、第2図は従来
の一例の製造工程図である。
図において、
10はp形GaAs基板(半導体基板)、10aはメサ
ストライプ、
11はストライプマスク、
12はn形GaAs層(第1の半導体層)、13はp形
GaAs層(第2の半導体層)、4はGa InP層(
第3の半導体層)、5はp形AlGa InP層(第5
の半導体層)6はGa InP層(第4の半導体層)、
7はn形AlGa InP層(第5の半導体層)8はn
形GaAs層
を示す。FIG. 1 is a manufacturing process diagram of an embodiment of the present invention, and FIG. 2 is a manufacturing process diagram of a conventional example. In the figure, 10 is a p-type GaAs substrate (semiconductor substrate), 10a is a mesa stripe, 11 is a stripe mask, 12 is an n-type GaAs layer (first semiconductor layer), and 13 is a p-type GaAs layer (second semiconductor layer). ), 4 is a Ga InP layer (
5 is a p-type AlGa InP layer (fifth semiconductor layer), 5 is a p-type AlGa InP layer (fifth
semiconductor layer) 6 is a Ga InP layer (fourth semiconductor layer),
7 is an n-type AlGa InP layer (fifth semiconductor layer) 8 is an n-type AlGa InP layer (fifth semiconductor layer)
Figure 3 shows a shaped GaAs layer.
Claims (1)
マスク(11)をマスクとして選択的なエッチングを行
ない、該基板(10)上にメサストライプ(10a)を
形成する工程と、 該ストライプマスク(11)をマスクとして、逆導電形
の第1の半導体層(12)、一導電形の第2の半導体層
(13)、及び、第3の半導体層(14)を、選択的に
上記半導体基板(10)の表面から順に形成する工程と
、 該ストライプマスク(11)及び該第3の半導体層(1
4)を除去する工程と、 該メサストライプ(10a)上を含む基板 (10)上に、第4の半導体層(16)、該第4の半導
体層(16)よりも禁制帯幅の広い第5の半導体層(1
5、17)とを順に形成する工程とを含むことを特徴と
する半導体装置の製造方法。[Claims] A step of selectively etching using a stripe mask (11) formed on a semiconductor substrate (10) of one conductivity type as a mask to form a mesa stripe (10a) on the substrate (10). Using the stripe mask (11) as a mask, a first semiconductor layer (12) of opposite conductivity type, a second semiconductor layer (13) of one conductivity type, and a third semiconductor layer (14) are formed. selectively forming the stripe mask (11) and the third semiconductor layer (10) in order from the surface of the semiconductor substrate (10);
4), and a fourth semiconductor layer (16), a fourth semiconductor layer (16) having a wider forbidden band width than the fourth semiconductor layer (16), is formed on the substrate (10) including the mesa stripe (10a). 5 semiconductor layers (1
5 and 17).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23291390A JPH04113685A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23291390A JPH04113685A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04113685A true JPH04113685A (en) | 1992-04-15 |
Family
ID=16946802
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23291390A Pending JPH04113685A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04113685A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5271028A (en) * | 1991-07-22 | 1993-12-14 | Sharp Kabushiki Kaisha | Semiconductor laser device |
-
1990
- 1990-09-03 JP JP23291390A patent/JPH04113685A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5271028A (en) * | 1991-07-22 | 1993-12-14 | Sharp Kabushiki Kaisha | Semiconductor laser device |
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