JPH04113590A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To operate surely and at high speed by providing an (n) channel transistor prescribing a charge up potential and a (p) channel transistor prescribing a charge up time at a charging part. CONSTITUTION:A bit line charging part 1 is provided with (n) channel MIS transistors T1 and T4 to be the transistor for a DC load and a (p) channel MIS transistor T5 to be the transistor for the short of a bit line pair, furthermore, (n) channel MIS transistors T21 and T31 and (p) channel MIS transistors T22 and T32 as the transistor for an AC load are arranged serially. And the charge up potential of a signal line pair 2 and 2' is prescribed by the (n) channel transistors T21 and T31, and the charge up time is prescribed by the (p) channel transistors T22 and T32 as well. Thus, the delay of a charge starting time from a reset signal starting time is reduced, the shortage of a charging time is eliminated, and the whole reset time is shortened.

Description

[Detailed description of the invention] [Summary of the invention] Regarding semiconductor storage devices.

The purpose is to shorten the reset time required to charge up a pair of signal lines that transmit complementary signals.

The charging portion of the signal line pair defines the charge-up potential n
A channel transistor and an n-channel transistor connected in series with the n-channel transistor and controlled by a clock signal to define a charge-up time.

[Industrial Application Field] The present invention relates to a semiconductor memory device used as a memory device for electronic computers, and in particular to static RAM. Many devices are now being used that are equipped with a reset circuit to increase speed.

[Prior Art] Referring to FIGS. 3 and 4, a conventional static RAM
I will explain about it.

FIG. 3 is a block diagram for explaining the overall configuration of the static RAM. The memory cell 3 is selected by the column decoder 5 by selecting the bit line pair 2, 2, which is a signal line pair.
' is performed by specifying each word line 11 by the row decoder 6.

That is, the memory cell 3 connected to the word line 11 corresponding to the row address ' is connected to a sense amplifier 7 and a write amplifier 8 via a transfer gate included in the column decoder 5 and data buses 9, 9'.

During reading, the signal line pair 2 connected to the memory cell 3
, 2' are detected by the sense amplifier 7. During writing, the write amplifier 8 lowers the potential of one of the bit line pairs 2 and 2' to the logic level "L".
Writing is performed by setting the logic level "H1" and the other one to "H1". When an address change occurs, the bit line pair whose potential has dropped on one side during reading and writing is restored to its initial potential. Charge-up to restore this initial potential is performed via a charging section (bit line charging section) 1.

Figure 4 shows the conventional static RAM shown in Figure 3.
Among them, bit line charging section 1. Bit line pair 2.2', each memory cell 3. Also, the internal circuit and connection status of the reset signal generator 4 are shown. Since each memory cell 3 has the same configuration, only one of its internal circuit configurations is shown. Furthermore, since the circuits of each bit line charging section 1 have exactly the same configuration, the reference numerals in the description will be added only to the leftmost one.

Each bit line pair 2.2' is connected to a voltage V by DC load transistors TI and T4 consisting of n-channel old S transistors.
It is constantly connected to the CC power supply and charged to a predetermined potential.

However, in order to rapidly charge up the bit line, which has once dropped, to a predetermined potential, the current driving ability of these DC load transistors TI and T4 is insufficient. Therefore, to increase the speed of the static RAM, AC load transistors T2. T3 is provided.

During the reset period, when the reset signal ΦR1ΦR is output from the reset signal generator 4, the bit line pair 2.2' is short-circuited to bring them to the same potential. The transistor T5 for shorting the bit line pair 2, 2' and the AC for temporarily assisting in charging up the bit line pair.
Load transistor T2. T3 are the reset signals Φ3. It is driven by Φ8 and becomes conductive.

FIG. 6 shows an example of how the bit line potential is charged during the reset period. In the figure, H of bit line pair 2.2'
The bit line BL is at the L level, and the bit line BL is at the L level, firstly conductive through the shorting transistor T5 to have the same potential, and secondly, the AC load transistor T2.
T3 starts conducting only when the gate voltage becomes a voltage value higher than the bit line potential by the value of the threshold voltage VT)IN, and remains active until the bit line potential becomes a value lower than the power supply voltage Vcc by the threshold voltage VTHN. do.

Static RAM to reduce reset time as much as possible
Due to the need to increase the speed of the AC and
Load transistor T2. For T3, an n-channel MIS transistor with large current drive capacity is used.

The reset signal Φ is generated by a large AC load transistor T2.
Since it is necessary to drive T3 all at once, the signal waveform as a pulse wave is distorted, resulting in distorted signals as shown in two examples as curves A and B in the conventional charge-up time explanatory diagram of Fig. 7. It becomes a waveform. Curve A shows the distorted waveform of the reset signal ΦR when the current drive capability of the transistors constituting the reset signal generator is small.
1 and 2 respectively show the distorted waveforms of the reset signal Φ when the current drive capability is large.

Each AC load transistor T2. T3 is the time (tl,
t2 ), conduction begins, a charging current is supplied to the bit line pair, and the primary gate voltage reaches this predetermined value vG.
The reset operation as an AC load is completed at the time (t+ +j5) when the value falls below.

[Problem to be solved by the invention] Generally, the characteristics of transistors change depending on the surrounding environment.
Further, since the driving ability of each transistor is different, the waveform of the reset signal Φ supplied by the reset signal generator 4 varies as described with reference to FIG. 7.

As shown by curve A in Figure 7, when the distortion of the reset signal ΦR increases, the conduction time of the AC load transistor (
t, Lt2J) becomes short, and there is a possibility that the potential of the signal line pair after yardage-up will not rise to the predetermined value (Vcc-VTHN) shown in FIG. 6 due to the lack of charging time.

In the above case, when the reset period ends and the memory cell is read, the potential difference between the pair of signal lines 2 and 2' cannot be secured, and the accuracy of the read in the sense amplifier 7 cannot be guaranteed. Therefore, in order to avoid this, it is necessary to add a margin to the predetermined charge-up time, and this margin lengthens the reset time, which poses a problem in that it imposes restrictions on speeding up the static RAM.

Furthermore, a transistor T5 for shorting the signal line pair 2, 2'
Because of the relationship between the potential of the signal line and the gate voltage, it is inevitable to use a p-channel transistor, and therefore, as shown in FIG. Inverted signal Φ
, must be received as a gate signal. Therefore, in the reset signal generator 4, the AC load transistors T2. It is necessary to create two types of reset signals Φ2゜Φ2, normal and reverse, together with the reset signal ΦR applied to the gate of T3, which not only complicates the configuration of the reset signal generator 4 but also increases the Another problem is that the area required for arranging different signal lines increases.

In view of the above-mentioned conventional problems, the present invention solves the problem that the waveform of the reset signal is distorted due to the characteristics of each transistor of the reset signal generator, environmental conditions, etc., resulting in insufficient time for charging up the pair of signal lines. The aim is to ensure that operation uncertainties arise due to this, and that the reset time margin to avoid this does not become a constraint on increasing the speed of the storage device, thereby enabling reliable operation and increased speed. The purpose is to provide a semiconductor memory device.

Furthermore, the present invention simplifies the configuration of the reset signal generator and the wiring for sending the reset signal to the charging part of each signal line pair, thereby reducing costs, even when a signal line pair shorting transistor is used together. The purpose is also to reduce constraints on placement.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method that is arranged for each pair of signal lines that transmit complementary signals, and that sets the pair of signal lines to a predetermined potential within a reset period defined by a clock signal. In the semiconductor memory device, the charging section includes an n-channel transistor that defines a charge-up potential, and is connected in series with the n-channel transistor, and is controlled by the clock signal to perform charge-up. and a p-channel transistor that defines time.

[Function] By defining the charge-up potential of the signal line pair by the n-channel transistor and by defining the charge-up time by the p-channel transistor, even if the waveform of the reset signal is distorted, this distortion will reduce the charge-up time. A predetermined signal line potential can be easily obtained for each reset period without causing any shortening.

Furthermore, when a p-channel transistor for shorting a pair of signal lines is used together, the reset signal supplied to the gate of the p-channel transistor for AC load can be shared with the p-channel transistor for shorting this pair of signal lines. .

[Embodiment] FIG. 1 shows a main configuration of a semiconductor memory device according to an embodiment of the present invention as a circuit diagram. In the figure, 1 is a charging part (bit line charging part) of a signal line pair, and 2.2' is a bit line pair constituting the signal line pair.

3 indicates each memory cell, and 4 indicates a reset signal generator.

In this embodiment, the bit line charging section 1 serves as a DC load transistor as in the circuit of a conventional semiconductor memory device.
channel MIS) transistor Tl.

T4. and a p-channel old S transistor T5 that serves as a short-circuit transistor for bit line pairs, and further includes an n-channel old S transistor T21 Ta2 and a p-channel MI as AC load transistors having the configuration of the present invention.
S) Transistor T22. A structure in which Ta2 is arranged in series is adopted. In addition.

This AC load p-channel transistor T22゜T
a2 and n-channel transistor T21. T 31
The connection itself can be configured as in the second embodiment shown in FIG. 2, and therefore either a p-channel transistor or an n-channel transistor can be placed on the power supply side.

In FIG. 1, the reset signal Φ3 output from the reset signal generator 4 is different from the conventional two types of reset signals Φ3. There is only one kind of reset signal Φ, unlike Φ, which was required, and this reset signal Φ is connected to the p-channel old S transistor T5. T22. added to each gate of Ta2.

When the reset signal Φ, goes to L level, the bit line pair shorting transistor T5 conducts the bit line pair 2.2', and at the same time, the AC load p-channel old S transistor T22. Ta2 starts conducting.

N-channel transistor T21°Ta2 for AC load
Vce is supplied as the gate voltage to AC
The potential of bit line pair 2.2' rises through conduction of load p-channel transistor T22°Ta2. Vcc
AC load n-channel transistor T21. from the power supply voltage value Vcc. Ta2 threshold voltage VTH
Vcc - V7H, which is the value subtracted by N.

By this time, the potential of bit line pair 2.2' has increased.

AC load n-channel transistor T21. Ta2
becomes non-conductive and the AC load ends. After this AC
Load p-channel transistor T22. T 3
The reset signal Φ3, which is the gate voltage of No. 2, also becomes H level, and the reset period ends.

The charging time for the AC load of the circuit of this embodiment will be explained with reference to FIG. 8 and in comparison with the charging time for the conventional AC load shown in FIG.

First, reset signal ΦR (curves A and B) in FIG.
AC load start time 1. from falling start time t0. ．． 1
The delays up to 2 are small compared to the corresponding delays in FIG.

Therefore, there is an advantage that the AC load starts early.

Furthermore, in FIG. 7, regarding the time when AC load actually starts, time t, J is when the waveform distortion of the reset signal Φ is small (curve B) and when the waveform distortion of the reset signal Φ2 is large (curve A). However, in FIG. 8, the corresponding difference between tl and t2 at the start of AC load is extremely small. On the other hand, regarding the time when the AC load ends in FIG.

Time t4 when the waveform distortion of reset signal Φ2 is small
and time t when the waveform distortion of the reset signal ΦR is large,
However, in FIG. 8, the corresponding difference between t4 and t5 is large.

Charging start time tl+ “2+ il +
Fall or rise time of the reset signal at t2 1. These differences occur in the respective delays from , and the variations in charging start time in each curve A, H.

In FIG. 7, the reset signal ΦR or the AC load n
However, in FIG. 8, the p-channel transistor T22. T 32
This is due to the fact that the reset signal Φ, which becomes the gate voltage of , only needs to drop slightly from Vcc to V.

Charge end time i4' + j5' + t
4 r t5 reset signal Φ7. ΦR end time (falling or rising start time) delay from t3 and each curve A
.

Charging end time during 8"4+t5t4
With regard to such a difference between the fluctuations of +t5' and the fluctuation of t5', in FIG.
In contrast, in FIG. 8, the conduction of the n-channel transistor ends at t5'.
This is caused by a large increase from the θ level of 2 to the predetermined voltage value vG.

As described above, in the bit line charging section of this embodiment, by defining the charge-up time through the n-channel transistor, AC
Compared to the conventional charging section that is loading, the reset signal generation time t is the charging start time t1+t2. Therefore, the delay from 1 to 3 is reduced, and therefore the reset time can be shortened.

In addition, if the distortion of the reset signal ΦR is large, the end time of conduction of the AC load p-channel transistor is delayed, which makes it easier to secure the required charging time. Compared to conventional circuits that require a margin for the reset time due to the risk of time reduction, there is no need to provide a margin for the reset time, so the reset time can be shortened.

Furthermore, a p-channel transistor T2 for AC load
2. Since T 32 and the shorting transistor 5 of the bit line pair 2, 2' are both n-channel transistors, only one type of reset signal is required compared to the conventional method which required two types of reset signals. Therefore, the configuration of the reset signal generator 4 becomes simple. This situation is the fifth
In Figures (a) and (b), logic circuit diagrams of both the embodiment and the conventional reset signal generator 4 are shown.

As shown in FIG. 5, both the conventional reset signal generator and the reset signal generator of this embodiment include an address transition detection circuit ATD having the same configuration.

The address transition detection circuit ATD consists of five NAND gates N
AND 1 to NAND 5 and two special gates GATE
I.

It is composed of GATE 2. In the conventional reset signal generator, two types of reset signals ΦR1ΦR are required, so three inverters INV 1' to INV 3' including two inverters with large current driving capability are installed following the address transition detection circuit ATD. However, in this embodiment, only one type of reset signal ΦR is required, and one inverter INV1 with a large current driving capacity is sufficient.

In the reset signal generator of the above embodiment.

When the address transition detection circuit ATD detects a change in the column address or row address, it generates a constant width pulse Φ and outputs it to the inverter INV1.
NV1 outputs a reset signal Φ2, and this reset signal ΦR causes each n-channel transistor T22. Ta
2. By temporarily turning on T5, the bit line pair is short-circuited and AC loaded in response to an address change.

It is also possible to define the charge-up potential by simply using an n-channel transistor that defines the charge time, instead of adopting a configuration in which the charge-up potential is determined by an n-channel transistor as in the configuration of the present invention. This will cause some inconvenience.

That is, the AC load p-channel transistor T2
2. When the signal line potential is defined by Ta2.

According to the characteristics of the n-channel transistor, the signal line potential is V
The voltage will rise to a high voltage value that is almost the same potential as the cc power supply, but it is included in the column decoder 5 in Fig. 3.
The power supply configuration for the gate voltage applied to the transfer gate (shown as an example circuit in Figure 9), which is configured as a channel MIS l-transistor and is a bidirectional gate that connects this high voltage signal line and the data bus, has become complicated. This is an inconvenience.

Furthermore, in order to eliminate this inconvenience, configuring the transfer gate in FIG. 9 as a p-channel transistor instead of an n-channel transistor means that the n-channel transistor constituting each memory cell and the p-channel transistor as the transfer gate This is difficult to adopt considering the increase in occupied area caused by mixing with transistors.

In the above embodiments, a shorting transistor is provided and a bit line charging section is shown in which a DC load is used. However, the signal line pair in the present invention is not limited to a bit line pair, but may be a data bus, for example. Further, the shorting transistor and the DC load themselves are not essential requirements in the configuration of the charging section of the present invention, and it is possible to omit them.

[Effects of the Invention] As explained above, according to the configuration of the present invention, the delay in the charging start time from the reset signal start time is reduced, and the difference in current drive ability based on the difference (variation) in transistor characteristics and the environment are further reduced. There is no shortage of charging time due to changes, so the overall reset time can be shortened, and the speed of the semiconductor memory device can be increased.

Furthermore, in the case of a semiconductor memory device that also uses a p-channel transistor for shorting a pair of signal lines, only one type of reset signal can be used.

The configuration of the reset signal generator has been simplified.

The wiring for this can also be simplified.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention. FIG. 2 is a circuit diagram of a second embodiment of the present invention. FIG. 3 is a block diagram for explaining the overall configuration of the present invention and a conventional semiconductor memory device. FIG. 4 is a circuit diagram of a main part of a conventional semiconductor memory device. FIG. 5 is a circuit diagram showing the configuration of a reset signal generator, in which (a) is a conventional circuit diagram and (b) is a circuit diagram of an embodiment. FIG. 6 is an explanatory diagram of conventional AC loading of a bit line pair. FIG. 7 is an explanatory diagram of conventional charging time. FIG. 8 is an explanatory diagram of charging time in the embodiment. FIG. 9 is an explanatory diagram of a transfer gate circuit. It is. In FIG. 1, 1 is a charging section (bit line charging section); 2.
2' is a signal line pair, 3 is a memory cell, 4 is a reset signal generator, T21. Ta2 is an n-channel transistor for AC load, T22. Ta2 is a p-channel transistor for AC loading, and T5 is a p-channel transistor for shorting. , ATD Figure 5 Time 與茄J,! IC+) circuit cause Figure 1〆4 m d

Claims (2)

[Claims] (1) Arranged for each signal line pair (2, 2') that transmits complementary signals, and charges up the signal line pair (2, 2') to a predetermined potential within a reset period defined by a clock signal. In a semiconductor memory device including a charging section (1), the charging section (1) has a voltage n that defines a charge-up potential.
channel transistors (T21, T31), and p-channel transistors (T22, T22, T31) connected in series with the n-channel transistors (T21, T31) and controlled by the clock signal to define the charge-up time.
T32). (2) The charging section (1) according to claim 1 further includes a signal line pair (2).
, 2') p-channel transistor for shorting (T5)
A semiconductor memory device comprising: