JPH04113584A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To contrive a reduction of power consumption or to improve an access speed by generating the selection state, 1st non-selection state and 2nd non- selection state with a combination of logical levels of plural chip enable input signals. CONSTITUTION:The internal chip enable signal -CE' transmitted to an address buffer circuit 105 and the internal chip enable signal -CE'' transmitted to periph eral circuit parts other than the address buffer circuit 105 (e.g., a sense amplifier 106 and an input/output control circuit 107) are separately formed by a chip enable control signal -CE'. In this static RAM, three states are generated by the combination of internal chip enable signals -CE' and -CE''. In this case, the 1st non-selection state inactivating all peripheral control circuits 105-107, the 2nd non-selection state inactivating the peripheral control circuits 106, 107 other than the address buffer circuit 105, and the selection state activating all peripheral control circuits 105-107, are selectively generated. By this proce dure, the reduction of power consumption or improvement of access speed are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of chip enable input terminals.

[Prior Art] As shown in FIG. 2, a conventional semiconductor memory device of this type includes a memory cell array 201, a column decoder 202 and a row decoder 203 for selecting cells in the memory cell array 201. chip enable signal CEI
, CE2 supplied chip enable control circuit 204
and its output signal] 2, an address buffer circuit 205, a sense amplifier 206, and an input/output control circuit 2 controlled by
07. When the chip enable signal CE' is at a low level and the chip enable signal CE2 is at a high level, the semiconductor memory device is in a selected state.

On the other hand, if the chip enable signal -C-1 is at a high level or the chip enable signal CE2 is at a low level, the semiconductor memory device is in a non-selected state and cuts off the through current flowing to the peripheral control circuit section when selected.

FIG. 3 shows a chip enable control circuit 204, in which an internal chip enable signal 2' is transmitted to each peripheral control circuit. For example, the address buffer circuit 2 shown in FIG.
05, the internal chip enable signal ■1 is input to the first stage N.
It is transmitted as a single signal of OR circuit 205a. Therefore, the internal signal CE' becomes high level on the non-selected path, and the input first stage N
The through current of the OR circuit 205a is completely cut off, and the internal address signal light is fixed at a low level. Similarly, the sense amplifier 206 is also configured to become inactive when the internal signal T' becomes high level, thereby cutting off the through current. Further, the input/output control circuit 207 forcibly sets the input/output terminal I10 to a floating state when the internal signal CE' becomes high level.

[Problems to be Solved by the Invention] In the above-described conventional semiconductor memory device, even if the chip enable signal CEgo is set to a high level to bring it into a non-selected state, the chip enable signal CE2 is set to a low level to set it to a non-selected state. Even in the case of a non-selected state, the address buffer circuit is inactivated and the internal address signal lamp is fixed at a low level. Therefore, when restarting the read operation, a new address signal is required, and the internal address signal is formed after the internal chip enable signal is generated. As a result, when comparing the address access time and the CE go access time or the CE2 access time, there is a problem that the address access time is necessarily delayed by the delay time of the chip enable control circuit 204, and the data bit read speed is reduced.

[Means for Solving the Problem] The gist of the present invention is to provide a memory cell array that holds data bits, and a plurality of peripheral controls that include an address buffer circuit and enable operations of external devices on the data bits held in the memory cell array. and a chip enable control circuit that supplies an internal chip enable signal to a peripheral control circuit according to a combination of logic levels of a plurality of chip enable signals, wherein the chip enable control circuit is supplied to an address buffer circuit. a first non-selection state in which a first internal chip enable signal to be supplied to the address buffer circuit and a second internal chip enable signal to be supplied to peripheral control circuits other than the address buffer circuit are generated independently of each other, and all peripheral control circuits are inactivated; and a second non-selected state in which peripheral control circuits other than the address buffer circuit are inactivated, and a selected state in which all peripheral control circuits are activated.

[Operation of the Invention] When the semiconductor memory device according to the above structure enters the first non-selected state, all peripheral control circuits are deactivated, thereby preventing through current and the like.

On the other hand, when entering the second non-selected state, the address buffer circuit changes the internal address signal based on the address signal supplied from the outside, so when it enters the selected state, data can be immediately transferred.

[Example code] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a static random access memory (hereinafter referred to as static RAM) as an embodiment of the present invention. The difference between the configuration of the static RAM shown in FIG. For example, the internal chip enable signal -7C''Eyy that is transmitted to the sense amplifier 106 and the input/output control circuit 107) is formed separately.In this static RAM, the internal chip enable signal CE' and Three states occur depending on the combination of "CE".

The first state is the internal chip enable signal
This occurs when both E'' are at low level, and at this time all peripheral control circuits 105, 106 and 107 are in the activated state in the normal selection state.The second state is when the internal chip enable signal r
■' is low level, the internal chip enable signal E t
This occurs when t is at a high level, and at this time, the peripheral control circuits 106 and 107 other than the address buffer circuit 105 are inactivated, and the I10 terminal is also floating.
Externally, it is in a non-selected state. The address buffer circuit 105 operates normally according to the external address input Ai, and depending on the input voltage of the external address input A1,
Through current and A of the input first stage NOR circuit (see Figure 4)
When i changes, a corresponding charging/discharging current flows. However, since the internal address signal λ7 always changes according to Ai, the column decoder 1022 and the row decoder 1
03 also selects the specified address. This results in
There is no access time delay when EIT goes low again. The third state occurs when the internal chip enable signals CE' and C' are both at high level,
At this time, all the peripheral control circuits 105 to 107 are inactive, and the through current of the - cut is cut off.

A first example of the chip enable control circuit 104 that controls the internal chip enable signals ■' and rπ'' is the circuit shown in FIG. 5.Table 1 shows the circuit 10 shown in FIG.
4 is a correspondence table of input and output signals in four operations. In this circuit, when the chip enable signal CE2 is at a low level, a first non-selection state is entered in which all through currents are cut off, and the internal chip enable signal T1. When both CE2 are at a high level, a second non-selection state occurs in which the access time after changing from non-selection to selection is fast.

FIG. 6 shows a second example of the chip enable circuit 104 in the present invention. Table 2 is an input/output correspondence table for the chip enable control circuit shown in FIG. 6. When the chip enable signal -fll is at a high level and the chip enable signal CE2 is at a low level, the first non-selected state chip enable is set. Signals T1 and CE2 are both high level, or
When both are at low level, the second non-selected state is reached.

Table 1 Table 2 LO: Low level, Hl: High level [Effects of the Invention] As explained above, in the semiconductor memory device of the present invention, the selection state and the It is possible to generate a first non-selected state and a second non-selected state, and when it is important to reduce current consumption when non-selected, the first non-selected state is used and the access speed after changing from non-selected to selected is If you place importance on this, you can set a second non-selected state. Therefore, it is possible to reduce power consumption or improve access speed depending on usage conditions.

[Brief explanation of the drawing]

FIG. 1 shows a static RAM according to a first embodiment of the present invention.
2 is a block diagram of a conventional example, and FIG. 3 is a circuit diagram of a conventional chip enable control circuit.
Figure 4 is a circuit diagram of the address buffer circuit, and Figure 5 is the circuit diagram of the address buffer circuit.
Circuit diagram showing the chip enable control circuit of the embodiment, No. 6
FIG. 3 is a circuit diagram showing another example of the chip enable circuit. 101 ・ 102 ・ 103 ・ 104 ・ 105 ・ 106 ・ 107 ψ

Claims (1)

[Claims] A memory cell array that holds data bits, a plurality of peripheral control circuits that include an address buffer circuit and enable operation of external devices on the data bits held in the memory cell array, and a plurality of chip enable signals according to a combination of logic levels. In a semiconductor memory device that includes a chip enable control circuit that supplies an internal chip enable signal to a peripheral control circuit, the chip enable control circuit supplies a first internal chip enable signal that is supplied to an address buffer circuit, and a chip enable control circuit that supplies an internal chip enable signal to a peripheral control circuit. A second internal chip enable signal supplied to the control circuit is generated independently of each other, and a first non-selection state in which all peripheral control circuits are inactivated and peripheral control circuits other than the address buffer circuit are inactivated. A semiconductor memory device characterized in that a second non-selected state and a selected state in which all peripheral control circuits are activated are selectively generated.