JPH04113563A - Digital signal recording method - Google Patents

Abstract

PURPOSE:To sharply reduce the decision error of video data and audio data caused by regenerative error and to improve an error rate as a whole by selecting a synchronizing pattern corresponding to a data word when inserting the synchronizing pattern showing the head of a recording block to the recording block. CONSTITUTION:When inserting the synchronizing pattern I showing the head of the recording block composed of plural information symbols to this recording block, the synchronizing pattern is selected corresponding to the data word. Namely, the synchronizing pattern to the video data is made different from the synchronizing pattern to the audio data, and the two kinds of synchronizing patterns are discriminated by using both the identification of the two kinds of synchronizing patterns and a conventional identification code or utilizing that the number of bits in the synchronizing pattern is more than that of the identification code and that the probability for the synchronizing pattern for video to be completely erroneously recognized as the synchronizing pattern for audio is extremely low. Thus, the video data and the audio data can be correctly identified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal recording method suitable for use in high-density recording of digital signals in digital VTRs and the like.

BACKGROUND OF THE INVENTION Digital VTRs (hereinafter referred to as DVTRs) currently available on the market are for broadcasting purposes only, and record in a block format as shown in FIG. In other words, a synchronization pattern indicating the beginning of the block and an ID indicating information regarding the recorded data of the block.
This is the recorded data. During playback, this synchronization pattern is detected to identify the beginning of the block, and then the ID and data are restored.

In broadcast DVTRs currently available on the market, the synchronization pattern for video data and the synchronization pattern for audio data are the same. Video data and audio data are recorded with a special identification code added thereto as part of the ID shown in FIG. 2, which allows each recording block containing the respective data to be mutually identified. On the other hand, during playback, this identification code is used to identify whether the playback data is video or audio, and subsequent processing is switched according to this result.

Problems to be Solved by the Invention As shown above, in a DVTR, the processing of video data and audio data during reproduction is changed depending on the identification code within the recording block. Therefore, if this identification code is incorrect during playback, video data will be processed as audio data, or conversely, audio data will be processed as video data. This is a typical example of a very small error resulting in a large error, and is a big problem in practice.

Since currently commercially available DVTRs are for expensive broadcasting use, we have devoted a wealth of circuitry to sufficiently prevent errors in identification codes to solve this problem. DVTRs cannot be equipped with large-scale error countermeasure circuits like those used for broadcasting due to the selling price. Therefore, it is important to find a method that can greatly reduce such errors with relative ease.
This is a major issue in realizing a VTR.

Means for Solving the Problem The purpose of the present invention is to provide a new method as described below in order to solve this problem.

A digital signal recording method that selects the synchronization pattern according to the data word when inserting a synchronization pattern indicating the beginning of the recording block constituted by a plurality of information symbols.

Operation The present invention separates the synchronization pattern for video data and the synchronization pattern for audio data, and uses the identification of two types of synchronization patterns together with a conventional identification code, or the synchronization pattern has a larger number of bits than the identification code, and Video and audio can be correctly identified simply by distinguishing between the two types of synchronization patterns, taking advantage of the fact that there is a very low probability that a synchronization pattern for video will be completely mistaken for a synchronization pattern for audio.

Embodiment In this embodiment, an 8/12 code suitable for high-density recording will be explained as an example. The 8/12 code converts an 8-bit data word into a 12-bit code word, and connects the converted 12-bit code words to each other according to established rules. This code limits the number of consecutive bits to a minimum of 2 (=d) and a maximum of 10 (=k). The 8/I2 code will be explained in detail below.

For convenience of explanation, in order to classify the code words used in the 8/12 code, parameters representing the characteristics of the code words as shown in FIG. 3 are determined. In other words, L block: Starting end of a code word where 1 bit of the same binary value TB continues R block: End of a code word where r bits of the same binary value LB continue B block: b (=12-1-r) Codewords used in the intermediate 8/12 code of bit codewords are limited to those that satisfy the following conditions.

11) 1≦1≦9 1≦r≦9 (n) In the B block, completely satisfying the restriction d, () means that in the B block, 0 and 1 of 2 bits or more and 10 bits or less continue alternately. (excluding b=0). Furthermore, the following parameters F and E are introduced regarding 1 and r.

F=0 (1=1) F=1 (2≦l≦5) F=2 (6≦1≦9) E=O (r≦1).

E=1 (2≦r≦5) E=2 (6≦r≦9) The four parameters thus determined (TB, F,
E.

The connection between code words is controlled based on LB).
This control means that regarding the connection between the first codeword-1 and the second codeword-2 shown in FIG.
, meaning that the limit is satisfied. Hereinafter, the rules regarding the connection between code words will be referred to as a connection part.

Table 1 shows the four parameters (TB, F, E.

LB) shows the code word combination rules according to the present invention, which are defined based on LB.

(Hereafter the margin) (Hereafter the margin) Table 1 In Table 1, CW-No is the combination number of code words and the identification number of the code words that make up the combination. matches identical data words.

TB, F, E, and LB in Table 1 are parameters related to code words, and the example shows an example of a code word that can be represented by the parameters. Next, the code word combination rules in Table 1 will be explained in detail. In addition, code word A
A code word in which all 1's in 0.0 are replaced with 1's is called a back pattern of code word A, and is expressed as A''.

(1) F≠1. E≠1. TB=1. Code word t of LB=1
'W (F, E, 1) is its back pattern CW (F.

The values of F, E, TB are equal to E, 1)' and discharge (F, E, 1), and the code word CW (F, E, O) with LB=0 and its back pattern C11 (F, E, 0)”.

(c++-Nα=1.4.13) (2) F≠1. E≠1. The code word CW(F, 1
゜X) is combined with the pattern CW(F, 1.X)' on its back. Note that X represents both O and 1.

(Cga-Nα-2, 3, 14, 15) (3) F=1. E≠1. TB=1. Code word c for LB=1
h(1,E,1) is CW(1,E,1) and F.

The values of E and TB are equal, and the code word CW (1°E
, 0).

(Open - Open = 5. 6.11.12) (4) F = 1. Codeword CW(1,l,X) of E=1
and its back pattern CW (1, l, X)'' are not combined with other code words and are made to correspond to the data word alone.

(CW-floor = 7.8, 9.10) Due to the combinations of code words (1) to (4) mentioned above, as shown in Table 2, even when code words are connected, d, limits can be met.

(Left below) Codewords obtained by combining only the codewords that satisfy the conditions (1) and (II) above among the 12-bit codewords according to (1) to (4). The number of sets is 264, as shown in Tables 3.1 to 3.7. Note that DP in Tables 3.1 to 3.7 represents the absolute value of the difference between the number of 1's and 0's in a code word (referred to as disparity).

(Margins below) Table 3.1 (Margins below) Table 3.3 (Margins below) Table 3.2 (Margins below) Table 3.4 (Margins below) Table 3.5 Table 3.6 (Hereinafter referred to as margin) (hereinafter referred to as margin) Table 3.7 Since the number of 8-bit data words is 256, d=2 in the present invention. A 12-bit RLL code that satisfies =10 can convert all 8-bit data words. By the way, in normal digital recording, a format is used in which a plurality of pieces of data are treated as one block, and a synchronization pattern for block synchronization is added to each block. As this synchronization pattern, a special pattern that never appears in normal data is selected.

In the present invention, codewords that correspond to data words are limited to codewords with a leaf of 6 or less in Tables 3.1 to 3.6 (
256 words), and as a synchronization pattern, a pattern in which two identical code words (F=1.E=1) with OP of 8 are arranged in series is used (for example, code word 256 in Table 3.7). As shown in FIG. 5, any consecutive 12 bits (B12) of this 24-bit synchronization pattern always include the bit (bz: 1=1-B) that constitutes the code word with the DP of 8. Therefore, the DP of B12 is also 8.

On the other hand, the 24 bits include at least one 12-bit code word. Therefore, for any 24 bits of the bit example generated by connecting code words whose DP corresponding to the data word is 6 or less, the DP of the 12 bits therein is 6 or less.
Be sure to include the following parts. For these reasons, this synchronization pattern never appears in the bit examples obtained by connecting code words corresponding to data words.

As just shown, by determining the code word that corresponds to the data word and the code word used for the synchronization pattern, d=2. ni=
10, correct block synchronization can be guaranteed. Similarly, as a synchronization pattern, a codeword with a DP of -8 (F
=1. A pattern in which two words (E=1) are arranged in series is also used (for example, code word 256 in Table 3.7). In other words, 8
The /12 code has at least two words that are suitable for synchronization patterns that never appear in the data.

Here, the following two types of synchronization patterns are selected.

For video: 11111001111111111
0011111 For audio: 0000011000
00000001100000 These are complementary to each other, and a 24-bit error is required for the video and audio synchronization patterns to be completely incorrect. However, since the reproduced bit error rate in the normal state is less than IXl0-', or at worst less than IXl0-2, such probability can be completely ignored.

Next, means for realizing the present invention will be explained using FIG. 1. In FIG. 1, a holding circuit 1 sequentially holds 8-bit data words sent periodically. Holding circuit 1
The outputs are input to the codeword generation circuit 2 and the codeword generation circuit 3. In code word generation circuit 2, E in Table 3
= 1 “code word ゛ and E≠10゛′ code word 1”, their code word glue, parameter F regarding R block,
Generate E.

Here, the code word appearing in the output of the code word generation circuit 2 is C
Let's say W. On the other hand, the code word generation circuit 3 generates "° code word 2" in Table 3 where E≠1.

Here, the code word appearing in the output of the code word generation circuit 3 is C
Let's say W. Note that in Table 3, the digits correspond to the data words appearing at the output of the holding circuit 1. For example, if the value of the data word is 154, then N in Table 3.

154 codewords 100011100111 appear in the codeword generation circuit 2.

The holding circuit 4 receives the output of the code word generation circuit 2, the holding circuit 5 receives the output of the code word generation circuit 3, and the holding circuit 6 receives the parameter E regarding the R block of the immediately preceding code word CW(, -1, 3). , and hold the LBO value. Note that the value of LB may be the value of the last bit of the code word CW+s-1,a.

Further, the inversion control signal generation circuit 7 generates a value Y that controls whether or not the code word C-1 is made into a back pattern according to Table 2 (Y=1: back pattern).

In two cases, TB, F, L regarding the code word ch.
Let the values of B and E be TB,, F,, LBi, respectively.
, Ei.

Also, the immediately preceding code word” (TB regarding i-11m,
The values of F, LB and E are respectively TBi-1+F
Let i-1+LBi-1+E,-. At this time, the inversion information regarding the immediately preceding code word CW(i-1)a is set to Yl-1
Then, the inversion information Y regarding the code word C-8° becomes 1 when the following three conditions are satisfied.

(Y, 1) LBX,, = O, F = 0 (Y, 2) L
BX=-+=0, E i-1=O5 and F
, -2(Y,3)LBX4-+ = 1, E i
-1≠0, and F, = true, LBXi-, is l,
It is obtained by exclusive OR of Bi-, and Y,-3.

On the other hand, the selection signal generation circuit 8 generates a selection signal S, and by switching the switch 9 using the selection signal S, either the code word from the code word generation circuit 2 or the code word from the code word generation circuit 3 is selected. Select. This selection signal S becomes 1 only when the following condition is satisfied, and selects the code word from the code word generation circuit 3.

(S, 1) E =-+ = 0, LBX4-+
≠TB1 and F, -1 (5, 2) E=-+= 2
, LBXH-+=TB, F, -1 condition (Y,
1) to (Y, 3) and (5, 1) As can be seen from (5, 2), both the inversion control signal generation circuit 7 and the selection signal generation circuit 8 can be realized by simple logic circuits. Next, parallel/serial converter 10 converts the 12-bit parallel code word appearing at the output of switch 9 into serial data. The EXOR gate 11 inverts the serial code word or sends it out without inverting, depending on the output of the parallel/serial converter 10 and the inversion control signal Y from the inversion control signal generation circuit 7.

Holding circuits 12 and 13 are parallel/serial conversion circuits 0
It is used for the time adjustment of the code word output from the code word and the inverted control signal for this code word. On the other hand, the synchronization pattern generation circuit 14 generates a two-word (24-bit) synchronization pattern 111110 in the video section based on the AV switching signal.
011111111110011111 and F-1゜E=
1, and a two-word synchronization pattern 0 in the audio section.
00001100000000001100000 and F
=l, generate E-1.

These generated signals send the synchronization pattern to the switch 16 in accordance with the synchronization pattern interval signal from the counter 15.
F is sent to switch 17, and E is sent to switch 18. The switches 16, 17, and 18 select and output each signal from the synchronization pattern generation circuit 14 only while the synchronization pattern section signal from the counter 15 is ON. As a result, regarding the synchronization pattern, F=1. It is processed in exactly the same way as the E=1 codeword, and the synchronization pattern is not reversed and no restriction violation occurs in d before or after the synchronization pattern.

As shown above, an 8-bit code word is converted into a 12-bit data word using the circuit configuration shown in FIG.
In the 8/12 code, which limits the number of consecutive bits of the same binary value in the focus string created by connecting two focus data words to between 2 and 10, video and audio signals that never appear in the data are used. Two types of synchronization patterns can be generated.

On the other hand, identification of video and audio synchronization patterns can be easily realized using two types of matching circuits shown in FIG.

That is, the synchronization pattern 1111 for incoming data and video
10011111111110011111, and a matching detection circuit 19 that checks whether the incoming data matches the audio synchronization pattern 0000011000000000011.
This is a match detection circuit 20 that checks for a match with 00000.

- The number output circuit 19 generates a matching signal and an AV identification signal (=0) indicating that it is a video, and - the number output circuit 20
Then, a matching signal and an AV identification signal (=1) indicating that it is audio are generated. As a result, the synchronization pattern detection signal and the AV identification signal can be obtained simultaneously. Thereafter, for example, it can be used in conjunction with conventional identification codes to further reduce the probability of misidentification between video and audio.

Next, a decoding circuit that decodes an 8-bit data word from a 12-bit code word based on the synchronization pattern detection signal detected in FIG. 6 will be described. The code word extraction signal generation circuit 22 generates a signal indicating the word boundary of the code word from the reproduced bit string based on the synchronization pattern detection signal.

The code word extraction circuit 23 extracts a code word in units of 12 bits from the reproduced bit string based on the output of the code word extraction signal generation circuit 22.

Thereafter, the 12-pinto code word is decoded into an 8-bit data word. In the conventional decoding method, the 12 bits to be decoded are directly decoded into 8 pinto data words. Assuming that this decoding is performed in a ROM (Read Only Memory), the necessary steps for the ROM are 2 I2X 8 =
It is 32 kilobits. On the other hand, the capacity of the ROM required for the decoding circuit used in the present invention is 4 kP at most.

The 8/12 code decoding method will be described below, and then the decoding circuit will be described.

The decoding method for the 8/12 code is characterized by the following two points.

(1) All leading bits of the code word to be decoded are set to 1.

(2) Instead of decoding the code word itself, decoding is performed using a bit pattern identification code obtained by dividing the code word.

Next, we will show that correct decoding can be achieved using a decoding method with these characteristics.

As shown above, regarding the code word of the present invention with F≠1, the code word W2 starting with 1 and the back pattern darkness' of the code word W2 are
The same data words are associated with each other.

Therefore, if it is known that F≠1 of the codeword to be decoded, whether this codeword is a codeword starting with 1 -2,
Alternatively, there is no need to distinguish and decode whether it is the back pattern -2'' of code word W2. Therefore, for code words with F≠1, the same identification code should correspond to code word W2 and the ridge. That's fine.

On the other hand, for the code word with F=1, the first bit TB is 1
The code word W2 and the back pattern -2' of the code word -2 whose TB is 0 are made to correspond to different data words. Therefore, the data story corresponding to the code word W2 and the code word -
If the data word D' corresponding to 2' is arbitrarily selected, it is necessary to output an identification code that can distinguish the code word -2 and the code word D' from each other.

However, the data word corresponding to the code word and the data word D' corresponding to the code word -2' are complementary, that is, all l's of the data word are inverted to O's, and all O's are inverted to 1's. If the obtained data word is D', the identification code for code word 2 can be made equal to the identification code for code word -2'.

This is because the identification code between code words is 10,
Identification code ID! Let D be the data word output for the two.

At this time, since the identification code for code word W2' is also ID, the data word output is also D. Here, the code word W
If it is detected that F=1 of 2'' and TB=0, all 1's in the data story of the decoder output are inverted to O's, and all 0's are inverted to 1's. ,
A data word D° corresponding to the final code word −2′ is obtained.

A decoding circuit configured based on the decoding method described above will be explained using FIG. 7. In FIG. 7, 12 exclusive OR (EXOR) gates 23 and 12 negation (
NOT) Gate 24 is for converting a 12-bit code word to be decoded into a code word that always starts with 1.

- As an example, 10011100 as the code word to be decoded
Assume 1100. The first bit I-TB of this code word is an digit, and the EXOR gate 23 works as a negation, so
The output of NOT gate 24 becomes 100111001100.

Conversely, if we assume 011000110011 as the codeword to be decoded, since TB of this codeword is 0, EXO
The input appears as is at the output of the R gate 23. Therefore, the output of NOT gate 24 is 100111001
100 is obtained. The temporary decoding circuit 25 in FIG.
An identification code is generated for the upper 6 bits of the code word that always starts with 1 and is obtained at the output of the NOT gate 24. Third
As can be seen from the table, there are 13 different upper 6 bits of the code word starting with 1 as shown in Table 4.

Therefore, the identification code (ID) for the top 6 bints
can be expressed in 4 bits. Furthermore, the temporary decoding circuit 25 also outputs an inverted control signal Y that becomes 1 only when F=1 and TB=O of the code word to be decoded. Note that the inversion control signal Y
can be realized using a simple logic circuit. Further, the temporary decoding circuit 26 in FIG. 7 generates an identification code for the lower 6 bits of the code word that always starts with 1 and is obtained from the output of the NOT gate 24.

As can be seen from Table 3, there are 26 ways for the lower 6 bits of a code word starting with 1, as shown in Table 5.

(Left below) Table 5 Therefore, the identification code for the lower 6 bits (10)
can be expressed in 5 bits. Tables 6.1 and 6.2 show that the 9-bit identification code obtained in this way corresponds to the code word starting with 1 in Table 3 without duplication.

Table 6.2 Table 6.1 (blank below) The inverse conversion circuit 26 in FIG. 7 is for realizing Table 6, and outputs a data word for a 9-bit identification code.

The 8 EXOR gates 28 are the 8
This is for determining the exclusive OR with the inverted control signal Y for each focus. As shown earlier,
For a codeword with F=1, the codeword starting with 1 and the data word corresponding to its back pattern are also complementary to each other. Therefore, for a codeword with F=1 and TB=0, Y=1
Therefore, only in this case, the output of the EXOR gate 28 becomes the inverted value of the output of the inverse conversion circuit 27, and correct decoded data can be obtained.

As described above, the decoding circuit of the present invention uses an identification code for a bit pattern obtained by dividing a codeword, rather than the codeword itself, to reduce the R required for decoding.
The OM capacity has been reduced to 178. Specifically,
The temporary decoding circuits 25 and 26 in FIG. 7 are relatively simple logic circuits (for example, programmable log
ic Device).

Therefore, the capacity required for the decoding ROM is 29×8=4 kilobits (9 bits for address and 8 bits for output). In addition, in this example, 8/1 is highly effective for high-density recording.
Although an example of 2-conversion code conversion is shown, it is also effective for other recording codes.

Effects of the Invention The present invention converts an 8-bit data word into a 12-bit code word, and converts the code word to a 12-bit code word. For the 8/12 code, which has a performance suitable for high-density recording where d = 10, two types of synchronization patterns that never appear in the data are created for video and audio, respectively, while maintaining the restriction on d. It can be used for various purposes.

As a result, errors in determining video data and audio data due to playback errors can be greatly reduced, improving the overall error rate. Moreover, since the present invention can be realized with a very practical circuit configuration, it has great practical effects. As described above, the present invention is effective for home digital VTRs that require high-density recording.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a code conversion device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of recording blocks, FIG. 3 is a structural diagram of code words, and FIG. 4 is an explanation showing connections between code words. 5 is a structural diagram of a synchronization pattern, FIG. 6 is a circuit diagram of a synchronization detection circuit, and FIG. 7 is a block diagram of a decoding circuit.

Claims (2)

[Claims] (1) A digital signal recording method characterized in that when inserting a synchronization pattern indicating the beginning of a recording block constituted by a plurality of information symbols, the synchronization pattern is selected according to the data word. (2) The number of consecutive bits of the same binary value in a bit string obtained by converting an 8-bit data word into a 12-bit code word and connecting the code words in a recording block is 2 or more,
Sync pattern is 111110011111111110
011111 and 0000011000000000
011111. The digital signal recording method according to claim 1, wherein the digital signal recording method is 011111.