JPH04111472A - Thin film transistor memory - Google Patents

Abstract

PURPOSE:To made it possible to write in/erase on a bit basis only with form terminals of an source electrode, a drain electrode, a selection gate electrode, and a memory gate electrode by arranging a first selection transistor and a second selection transistor so as to carry out one sided channel operation and a memory transistor to carry out both sided channel operation, depending on the direction of a field to be applied. CONSTITUTION:A first selection transistor Tr 11 is arrayed in the direction of a channel while a memory transistor Tr 10 and a selection transistor Tr 12 are laid out in series where the first selection transistor Tr 11 and the second selection transistor Tr 12 are adapted to carry out one sided channel operation while the memory transistor is arranged to carry out both sided channel operation, Moreover, this construction makes it possible to write in/erase the interior of a memory array electrically and selectively only with four terminals of a source electrode 25, a drain electrodes 22 and 23 and a memory gate electrode 36. Especially, compared with the prior art memory structure which is unable to erase p channels and write in n channels, higher speed operation can be expected.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides electrical writing and writing using thin film transistors.
This invention relates to an erasable film transistor memory.

[Prior art] EEPROM that can be electrically written and erased is MNO3.
There are two types: type structure and floating gate type structure. In either case, there is a tunnel effect in writing/erasing.
ect), the write/erase current is extremely small. Therefore, when this EEPROM is used as a data memory in an electronic device such as an electronic notebook, it is possible to develop a multifunctional electronic device such as erasing all bits simultaneously and writing/erasing in page units.

The MNO3 type memory cell is an FET in which the gate oxide film of the MOSFET is replaced with a double layer structure of an extremely thin oxide film (~2OA) and a nitride film (~500A), and is made of a metal-nitride monoxide-semiconductor ( MNOS) structure FET. FIG. 12 is a diagram showing a cross-sectional structure of an n-channel MNOS memory cell.

As shown in FIG. 12, the MNOS memory 1 is constructed by depositing, for example, boron (B) on an n-type S1 substrate 2 and then thermally diffusing it into a p-w
el13 is formed, and then phosphorus (P) is implanted to form an n+ diffusion layer 4.5 which will become a source and a drain. Thereafter, a thin Si oxide film 6 is deposited thereon by, for example, thermal oxidation, and is removed leaving only the area directly below the control gate 12 (described later).

Next, an insulating layer 7, a selection gate 8, an isolation gate 9, an insulating layer 10, a silicon nitride film 11, and a memory gate (control gate) 12 are formed.

Data is written in the MNOS memory 1 by tunneling electrons (or holes) from the n+ diffusion layer 4 to the nitride film 11 through the thin oxide film 6. Of the electrons transferred into the nitride film 11, those captured at the oxide film-nitride film interface or at deep energy levels (traps) existing in the nitride film 11 contribute to data retention. It is known that not only traps for electrons but also traps for holes exist in the nitride film 11, and it is also possible to write by tunneling holes by setting the voltage of the selection gate 8 negative.

Note that for writing, a voltage pulse of about 25V (~10m
5ec) is applied. In this way, the written M
NOS memory l will have a high threshold voltage.

On the other hand, data in the MNOS memory 1 is erased by applying a voltage pulse having a polarity opposite to that of writing to the selection gate 8. Since it is necessary to expel the electrons trapped in the energy level, it is necessary to apply a pulse (for example, -30V, 100m5ec) that is higher in voltage and wider than the write pulse.

Figure 13 shows MNOS memory 1 using p-well 13.
FIG. 13 (A) is a diagram showing a write/erase driving method of
) shows an equivalent circuit of the MNOS memory 1 in FIG. In the figure, Vp is the write/erase voltage, and VON is the voltage at which the selection gate opens, and the write/erase control as shown in FIGS. 13(B) to (F) is performed depending on the voltage applied to each electrode. will be realized.

[Problems to be Solved by the Invention] However, in such a conventional EEPROM, a p-well 13 is formed in the Si substrate 2, and an nch transistor having a memory gate 12 with an MNO3 structure is formed thereon. Since the memory transistor was constructed using the same method, it was merely an extension of the MOS transistor manufacturing process technology, and it was difficult to increase the area because it was necessary to form a diffusion region such as a p-well 13.

In addition, as shown in FIG. 13, the driving method during writing/erasing uses the potential of the p-well 13 in addition to the source/drain, selection gate 8, and memory gate 12, so the number of electrodes is large. There was also a problem that the control was complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor memory structure using thin film transistors that can significantly reduce manufacturing steps and achieve higher integration and lower costs.

[Means for Solving the Problems] In order to achieve the above object, the thin film transistor memory according to the present invention includes a semiconductor layer, a source electrode and a drain electrode electrically connected to the semiconductor layer, and the source electrode and the drain 1! a floating intermediate source electrode and a drain electrode formed between the electrodes, a first selection gate electrode and a second selection gate electrode to which a selection voltage for controlling write selection/non-selection is applied, and a predetermined electrode. A thin film transistor memory comprising a memory gate electrode to which a gate voltage for moving carriers is applied, the first selection gate electrode comprising the first selection gate electrode, the source electrode and the intermediate source electrode, and the semiconductor layer. The selection transistor is controlled so that a channel portion of the semiconductor layer formed between the source electrodes operates in one channel, and the second selection gate electrode, the drain electrode and A second selection transistor including the intermediate drain electrode and the semiconductor layer is controlled to perform one-channel operation in a channel portion of the semiconductor layer formed between the drain electrode and the intermediate drain electrode, A memory transistor including the memory gate electrode, the intermediate source and drain electrodes, and the semiconductor layer has a channel portion of the semiconductor layer formed between the memory gate electrode and the intermediate source and drain electrodes. Both channels are controlled to operate depending on the direction of the electric field applied to the channel.

[Operation] According to the above-described means, the thin film transistor memory enables erasing in units of bits even though the first selection transistor and the second selection transistor operate in one channel, and prevents data from changing when not selected. In addition, since the memory transistor operates in both channels, reverse side carrier injection can be performed efficiently.

Further, it becomes possible to electrically selectively write/erase the inside of the memory array using only four terminals: a source electrode, a drain electrode, a selection gate electrode, and a memory gate electrode.

[Example] Hereinafter, the present invention will be explained based on the drawings.

1 to 11 are diagrams showing a first embodiment of a thin film transistor memory according to the present invention, and FIGS. 1 to 5 are manufacturing process diagrams of the thin film transistor memory.

First, as shown in FIG. 1, a conductive layer made of, for example, chromium (Cr) is deposited by sputtering or the like on an insulating substrate 21 made of glass or the like, and patterned to form the first selection gate of the selection transistor Trll. An electrode 22 and a second selection gate electrode 23 are formed.

Next, as shown in FIG.
A selection gate insulating film 24 made of silicon nitride (Si, N4) in a stoichiometric ratio is deposited over the entire surface of the insulating substrate 21 on which the second selection gate electrode 2 and the second selection gate electrode 23 are formed, using a plasma CVD method or the like. After that, this selection gate insulating film 24
an electrode metal film made of, for example, chromium (Cr) on top;
Polysilicon doped with impurities such as phosphorus (P)
An n-type ohmic contact semiconductor layer consisting of ly-5i) or the like is sequentially deposited and patterned to form a source electrode 25, a drain electrode 27, an intermediate source electrode 29, and an intermediate drain electrode 30. A type ohmic contact layer 26, 28° 31.32 is formed.

Next, as shown in FIG. 3, amorphous silicon (a-3i) is deposited on the selection gate insulating film 24 on which the drain electrode 25, the source electrode 27, and the intermediate source/drain electrodes 29 and 30 are formed, and then patterned. A semiconductor layer 33 is formed. In this case, phosphorus-doped polysilicon (poly-3i) is used as the ohmic contact layer 26,
When used as transistors 28, 31, and 32, memory write/erase operations can be performed for either p-channel operation or n-channel operation, which are the operating characteristics of the transistor.

After that, a thin layer of silicon nitride (SilN+) having a charge storage function is deposited on the semiconductor layer 33, and then the intermediate source/drain electrodes 29 are formed as shown in FIG.
Silicon nitride (St.

The memory nitride film 3 is etched to leave only the portion facing the memory gate electrode fli36, which will be described later.
form 4. The memory nitride film 34 is made of silicon nitride with a composition ratio St/N of silicon atoms Si and nitride atoms N that is higher in Si than the stoichiometric ratio of the selection gate insulating film 24.

Next, as shown in FIG. 5, the selection gate insulating film 2 is formed over the entire surface of the semiconductor layer 33 by plasma CVD or the like.
A memory gate insulating film 35 made of silicon nitride having the same stoichiometric ratio as 4 is formed, a conductive layer such as chromium is deposited thereon, and then patterned to form a memory transistor Trio at a position facing the memory nitride film 34. A memory gate electrode 36 is formed to complete the thin film transistor.

Thin film transistor memory 2 manufactured as above
0, one memory cell has a source electrode 25 and a drain electrode 27 electrically connected to the semiconductor layer 33, and a floating intermediate source/drain electrode 29.0 formed between the source electrode 25 and the drain electrode 27. 30, and a first selection gate electrode 22 and a second selection gate electrode 23 to which a selection voltage for controlling write selection/non-selection is applied.
and a memory gate electrode 36 to which a gate voltage for moving predetermined carriers is applied.
Source electrode 25, intermediate source electrode 29, and semiconductor layer 33
The second selection gate electrode 23, the selection gate insulating film 24, the drain electrode 27, the intermediate drain electrode 30, and the semiconductor layer 33 constitute the second selection transistor Tr12. The memory gate electrode 36, the memory nitride film 34, the intermediate source/drain electrodes 29, 30, and the semiconductor layer 33 constitute a memory transistor Trio. In other words, this thin film transistor memory 20 includes a first selection transistor Trll, a memory transistor TriO1, a second selection transistor Tr1
The memory transistor Trio has a structure in which three transistors No. 2 are arranged in series, the first selection transistor Trll and the second selection transistor Tr12 are configured to operate in one channel, and the memory transistor Trio is configured to operate in both channels.

6 and 7 show Ve of the thin film transistor memory 20.
-Io (gate voltage-drain current) characteristics, and FIG.
FIG. 7 shows the VG-ID characteristics of the selection transistor Tri2, and FIG. 7 shows the VG-ID characteristics of the memory transistor TrlO. First selection transistor Trll
As shown in FIG. 6, the second selection transistor Tr12 operates on the n-channel side, and has a characteristic that the n-channel side is easily cut off so that no current flows. As a result, the selection transistors Trll and Tr12
It has the characteristic that non-selective operation can be easily performed.

On the other hand, the memory transistor Trio has a memory gate electrode 36 and an intermediate source/drain electrode 2, as shown in FIG.
Both holes and electrons can be used as carriers depending on the direction of the electric field between 9.30 and 30°, so both channels operate on the n-channel side and the n-channel side. In this case, phosphorus-doped polysilicon (poly-3i) is used as the ohmic contact layer 26, 28, 3 between the metal film for metal electrode and the semiconductor layer 33.
Since it is used at 1°32, it does not become a barrier to the extent that it interferes with writing/erasing of the memory for either p-channel or n-channel conduction. Therefore, as described below, when appropriate bias is applied to the memory gate electrode 36, source electrode 25, and drain electrode 27, erasing and writing of data can be realized.

8 to 11 are diagrams showing erasing and writing operations of the thin film transistor memory 20.

Although FIGS. 8 to 11 show one thin film transistor memory 20, in reality, a large number of thin film transistor memories 20 are formed in a matrix.

Further, the memory nitride film 34 shown in FIG. 8 is arranged so that when the write/erase voltage Vp is applied, holes h+ or electrons e- are trapped and erase/write is performed. It is assumed that the film thickness etc. have been created.

■ Erasing (hole h+ injection into the memory nitride film 34)
As shown in the figure, by applying a negative bias (ground level in this embodiment) to the memory gate electrode 36 and applying a positive bias to the source electrode 25 and drain electrode 27, the intermediate source/drain electrode 2 is in a floating state.
This is done by applying a positive bias to 9.30 to trap holes (see h+ in FIG. 8) in the memory nitride film 34. Now, the memory gate electrode 36 is grounded, the source electrode 25 and drain electrode 27 of the memory are set to Vp, and the first selection gate electrode 22 and second selection gate electrode 23 are set to the selection partial voltage V ON -E r during erasing. Then, the first selection transistor Trll and the second selection transistor Tr
Reference numeral 12 biases the intermediate source/drain electrodes 29 and 30 of the memory to Vp in single channel (n channel) operation.

As a result, the potential of the intermediate source/drain electrodes 29 and 30 of the memory transistor TrlO becomes higher than the memory gate electrode 36 by Vp, so that
Holes h+ are emitted from the intermediate source/drain electrodes 29.30 of lO through the semiconductor layer 33 toward the memory nitride film 34. Therefore, as shown in FIG. 8, holes h+ are trapped in the memory nitride film 34, and erasing is performed in units of 1 bit.

■For a thin film transistor memory that you do not want to erase, as shown in FIG. Since the channel portions of Trll and the second selection transistor Tr12 are in a high impedance state, the intermediate source/drain electrodes 29 and 30 of the memory transistor Trlo are floating.
A potential difference similar to that of Vp applied to the source electrode 25 and drain electrode 27 is generated between the memory nitride film 34 and the memory nitride film 34 .
Internal state is preserved. In this case, in order for the data to remain in its previous state, the erasing pulse applied to the selection gate electrodes 22 and 23 must be applied for a sufficient period of time to rewrite the data during selection, and during non-selection time. It is necessary to design the memory cell so that the application ends before a large potential difference occurs between both ends of the memory.

l put up Next, writing will be explained.

Writing (electronic e-oil injection into the memory nitride film 34 is performed by applying a positive bias to the memory gate electrode 36 as shown in FIG. A negative bias (ground level in this embodiment) is applied.Then, selection/non-selection of writing in this thin film transistor memory is performed by n-channel 0N10FF operation of the transistors Tri1 and Tr12 (the first selection gate electrode 22, the second Selection gate electrode 2
This is done by controlling the flow of electrons e- with 0N10FF). Now, as shown in FIG. 10, when Vp is applied to the memory gate electrode 36 and the source electrode 25 and drain electrode 27 are grounded, the floating intermediate source/drain electrodes 29 and 30 and the memory gate electrode The potential difference Vp between memory transistor Tr
i.

There is a potential difference between the intermediate source/drain electrodes 29, 30 and the memory gate electrode 36, and as a result, the memory nitride film 3
Vp is applied across both ends of the memory transistor Trl.
Electrons e- from the intermediate source/drain electrode 29.30 of O
is injected and written. Therefore, as shown in FIG. 10, electrons e- flow into the memory nitride film 34, the memory nitride film 34 is charged with electrons e-, and writing is performed in units of 1 bit.

When writing is not selected, the first selection gate electrode 22 and the second selection gate electrode 23 are set to the write non-selection voltage Voff-Wr as shown in FIG. Since the channel portion of the transistor Tr12 is in a high impedance state, the memory gate electrode 36 is connected to the intermediate source/drain electrodes 29 and 30 of the memory transistor Trio during the short write pulse application time.
Since a Vp comparable to the Vp applied to the memory nitride film 34 appears and almost no potential difference appears between both ends of the memory nitride film 34, the internal state of the memory nitride film 34 is maintained. However, in order for this to hold true, the memory cell has the input impedance of its memory transistor Trio and the selection transistors Trll and Tr.
It is necessary to design the output impedance of No. 12 when not selected in accordance with the write pulse application time.

In this way, the selection transistors Trll and Tr12 are n
Although the memory transistor Tri operates only as a channel, it operates in both p-channel and n-channel directions.
By applying a bias to the intermediate source/drain electrodes 29 and 30, electrons e- can be efficiently supplied to the interface of the memory nitride film 34 during writing, and holes h+ can be efficiently supplied during erasing. As explained above, in this embodiment, the thin film transistor 20 is connected to the first selection transistor Trll and the memory transistor Trill in the channel direction.
, a second selection transistor Tr12 are arranged in series, and a first selection transistor Trll and a second selection transistor Tr1 are arranged in series.
2 operates in one channel, and the memory transistor TrlO
Since it is configured to operate on both channels, it is possible to prevent data from fluctuating on the transistor Trll and Tr12 sides when not selected, and on the memory transistor Trio side, since both channels operate, Injection can be performed efficiently. Also, a source electrode 25, a drain electrode 27, a selection gate electrode 22.
It becomes possible to electrically selectively write/erase the inside of the memory array using only four terminals, ie, the memory gate electrode 23 and the memory gate electrode 36.

In particular, the selection transistors Trll and Tr12 operating in one channel (n channel) select/unselect write/erase, and the intermediate source of the memory transistor Trlo
Since erasing is performed between the source electrode 22 and the memory gate electrode 29 by electrons e- during writing and holes h+ during erasing from the drain electrodes 29 and 30, p-channel erasing/n-channel programming is not possible. The speed can be increased compared to memory with a conventional structure. Furthermore, even if the structure allows p-channel erase/n-channel writing, if the selection transistors Trll and Tr12 are used to perform both channel operations, the selection transistors Trll,
There is a width in the non-selection voltage of Tr12, and the operating voltage also varies from the threshold voltages Vthp and Vt of transistor Trll.
Although an amplitude greater than or equal to hn is required, in the thin film transistor of the present invention, it is sufficient to satisfy vth of an n-channel, so the amplitude of the voltage used may be small.

In addition, since the memory gate part and the selection gate part are completely separated as a transistor, there is no need for a photolithography process to separate the memory nitride film for the memory transistor as that region. Even if the film 34 covers the entire plane, it does not affect the memory characteristics.

Furthermore, a selection transistor Tr is included in one memory cell.
Since Tr12 and the memory transistor Trlo are integrated, the manufacturing process can be greatly simplified, and by integrating them, it is possible to achieve high integration and a large area. can.

[Effects of the Invention] According to the present invention, the first selection transistor and the second selection transistor are configured to operate in one channel, and the memory transistor is configured to operate in both channels depending on the direction of the applied electric field. It is possible to prevent fluctuations in data when not selected, and to increase the efficiency of carrier injection. Writing/erasing becomes possible. Furthermore, the selection transistor and the memory transistor can be integrated into one memory cell, which greatly simplifies the manufacturing process and reduces costs, and also allows for higher integration and larger area.

[Brief explanation of the drawing]

1 to 11 are diagrams showing an embodiment of a thin film transistor memory according to the present invention, FIGS. 1 to 5 are manufacturing process diagrams of the thin film transistor memory, and FIG. 6 is a Vc-ID characteristic of a selection transistor. 7 is a V c -I D characteristic diagram of a memory transistor, FIG. 8 is a diagram for explaining the movement of carriers during erasing, and FIG. 9 is a diagram for explaining the operating state when erasing is not selected. Figure 10 is a diagram for explaining the movement of carriers during writing, Figure 11 is a diagram for explaining the operating state when writing is not selected, and Figure 12 is a diagram showing the cross-sectional structure of a conventional thin film transistor memory. 13 are diagrams showing a conventional method for driving a thin film transistor memory. TrlO...Memory transistor, Trll...
- Selection transistor, Tr12...Second selection transistor, 20...Thin film transistor memory, 21
... Insulating substrate, 22 ... First selection gate electrode, 23 ... Second selection gate electrode, 24 ...
Selection gate insulating film, 25...source electrode, 27...
...Drain electrode, 29.30...Intermediate source/drain electrode, 33...Semiconductor layer, 34...Memory nitride film, 35...Memory gate insulating film, 36...
...Memory gate electrode. Patent applicant: Casio Computer Co., Ltd.

Claims (1)

[Claims] (1) A semiconductor layer, a source electrode and a drain electrode electrically connected to the semiconductor layer, a floating intermediate source electrode and drain electrode formed between the source electrode and the drain electrode, and a writing A thin film transistor memory comprising a first selection gate electrode and a second selection gate electrode to which a selection voltage for controlling selection/non-selection is applied, and a memory gate electrode to which a gate voltage for moving predetermined carriers is applied. A first selection transistor including the first selection gate electrode, the source electrode and the intermediate source electrode, and the semiconductor layer is formed between the source electrode and the intermediate source electrode. A second selection transistor is controlled such that the channel portion of the semiconductor layer operates in one channel, and the second selection transistor includes the second selection gate electrode, the drain electrode and the intermediate drain electrode, and the semiconductor layer. A channel portion of the semiconductor layer formed between the drain electrode and the intermediate drain electrode is controlled to perform one-channel operation, and the memory gate electrode, the intermediate source electrode and the drain electrode, and the semiconductor layer The memory transistor is controlled to operate in both channels depending on the direction of an electric field applied to a channel portion of the semiconductor layer formed between the memory gate electrode and the intermediate source and drain electrodes. thin film transistor memory.