JPH04111412A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the drawing reliability of a semiconductor device manufacturing method by controlling a positional deviation of a substrate during the course of the drawing caused by wrong alignment detection or charge up of a substrate being drawn and improving the positioning accuracy. CONSTITUTION:A wafer is positioned to a stage coordinate system by finding the reference position and extended/contracted and rotated components of the wafer by using two or more arbitrary alignment marks on the wafer. By scanning the alignment marks with electron beams and differentiating the obtained reflected electron waveform, the positions of the alignment marks are measured from two peak values. Alignment of the wafer is performed by measuring the positions of a plurality of alignment marks and finding the deviated quantity of the marks from their original positions. After drawing, positions of the alignment marks are again measured and the deviated quantities of the marks are found. The positional deviation is compared with a standard value and, when the deviation is within a standard value, the deviation is fed back to the movement of a stage. When the deviation exceeds the standard value, the deviation is fed back to the movement of the stage after the faulty pattern is exposed and the next chip is exposed.

Description

[Detailed Description of the Invention] [Summary] Direct exposure (drawing) on a substrate using an electron beam exposure device, etc.
Regarding how to do it.

The purpose is to guarantee alignment accuracy including positional deviation during drawing, increase reliability of drawing, and eliminate chips with one positional deviation defect.

1) Align the substrate using an alignment mark formed on the substrate for each block containing a chip or multiple chips.9 Then, after exposing the substrate to light, detect the alignment mark again and measure the amount of positional deviation. The amount of positional deviation is compared with a standard value to determine the quality of the chip or block.

2) A chip or block that is found to be defective in the above determination is configured to be exposed to a pattern that can be excluded as defective in an electrical test.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for directly exposing a substrate to light using an electron beam exposure device or the like.

In recent years, as semiconductor devices have become more highly integrated and miniaturized, alignment margins in lithography processes have become increasingly strict, making it difficult to manage alignment accuracy.

The present invention can be used as a method for managing alignment accuracy and a method for processing non-standard chips by addressing this difficulty.

[Conventional technology]

The current alignment method in direct writing detects the alignment mark inserted in each chip or block containing multiple chips, calculates an alignment correction value, and returns this correction value to the drawing means to perform drawing. ing.

Also, check the positional deviation of the actual device pattern.

This was done by observing the exposed and developed substrate (wafer, mask, etc.).

(Problems to be Solved by the Invention) Therefore, there is a possibility of positional deviation due to erroneous detection during alignment before exposure, or positional deviation due to charge-up that accumulates on the substrate during drawing, and the actual pattern after development. A problem has arisen in that it is impossible to judge whether the product is good or bad without observing it.

In addition, for development inspection of only a specific wafer or chip,
Since information on positional deviations for all wafers and all chips cannot be obtained, a problem has arisen in that defective chips cannot be excluded.

An object of the present invention is to ensure alignment accuracy including positional deviation during drawing, thereby increasing the reliability of drawing and making it possible to exclude chips with one positional deviation defect.

[Means to solve the problem]

What is the solution to the above problem?

1) Align the substrate using an alignment mark formed on the substrate for each block containing a chip or multiple chips.9 Then, after exposing the substrate to light, detect the alignment mark again and measure the amount of positional deviation. and 2) a method for manufacturing a semiconductor device in which the amount of positional deviation is compared with a standard value to determine the quality of the chip or block, or 2) a method in which a chip or block that is found to be defective as determined by the above determination can be excluded as defective in an electrical test. This is achieved by the method for manufacturing a semiconductor device described in item 1) above, which exposes a pattern with light.

[Effect]

The present invention detects the alignment mark on the chip again after normal alignment and exposure processing, measures the amount of positional deviation, and compares it with a preset standard value to determine whether the chip is good or not. This is to ensure that there is no misalignment inside.

In addition, non-standard chips are exposed by superimposing a pattern that can be excluded as defective in an electrical test (a pattern that becomes defective in a wafer blowing test, hereinafter referred to as a defective pattern) on the above exposure.

〔Example〕

FIG. 1 is a flowchart of a drawing process explaining one embodiment of the present invention.

Next, examples will be explained in order of steps.

(1) Pre-alignment Here, wafer alignment is performed.

Using two or more arbitrary alignment marks on the wafer, a rough reference position of the wafer, expansion/contraction and rotational components of the wafer are determined, and the wafer and stage coordinate systems are aligned.

(2) Stage movement The stage is stepped and repeated for each chip.

(3) Alignment The alignment mark is scanned with an electron beam, the resulting reflected electron waveform is differentiated, and the position of the alignment mark is measured from the two peak values (see Figure 2).

FIGS. 2(a) to 2(C) are diagrams illustrating position measurement of alignment marks.

FIG. 2(a) shows the cross-sectional shape of the alignment mark,
FIG. 2(b) shows a reflected electron waveform obtained when the electron beam scans across the alignment mark, and FIG. 2(C) shows its differential waveform.

For alignment, measure the positions of multiple alignment marks using the method described above (see Figure 3).9) Find the amount of deviation from the original (designed) mark position.

An electron beam deflection correction coefficient (amplifier gain per revolution, height, offset, etc. in the deflection section of the electron beam lithography apparatus) corresponding to the amount of deviation is determined.

FIG. 3 is a plan view showing an example of position measurement of a plurality of alignment marks.

In the figure, the cross mark indicates an alignment mark, and the square shape indicates a chip.

Here, the positions of four alignment marks are measured.

(4) Exposure For example, in the case of a variable rectangular beam, the pattern data on the memory is transferred to a pattern generator to perform optimal shot division. Furthermore, the image is drawn after being corrected using the deflection correction coefficient obtained in (3) above.

(5) Re-alignment (feature of the present invention) After drawing, the position of the alignment mark is measured again using the deflection correction coefficient determined in (3) above, and the amount of deviation from the original mark position is determined.

An example showing the tendency of deviation in a normal chip is shown in FIG.

FIG. 5 shows an example of the trend of abnormal chip displacement due to charge-up during exposure.

In Figures 4 and 5, 1 point is a measurement point, and 4 points per location.
Measurements are taken point by point. The solid line rectangular figure is the original design figure, and the dotted line square figure is the actual measured figure.

(6) Determining the amount of positional deviation, and (7) Exposure of defective patterns Compare the amount of positional deviation with the standard value.

(a) If it is within the specifications, return to stage movement in (2).

Expose the next chip.

(b) If it is out of specification, after exposing the defective pattern.

Returning to the stage movement in (2), the next chip is exposed.

FIG. 4 is a plan view showing an example of the tendency of deviation in a normal chip.

FIG. 5 shows abnormalities caused by charge-up during exposure [effects of the invention] As explained above, according to the present invention, positional deviations during drawing due to misdetection of alignment, charge-up of the substrate during drawing, etc. It is now possible to improve the reliability of drawing by managing and guaranteeing alignment accuracy.

Furthermore, chips with 9 misaligned defects can now be excluded by a blobbing test.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart of a drawing process explaining an embodiment of the present invention. FIGS. 2(a) to 2(C) are diagrams illustrating position measurement of alignment marks. FIG. 3 is a plan view showing an example of position measurement of a plurality of alignment marks. Diagram of the deviation of the tip (a) -L''-Explanatory diagram of the 1st measurement of haze No. 3 Diagram 0.1μm 0.1μm Discrepancy between normal t and tip Diagram 4 * Normal t and tip 5th flash of misalignment

Claims (1)

[Claims] 1) Aligning the substrate using an alignment mark formed on the substrate for each block containing a chip or a plurality of chips, and then detecting the alignment mark again after exposing the substrate to light. A method of manufacturing a semiconductor device, comprising: measuring the amount of positional deviation, and comparing the amount of positional deviation with a standard value to determine the quality of the chip or block. 2) The method of manufacturing a semiconductor device according to claim 1, wherein the chip or block determined to be defective by the determination is exposed to a pattern such that it can be excluded as defective in an electrical test.