JPH04111169A - Circuit design system - Google Patents

Abstract

PURPOSE:To easily design a pipe line processing circuit by referring to a means where a question rule is stored, deciding the details of the attribute of an element, referring to a means where a conversion rule is stored, and converting a directed graph having operation attribute into a circuit diagram. CONSTITUTION:A user selects a data pass from among menues, connects the selected data passes according to the flow of data with the directed graph. A detail decision part 5 retrieves a table 4 where the question rule is stored based on the output of a graphic editor 3 to decide each attribute of the data pass, operation, and signals, and the question items are presented to a designer by displayed in an area 23 of an editor 3. A circuit conversion part 7 refers to a table 6 where the conversion rule is stored to be converted the directed graph having operation attribute into the circuit diagram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a circuit design method, and particularly to a design method for automatically generating a circuit from a directed graph with behavior.

[Prior Art] As a conventional computer-aided design system, a logic synthesis system that enables circuit design by inputting a flowchart is known (for example, Japanese Patent Application Laid-Open No. 1-30918
Publication No. 5).

[Problem to be Solved by the Invention 1] The above technology allows even software engineers who are not hardware experts to automatically generate circuits by simply writing a flowchart. Describing a processing format (a processing format in which data is sent to a group of modules and output is obtained continuously after a certain delay time) in a flowchart is complicated, and the flow of data becomes complicated. . Furthermore, conventional directed graphs can only describe connection relationships between nodes, and thus lack versatility.

It is an object of the present invention to provide a circuit design formula that can easily design a panoply processing circuit.

[Means for Solving the ε Problem] In order to achieve the R+i objectives, the present invention proposes a hierarchical design of LSI. -C1λL) system, - a graph editor for editing a directed graph that views behavioral attributes, a means for storing an editor menu defining elements used in the graph editor, and an editing rule for the graph editor. a means for storing quality rules for determining the details of the element; and a means for determining the attribute details of the element by referring to the query rule or the stored means based on the output of the graph editor. a circuit for converting a directed graph having the behavior attribute into a circuit diagram by referring to the stored conversion rule; The user uses the keyboard or mouse to select the data bus in the displayed menu and displays it at a predetermined position on the screen. Connect the pig paths with a directed graph according to the data flow. At that time, select U action from the displayed menu and create an undirected graph with actions by adding action attributes to the connection relationship of the graph. , automatically converts the created directed graph with behavior into a circuit diagram.

[Example] Hereinafter, an example of the wooden invention will be specifically described with reference to the drawings.

FIG. 1 is a functional block diagram according to an embodiment of the present invention.

” is a table that stores editor menus, and includes elements that can be used in the graph editor (pig path, movement,
signal) is defined. Here, a data bus corresponds to a node in a circuit graph that has the function of holding data.A specific example of a data bus is shown in Figure 6 (adders, multipliers shall have a latch to hold data). Also, the operation is
It defines the operation of the data bus when a clock signal is input, and represents the connection relationship between the data buses during circuit conversion, which will be described later. The operation definition is shown in FIG. Furthermore, the signal represents input data corresponding to the starting point of the graph and output data corresponding to the ending point of the graph, and the signal definition is shown in FIG.

2 is a table storing editing rules for the graph editor, which defines usable operations on each data bus, and the rules are shown in FIG.

3 is a graphic editor for directed graphs with actions, and the screen image thereof is shown in FIG. In Figure 2,
21 is a work area for creating a directed graph with behavior;
Reference numeral 22 is an area where a menu read from table 1 that stores editor menus is displayed, and 23 is an area where question rules to be described later are displayed, and is a window for interaction with the user.

The user selects a data bus from the displayed menu using the keyboard or mouse and directs it to be displayed at a predetermined position on the screen. Then, the selected data buses are connected using a directed graph according to the flow of the pig. In that case, a directed graph with an action is created by selecting an action from the displayed menu and adding an attribute of the action to the connection relationship of the graph. Also,
Interface with external signals can be done using the signal menu (1 person,
○Select from

4 is a table in which interrogation rules for determining details of data buses, operations, and signals are stored.

This table further includes options for the designer (e.g.
(selection of number of bits), advice (designation of number of characters), etc. Figure 10 shows the question rule.

Reference numeral 5 denotes a detailed determination unit which searches table 4 in which question rules are stored based on the output of graphic editor 3 and converts the question items into editor 3 in order to determine each attribute of the data bus, operation, and signal. It is presented to the designer by displaying it in area 23.

In that case, advice or options are presented to help the designer answer the question. By answering the questions presented, the designer determines the data bus, operation,
Each attribute of the signal is determined.

6 is a table storing conversion rules for creating a circuit diagram, and FIG. 1 shows the conversion rules.

Reference numeral 7 denotes a circuit conversion unit that converts the directed graph with behavior into a circuit diagram by referring to the table 6 in which conversion rules are stored.

The present invention will be explained below using specific examples.

FIG. 3 shows an example of a directed graph with operations created by the graphic editor 3, in which 31 to 33 are registers that are data buses, 34 and 35 are adders, and 36 is a counter. Attribute (MOV, 5
FTL1 etc.) are added. This graph shows the input I
The process of outputting the AND of the result of multiplying N by 11 (decimal) and FF (hexadecimal) to the output OUT is expressed using a shift operation and an adder. The arrows between the data buses
It represents the state transition in one clock.

FIG. 4 shows the operation of the pipeline along with clocks.

The circuit becomes matte state due to R3 signal and 1, CLK
Pipeline processing progresses depending on the signal. When the first clock is input, it is transferred to the first input ■\1 or REGi.

At the second clock l2\1 and ■\]X2 (SETLI
) or A D D l, ■ \1 or REG2, and the second input ■ N2 or RE G l. lNlX8 and A with the third clock and REG2 multiplied by 8 (SFTL3)
D D l result (lNlX3) goes to ADD2, ■X2
and■\2×2 goes to ADDl, IN2 goes to REG2, 3rd
input IN3 is transferred to REG1. At the fourth clock, the AND output of the result of ADD2 (INlx+1) and FF (hexadecimal) is sent to REG3, which is REG2 multiplied by 8.■
The result of N2×8 and ADDl (■\2×3) goes to ADD2, IN3 and ■\3×2 go to ADDI, IN3 goes to REG2
, the fourth input 4 is transferred to REGI. below,
Since it operates in the same way, its explanation will be omitted.

FIG. 5 is a circuit diagram obtained by converting the directed graph with behavior shown in FIG. 3 using the conversion rules shown in FIG. 11.

In this circuit diagram, the connection line 51 between REG2 and ADD2 is wired with a 3-bit shift, and R
The connection line 52 between EGI and ADDl is designed to be wired with a one bit shift.

Further, the connection line 53 is designed to connect CLK and an increment terminal.

[Effects of the Invention] As described above, according to the present invention, a circuit is automatically generated from a directed graph with behavior, so a design method that allows easy understanding of data flow can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram according to an embodiment of the present invention;
Figure 2 shows a screen image of the graphic editor of the present invention, Figure 3 shows an example of a directed graph with motion created by the graphics editor, and Figure 4 clocks the pipeline operation. Figure 5 shown with
The figure shows a circuit diagram obtained by converting a directed graph with behavior using conversion rules, Figure 6 shows a specific example of a data bus, Figure 7 shows a behavior definition, and Figure 8 9 is a diagram showing the signal definition, FIG. 9 is a diagram showing the editing rules, and 1st
FIG. 0 is a diagram showing the question rule, and FIG. 11 is a diagram showing the conversion rule. A table that stores the editor menu, a table that stores the editing rules of the 2° graph editor, 3. A graphic editor for directed graphs with motion, 4.
A table in which question rules are stored; 5. Detail determination section; 6. A table in which conversion rules for creating a circuit diagram are stored; 7. A circuit conversion section that converts a directed graph with behavior into a circuit diagram. Fig. 1 01, IT-ADR5 00 N I'm a smart snorer.

Claims (1)

[Claims] (1) In a CAD system that performs hierarchical design of LSI, a graph editor for editing a directed graph having behavioral attributes, a means for storing an editor menu defining elements used in the graph editor, and an editing rule for the graph editor are provided. means for storing, a means for storing a question rule for determining details of the element, and a means in which the question rule is stored based on the output of the graph editor, and determining details of the attribute of the element. a means for determining details;
a means for storing conversion rules for creating a circuit diagram;
1. A circuit design method comprising: circuit conversion means for converting a directed graph having the behavior attribute into a circuit diagram by referring to a means in which the conversion rule is stored.