JPH0410820A - Voice file - Google Patents

Abstract

PURPOSE:To easily rewrite an old voice signal by converting a voice signal inputted to a coding circuit into a digital voice signal at a sampling period. CONSTITUTION:The system is devised such that N-set of storage means (terminal control memory) 32a-1-32d-32 are employed and the storage means 32a-1-32d-32 are read sequentially and repetitively at an interval being 1/N of a sampling period T of a digital signal stored in a voice memory 2 to allow each of the storage means 32a-1-32d-32 to read the signal at each interval T. Then while the storage means 32a-1-32d-32 are used to read a voice signal from the voice memory 2, one of the storage means 32a 1-32d-32 is used for the write to the voice memory 2. Thus, the recording is attained while making reproduction. Thus, while an old voice sentence is being reproduced, the sentence is rewritten into a new voice sentence with succession.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an audio file that allows a plurality of audio sentences to be output simultaneously.

[Prior Art] Conventionally, as the above-mentioned audio file, for example,
There is something like the one disclosed in No.-81't37.

This means that if N audio sentences are not read simultaneously from one audio memory, and if the audio memory stores a digital audio signal sampled at a sampling period of T, N audio sentences are read from the beginning at T/ By reading each one at intervals of N periods, each audio sentence can be read out at T
It is read out every cycle.

[Problem to be solved by the invention] However, the above-mentioned audio files are for playback only, and ROM is often used as the audio memory, so there is a problem in that it is not possible to add new audio sentences. There was. To solve this problem, for example, the audio memory should be a readable and writable RAM, or a combination of ROM and RAM.
It may be possible to use it in combination with M. but,
Even with this, in order to store a new audio sentence in RAM, the playback of the audio sentence must be interrupted, and new audio sentences can be stored during a time when the audio file is not in use.
For example, a new problem arises in that it must be carried out late at night.

An object of the present invention is to provide an audio file that solves the above problems.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an audio memory having a plurality of areas storing digital audio signals obtained by digitizing audio sentences at a predetermined sampling period T. and a readout area which is a storage area of the voice memory in which the voice sentence to be outputted from the voice memory is stored, and a readout area which is a storage area of the voice memory that stores the voice sentence to be outputted from the voice memory, and a voice sentence to be newly stored in the voice memory. N storage means each having a write area that is an area for storing a write area, and a calling means that repeats an operation of sequentially reading the stored values of the N storage means one by one at every T/N interval; The digital audio signal sent out from the audio memory is
a decoding circuit that decodes the input audio signal into an analog audio signal in response to a second control signal; an encoding circuit that encodes the input audio signal into a digital audio signal in response to a second control signal; and the called storage means. means for transmitting the stored value to the audio memory and supplying a first control signal to the decoding circuit when the stored value is in the read area; and means for supplying a second control signal to the audio memory and to the encoding circuit.

[Operation] According to the invention, the N storage means are repeatedly recalled in sequence every T/N interval. That is, both storage means are recalled every T intervals. Then, each time the readout area of the audio memory is stored in the storage means and recalled, a digital audio signal is read out from the readout area.

Since such readout is performed every T intervals as described above, it is decoded into a complete audio signal by supplying it to the decoding circuit. In addition, each time the write area of the audio memory is stored in the storage means or is recalled, that is, at intervals of T, the audio signal input to the encoding circuit is converted into a digital audio signal with a thumbblink period T. converted and written to the write area.

[Embodiment] As shown in FIG. 1, this embodiment has an audio memory 2, which consists of a read-only EFROM audio memory 4 and a readable/writable CMO5RAM audio memory 6. Audio memory 4 contains multiple audio sentences or ADPCM.
The format is memorized. The audio memory 6 also stores audio sentences in the form of ADPCM, as will be described later. These audio memories 4.6 are connected via a memory interface 8 to an address bus 10.6. It is connected to the memory bus 12.

This embodiment also includes a host computer 14,
It controls each terminal block 16a to 16d via the system hub 18. Since these terminal blocks 16a to 16d all have the same configuration, only the terminal block 16a will be described in detail, and the terminal solo block 15b will be described in detail.
For each of the components 16d to 16d, the same numerals b to d as the numerals assigned to the components of the terminal block 16a are added to the end, and the explanation thereof will be omitted.

The terminal block 6a includes an ADPCM decoding circuit 20a, a timing circuit 22a, a central processing unit 24a, a terminal broadcasting device 26a, and an ADPCM encoding circuit 28a.

The ADPCM decoding circuit 20a decodes the ADPCM signal supplied from the audio memory 4 or 6 via the memory lot 12 into a PCM signal in response to the strobe signal supplied from the timing circuit 22a.

Further, the terminal broadcasting device 26a includes 26a-1 to 26a-3.
2, a total of 32 terminals are provided, and a different terminal address is assigned to each terminal. Also, each terminal broadcasting device 2
6a-1 to 26a-32 are all output circuits 29a
and a speaker 30a, of which the one to which the control signal is supplied from the timing control circuit 22a is
At that time, the PC supplied from the ADPCM decoding circuit 20a
The M signal is demodulated into an analog audio signal and broadcast.

The ADPCM encoding circuit 28a receives an audio signal from an audio input device (not shown), converts it into an ADPCM signal, and sends it to the memory lot 12 every time the timing circuit 22a supplies a control signal.

Further, the ADPCM encoding circuit 28a supplies the CMO3RAM audio memory 6 with a write signal for writing the ADPCM signal obtained as described above into the CMO5RAM audio memory 6.

The timing circuit 22a generates a strobe signal and each control signal based on signals from the central processing unit 24a. The central processing unit 24a has the same number of terminal control memories 32a-1 to 32a-32 as the terminal broadcasting devices 26a-1 to 26a-32. and the terminal address of the terminal broadcasting device to be broadcast are stored. When it becomes necessary to perform broadcasting by the host computer 14, a built-in broadcast control program, or artificially inserted control input, the text numbers, phrase numbers, and broadcast numbers that specify the text to be broadcast are stored. This is done in response to sending the terminal address of the terminal block to each terminal block via the system bus 18.

Further, in the terminal control memory 12a-32, there is a flag indicating that the recording state is in progress when there is a recording request from the host computer 14 and the address of the above-mentioned audio sentence and the terminal address are not stored. and a CMO3RAM audio memory 6 that stores audio sentences to be recorded.
The memory address above is stored.

Next, the operation of this device will be explained. First, for convenience of explanation, a state in which only reproduction is performed will be explained.

Now, when all the terminal control memories 32a-1 to 32d-32 of each central processing unit 24a to 24d are blank, the terminal address of the terminal broadcasting device 26a-1 to 26d-32 that performs broadcasting from the host computer 14 and It is assumed that these terminal broadcasting devices 26a-1 to 26d-32 send out to the system bus 18 a command consisting of a text number and a clause number specifying a text to be broadcast.

At this time, each central processing unit 24a to 24d performs processing according to the flowchart shown in FIG. That is, it is determined whether there is a request from the host computer 14 (step S2), and if the answer is YES, it is determined whether this request is a recording request (step S4). Since it is assumed that this request is not a recording request, input the terminal address from the host computer 14 (step S
6).

Then, it is determined whether the input terminal address belongs to the terminal block to which it belongs (step S8). If the answer is NO, the process returns to step S2; if the answer is YES, the input terminal address is specified by the terminal broadcasting device. It is determined whether the program is currently being broadcast (step S tO). Is this answer YES?
If so, the process returns to step S2, and if the answer is NO, the text number and phrase number from the host computer 14 are input (step 512), and the memory address and terminal address created from these sentence numbers and phrase numbers are input. Write to an empty channel of the terminal control memory (step 514).

When data is written to each terminal control memory in this manner, each central processing unit 24a to 2'ld performs processing according to the flowchart shown in FIG. That is, the value of the counter N for specifying each terminal control memory is set to 1 (step 515), and it is determined whether the terminal control memory specified by the counter N is empty (step 518). If the answer is NO, the Nth terminal is The first memory address in the control memory that has not been sent out is transferred to the address bus 12.
(step 520). For example, if the central processing unit is 24a, the memory address 50 is as shown in FIG.
Send a. As a result, the ADPCM signal read from the audio memory 2 is input to the ADPCM decoding circuit (
After 528 in FIG. 4), the timing circuit supplies the stroller signal to the ADPCM decoding circuit (548 in FIG.
) and decoded into a PCM signal (step 522). Then, the control signal is supplied via the timing circuit to the terminal broadcasting device specified by the terminal address in the N#th terminal control memory, and the decoded PCM signal is D/A converted and converted into an analog audio signal. broadcast from the terminal broadcasting device (step 524). Then, it is determined whether all the memory addresses in the Nth terminal control memory have been read out (step 526), and if the answer is YES, the contents of the Nth terminal control memory are deleted (step 528), and the value of the counter N is set to 1. Step 530. Also, the answer to step S26 is N.

If so, jump to step 328 and proceed to step S.
Execute 30. Also, if the answer to step S18 is YES, step S30 is immediately executed.

Following step S30, the value of the counter N is the final value of 32.
(step 532), the answer is NO, or even if it is YES, if the 32nd terminal control memory is not in the recording state (the answer to step S34 is NO),
It is determined whether the value of the counter N is greater than 32 (step 536), and if the answer is NO, step 518 is executed; if the answer is YES, the value of the counter N is set to 1 (step 838), and then Step 318 is executed.

These operations are performed when the tower central processing units 24a to 24d are used only for reproduction, but these operations are regulated by timing pulses from the timing pulse generation circuit 34 shown by dotted lines or clock signals from the host computer 14. As shown in FIG. 4, each central controller 24a to 24d performs the above operations at T/32
Each central control unit 24a to 2
4a is performed at intervals of T/32×4 seconds. However, T is the ADPC stored in the audio memory 2.
This is the sampling period of the M signal. Therefore, maximum 32
Different broadcasts can be performed simultaneously from four terminal broadcasting devices.

When recording an audio sentence in the CMO5RAM audio memory 6 while reproducing it, a recording request is sent to the host computer 14 or one of the tower central processing units 24a to 24d, for example, the central processing unit 24a, via the system hub 18. Then, as shown in FIG. 2, the answers to step S2.4 are both YES, and the recording terminal control memory 32a-32
It is determined whether it is empty (step 540). If the answer is No, the process returns to step S2, and if the answer is YES, the sentence number given by the host computer 14 to be added to the new audio sentence to be recorded and the time required to record the audio sentence. is input (step 542).

Then, the memory address determined based on the text number and the number of seconds of recording is stored in the terminal control memory 32a-32, and a flag is set to indicate that the recording state is in progress (step 544).

As a result, for example, when the terminal control memory 32a-:12 is specified (when the answer to step S32 is YES)
As shown in FIG. 3, since the recording state flag is set, the answer to step S34 is YES, and the first memory address that has not been sent out in the 32nd terminal control memory 32a-32 is assigned to the address bus. IO (step 546), now assigning this memory address to the fourth
It is assumed to be 50a in the figure. Next, the ADPCM encoding circuit 28a that has already been converted from the audio input signal is stored on the memory bus 12.
ADPCM signal being sent from (56a in Figure 4)
is written to the above memory address in response to a write signal (58a in FIG. 4) (step 848). In addition,
The write signal is A in response to a control signal generated by the timing circuit 22a according to instructions from the central processing unit 24a.
The DPCM encoding circuit 28a generates the signal. Next, ADPCM
The timing circuit 22 sends a conversion instruction signal to the encoding circuit 28a.
a to the central processing unit 24a (step 5).
50). This conversion instruction signal is shown as 60a in FIG. This causes the ADPCM encoding circuit to start converting the audio signal input thereto into an ADPCM signal. The ADPCM signal thus converted is stored in the CMO3RAM audio memory 6 the next time step S48 is executed. Following step S50, it is determined whether all memory addresses of the 32nd terminal control memory 32a-:12 have been read (step 552), and the answer is YES.
If S, all contents of the 32nd terminal control memory 32a-32 are erased (step 554), step S36
Execute. Further, if the answer to step S52 is No,
Step S54 is jumped to and step S36 is executed. Thereafter, step S18 is executed via steps S36 and S38. Therefore, the ADPCM signal is stored in the CMO5RAM audio memory 6 at intervals of T/32. During this time, broadcasting is being performed from other terminal broadcasting devices stored in the terminal control memory in the same manner as described above.

In the above embodiment, four terminal blocks were provided, but this number can be increased or decreased as desired depending on the situation, and the minimum number is one.
Only one terminal block may be provided. In addition, in the above embodiments, either an ADPCM encoding circuit is provided in each terminal block so that recording can be performed from any terminal block, or an ADPCM encoding circuit is provided only in a specific terminal block, and that terminal block It may also be possible to make recording possible only from the source. Further, in the above embodiment, all the addresses where the plurality of ADPCM signals constituting the audio sentence to be broadcast from the broadcasting terminal device serving as the terminal control memory are stored are stored, but each time the reading timing comes, The address may also be supplied from the host computer 14. Similarly, ADPC is added to CMO3RAM audio memory.
Although all the addresses for writing the M signal are stored in the terminal control memory, these may also be supplied from the host computer at each write timing.In addition, in the above embodiment, the addresses are stored in the terminal control memory used for recording. You can search for a terminal control memory that is not used for playback when a specific terminal control memory is not used for playback, or search for a terminal control memory that is not used for playback when a recording request is generated, or use it for recording. A dedicated terminal control memory may be provided.

[Effects of the Invention] As described above, according to the present invention, N storage means (terminal control memories) are used, and these storage means are stored at 1 of the sampling period T of the digital signal stored in the audio memory.
By sequentially and repeatedly reading data at intervals of /N, each storage means is configured to be read at intervals of T.
While these storage means are used to read out audio from the audio memory, one of them is used for writing into the audio memory. Therefore, it is possible to perform recording while performing playback, and there is no need to take the trouble to interrupt the playback operation for recording, or to perform recording late at night when the playback operation is not being performed. In particular, as in this embodiment, if the terminal control memory used for writing is the terminal control memory 32a-32 that is finally called, for example, the digital audio signal at the address to be rewritten can also be stored in other terminal control memories. Even if the old digital audio signal is read out, it is rewritten with a new digital audio signal immediately after being read, so that the old audio sentence can be rewritten to a new audio sentence without stopping while reproducing the old audio sentence.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of an audio file according to the present invention, FIG. 2 is a flowchart of a part of the same embodiment, and FIG.
This figure is a flowchart of other parts of the same embodiment, and FIG. 4 is an operation timing chart of the same embodiment. 2...Audio memory, 20a to 20d...A
DPCM decoding circuit, 24a to 24d...Central processing unit (calling means, supplying means), 28a to 28
d... ADPCM encoding circuit, 32a-1 to 3
2d-32...Terminal control memory (storage means). Patent applicant T-O-Nee Co., Ltd. Agent Satoshi Shimizu Haka 2nd person
figure

Claims (1)

[Claims] (1) An audio memory having a plurality of areas storing digital audio signals obtained by digitizing audio sentences at a predetermined sampling period T, and the audio in which the audio sentences to be output from the audio memory are stored. N storage means each having one for storing a reading area which is a storage area of the memory and one for storing a writing area which is an area for storing an audio sentence to be newly stored in the audio memory. and a calling means that repeats an operation of sequentially reading out the stored values of the N storage means one by one at every T/N interval, and a calling means that responds to the first control signal by the digital audio signal sent from the audio memory. a decoding circuit that decodes the input audio signal into an analog audio signal in response to a second control signal; an encoding circuit that encodes the input audio signal into a digital audio signal in response to a second control signal; means for sending this to the audio memory and supplying a first control signal to the decoding circuit; and when the recalled storage value of the storage means is a write area, supplying this to the audio memory; and means for supplying a second control signal to the encoding circuit.