JPH04107940A - Semiconductor device and its component parts - Google Patents

Semiconductor device and its component parts

Info

Publication number
JPH04107940A
JPH04107940A JP2225058A JP22505890A JPH04107940A JP H04107940 A JPH04107940 A JP H04107940A JP 2225058 A JP2225058 A JP 2225058A JP 22505890 A JP22505890 A JP 22505890A JP H04107940 A JPH04107940 A JP H04107940A
Authority
JP
Japan
Prior art keywords
pad
bonding wire
adjustment
impedance
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2225058A
Other languages
Japanese (ja)
Inventor
Sadayuki Daikuhara
大工原　貞行
Norio Nakazato
典生 中里
Chiyoshi Kamata
千代士 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Ltd
Hitachi Tohbu Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Tohbu Semiconductor Ltd filed Critical Hitachi Ltd
Priority to JP2225058A priority Critical patent/JPH04107940A/en
Publication of JPH04107940A publication Critical patent/JPH04107940A/en
Pending legal-status Critical Current

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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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Abstract

PURPOSE:To suppress the deterioration of a signal by providing a regulating means for matching the inductance of a signal-transmitting bonding wire and the ground electrostatic capacitance of the end of the signal-transmitting bonding wire to a transmission impedance. CONSTITUTION:A pad 2 for transmitting very high frequency signals is provided on the package 7 side and a regulating bonding pad 8 is arranged in the manner of adjoining a pad 5 provided on the chip 3 side. A signal-transmitting bonding wire 4 by means of a metal wire is connected between the pads 2 and 5 and a regulating bonding wire 9 is connected between the pads 2 and 8. Therefore, an inductance L2 by a wire 9 and a circuit by a stray electrostatic capacitance 10(C2) formed between the pads 2 and 8 relative to an inductance L1 by a wire 4 and a circuit by a stray electrostatic capacitance 6(C1) are added to the pad 2. In this case, impedance is regulated by change of the length and diameter of the wire 9. Thus, it is possible to conduct impedance matching and to raise a maximum frequency.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の信号伝送インピーダンスの整合を
図ると共に使用周波数を高める技術、特に、ギガヘルツ
域の周波数でのインピーダンス整合及び動作を可能にす
るために用いて効果のある技術に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a technology for matching the signal transmission impedance of a semiconductor device and increasing the usable frequency, particularly enabling impedance matching and operation at frequencies in the gigahertz range. It relates to techniques that can be used effectively.

σ従来の技術］ 一般に、リードフレームを用いた半導体装置は、リード
フレームと半導体チップとの間の電気的接続をワイヤボ
ンディングにより行っている。このような構造では、ボ
ンディングワイヤがチップ内のパターンの長さに比べて
長いため、例えば、数ギガヘルツ域の周波数になるとボ
ンディングワイヤに形成されるインダクタンスが無視で
きなくなり、このインダクタンスと浮遊静電容量とによ
って周波数特性が決定される。[Sigma] Prior Art] Generally, a semiconductor device using a lead frame uses wire bonding to electrically connect the lead frame and the semiconductor chip. In such a structure, the bonding wire is long compared to the length of the pattern inside the chip, so at frequencies in the several gigahertz range, for example, the inductance formed in the bonding wire cannot be ignored, and this inductance and stray capacitance The frequency characteristics are determined by

従来より、ボンディングワイヤのインダクタンスを低減
する技術として、次のようなものが知られている。Conventionally, the following techniques have been known as techniques for reducing the inductance of bonding wires.

■ボンディングワイヤの長さを短縮する。■Reduce the length of bonding wire.

■ワイヤ径を太くする。■Increase the wire diameter.

■ワイヤ数を増やす。すなわち、複数のワイヤを並列接
続する。■Increase the number of wires. That is, multiple wires are connected in parallel.

なお、この種の技術については、例えば、ＧａＡｓＩＣ
Ｓｙｍｐｏｓｉｕｍ　ＴｆｌｉＣ）ＩＮｒＣＡＬ　ＤＩ
ＧεＳＴ　（ガ！Ｊ’７ムー７シニード・アイシー・シ
ンポジウム　テクニカル・ダイジェスト）　Ｎｏｖｅｍ
ｂｅｒ　６−９．１９８８　　（１９８８・　　年１１
月発行）に記載がある。Regarding this type of technology, for example, GaAs IC
Symposium TfliC)INrCAL DI
GεST (Ga!J'7mu7 Sinead IC Symposium Technical Digest) Novem
ber 6-9.1988 (1988/ Year 11
(issued in May).

ところで、本発明者は、半導体装置の超高周波域におけ
る周波数特性の劣化及び入・出力インピーダンスの不整
合の問題について検討した。By the way, the present inventor has studied the problems of deterioration of frequency characteristics and mismatching of input and output impedances in the ultra-high frequency range of semiconductor devices.

以下は、本発明者によって検討された技術であり、その
概要は次の通りである。The following are the techniques studied by the present inventor, and the outline thereof is as follows.

例えば、通信などのインターフェースに用いられる半導
体装置は、８ビツト、１６ビツトなどのパラレル信号を
シリアル信号に変換するように構成されているが、上記
したように７リアル信号ラインにボンディングワイヤを
用いた場合、ライン中にインダクタンスが直列挿入され
るたぬ、その等価回路は第７図の如くになる。For example, semiconductor devices used for communication interfaces are configured to convert 8-bit, 16-bit, etc. parallel signals into serial signals, but as mentioned above, bonding wires are used for the 7 real signal lines. In this case, the equivalent circuit is as shown in FIG. 7, unless an inductance is inserted in series in the line.

すなわち、リードｌのバッド２とチップ３との間はボン
ディングワイヤによって接続されるが、このボンディン
グワイヤ４がインダクタンスＬを持っている。また、パ
ッケージ７のパッド５とアースライン（または電源ライ
ン）との間には浮遊静電容量６　（Ｃ）が生じている。That is, the pad 2 of the lead L and the chip 3 are connected by a bonding wire, and this bonding wire 4 has an inductance L. Further, a stray capacitance 6 (C) is generated between the pad 5 of the package 7 and the earth line (or power line).

周波数の上限を高くするにはＬ及びＣは小さいほど良い
結果が得られるが、これらを０にすることはできない。In order to raise the upper limit of the frequency, the smaller L and C are, the better the result, but they cannot be set to zero.

このインダクタンスＬと浮遊静電窓１６　　（Ｃ）がロ
ーパスフィルタを形成し、このＬとＣから遮断周波数及
びインピーダンスが決定される。通常、インピーダンス
は５ｏΩに設定されので、インピーダンス２は次のよう
に表される。This inductance L and the floating electrostatic window 16 (C) form a low pass filter, and the cutoff frequency and impedance are determined from this L and C. Normally, impedance is set to 50Ω, so impedance 2 is expressed as follows.

２＝帽；７こ 信号伝送においては、不整合による伝送損失やノイズの
混入の影響が重視されるから、インピーダンス２を指定
値（この場合、５ＤΩ）にしなければならない。したが
って、インダクタンス４及び浮遊静電容量６は、インピ
ーダンスＺを決めることのみを考えて決定し、最高周波
数の決定を配慮して決めることはない。つまり、遮断周
波数は、インピーダンスＺを決めるために出されたしと
Ｃから一義的に定まることになる。2=hat; 7 In signal transmission, since emphasis is placed on transmission loss due to mismatch and the influence of noise mixture, impedance 2 must be set to a specified value (in this case, 5DΩ). Therefore, the inductance 4 and the stray capacitance 6 are determined by considering only the determination of the impedance Z, and are not determined by considering the determination of the highest frequency. In other words, the cutoff frequency is uniquely determined from the resistance C that is taken out to determine the impedance Z.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところが、前記の如くボンディングワイヤのＬと浮遊静
電容量を用いて信号伝送用のインピーダンスを形成する
半導体装置においては、インピーダンスを設計値にする
とＬ及びＣの値が大きくなり、使用可能な最高周波数が
低くなるという問題のあることが本発明者によって見い
出された。However, in semiconductor devices that use L of the bonding wire and stray capacitance to form impedance for signal transmission as described above, when the impedance is set to the design value, the values of L and C become large, and the maximum usable frequency is The inventors have discovered that there is a problem in that the ratio becomes low.

将来、大量のデータを扱うことが予想され、このために
、例えば光通借及び超高周波（１０〜２０ギガヘルツ）
を用いたシステムが考えられるが、現状では数ギガヘル
ツが限度である。In the future, it is expected that large amounts of data will be handled.
It is possible to consider a system using , but currently the limit is several gigahertz.

また、従来においては、周波数が高いた於に、ワイヤの
微妙な形崩れや長さの違い、或いは多層間のばらつきな
どによってＬやＣに差異が生じるが、これを調整する手
段などがないため、インピーダンスを設計値に一致させ
ることが難しく、例えば第８図に示すように、インピー
ダンスが部分的（ここではボンディングワイヤ４の部分
）に不整合になりやすい。Additionally, in the past, when the frequency was high, differences in L and C would occur due to slight deformation of the wire, differences in length, or variations between multiple layers, but there was no way to adjust this. It is difficult to make the impedance match the design value, and for example, as shown in FIG. 8, the impedance tends to be partially mismatched (in this case, the bonding wire 4 portion).

そこで、本発明の目的は、ワイヤボンディングを用いな
がら、インピーダンス整合及び最高周波数を高くするこ
とが可能な技術を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a technique that can improve impedance matching and increase the maximum frequency while using wire bonding.

本発明の前記目的と新規な特徴は、本明細書の記述及び
添付図面から胡らかになるであろう。The above objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

〔課題を解決するための手段〕[Means to solve the problem]

本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下の通りである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、リードフレーム側のパッドと半導体チップ側
のパッドとを信号伝送用ボンディングワイヤによって接
続して超高周波信号の伝送路を形成する半導体装置であ
って、前記信号伝送用ボンディングワイヤのインダクタ
ンス及び前記信号伝送用ボンディングワイヤの端部の対
地静電容量を伝送インピーダンスに整合させる調整手段
を設けるものである。That is, it is a semiconductor device in which a pad on a lead frame side and a pad on a semiconductor chip side are connected by a bonding wire for signal transmission to form a transmission path for an ultra-high frequency signal, and the inductance of the bonding wire for signal transmission and the signal Adjustment means is provided to match the ground capacitance at the end of the transmission bonding wire to the transmission impedance.

〔作用〕[Effect]

上記した手段によれば、リードフレーム側または半導体
チップ側に設けられた調整用ボンディングパッドは、信
号伝送路に対し静電容量を増加させるように機能する。According to the above means, the adjustment bonding pad provided on the lead frame side or the semiconductor chip side functions to increase the capacitance with respect to the signal transmission path.

したがって、信号伝送用ボンディングワイヤのインダク
タンスによって伝送インピーダンスが上がっても、これ
を下げるように作用し、ボンディングワイヤ部分のイン
ピーダンスをその前後の信号伝送路のインピーダンスに
一致させることができ、しかも周波数特性を劣化させる
ことがない。Therefore, even if the transmission impedance increases due to the inductance of the bonding wire for signal transmission, it acts to lower this, making it possible to match the impedance of the bonding wire portion with the impedance of the signal transmission path before and after it, and also improve the frequency characteristics. It will not deteriorate.

〔実施例１〕 第１図は本発明による半導体装置の主要部を示す平面図
である。[Embodiment 1] FIG. 1 is a plan view showing the main parts of a semiconductor device according to the present invention.

第１図に示すように、超高周波信号を伝送するパッド２
はパッケージ７側に設けられ、チップ３側に設けられた
パッド５　（超高周波信号の入・出力用）に隣接させて
調整用ボンディングパッド８が配設されている。パッド
２とパッド５の間には金線による信号伝送用のボンディ
ングワイヤ４がボンディング接続され、パッド２と調整
用ボンディングパッド８の間には調整用ボンディングワ
イヤ９がボンディング接続されている。As shown in Figure 1, pad 2 transmits ultra-high frequency signals.
is provided on the package 7 side, and an adjustment bonding pad 8 is provided adjacent to the pad 5 (for input/output of ultra-high frequency signals) provided on the chip 3 side. A gold wire bonding wire 4 for signal transmission is bonded between the pad 2 and the pad 5, and an adjustment bonding wire 9 is bonded between the pad 2 and the adjustment bonding pad 8.

第２図は第１図の構成の等価回路を示し、パッド２には
ボンディングワイヤ４によるインダクタンスＬ１　　と
浮遊静電容量６　（Ｃ，）による回路に対し、調整用ボ
ンディングワイヤ９による第２のインダクタンスＬ、及
びパッド２と調整用ボンディングパッド８の間に形成さ
れる浮遊静電容量１０　　（Ｃ２＞による回路が付加さ
れた形になる。なお、第２図においては、外部回路との
接続のための５０Ωの伝送線１１がパッド２に接続され
ている。なお、リードが長くなると、インピーダンスが
規定値（５０Ω）から外れるが、これに対しては、リー
ドにマイクロストリップラインを形成してインピーダン
スを規定値になるようにしている。FIG. 2 shows an equivalent circuit of the configuration shown in FIG. L, and a circuit due to the stray capacitance 10 (C2) formed between the pad 2 and the adjustment bonding pad 8 is added. A 50Ω transmission line 11 is connected to pad 2.If the lead becomes longer, the impedance will deviate from the specified value (50Ω), but to counter this, a microstrip line is formed on the lead to increase the impedance. I'm trying to keep it at the default value.

調整用ボンディングワイヤ９を設けたことにより、パッ
ド２からチップ側を見たインピーダンスＺ０　は次のよ
うになる。By providing the adjustment bonding wire 9, the impedance Z0 when looking from the pad 2 to the chip side becomes as follows.

Ｚｏ　＝　Ｚｌ　　・Ｚ２　／　Ｚｌ　＋Ｚｘただし、 ２、＝　　４刀＝７でＥ、　　　＝　４３＝７でＴここ
で、ｚｌ　を大まかに設定し、微調整をｚ２により行う
ようにする。この場合、インピーダンスの調整は、調整
用ボンディングワイヤ９の長さ及び径を変えることによ
り行うことができる。Zo = Zl ・Z2 / Zl + Zx However, 2, = 4 swords = 7 = E, = 43 = 7 = T Here, zl is roughly set, and fine adjustment is performed using z2. In this case, the impedance can be adjusted by changing the length and diameter of the adjustment bonding wire 9.

このようなインピーダンス調整手段を設けたことにより
、外部から見た半導体装置のインピーダンスは、第３図
に示すように一定値を示し、乱れを生じることはない。By providing such an impedance adjustment means, the impedance of the semiconductor device viewed from the outside exhibits a constant value as shown in FIG. 3, and no disturbance occurs.

そして、信号の通過経路にはインダクタンスし２　が挿
入されないので最高使用周波数を高くすることができる
。Further, since no inductance 2 is inserted in the signal passage path, the maximum usable frequency can be increased.

また、調整用ボンディングパッド８を設けることにより
、従来のようにワイヤの長さ、径などを調整する方法に
比べて仕様変更などに容易に対処することができるよう
になる。Further, by providing the adjustment bonding pad 8, changes in specifications can be easily handled compared to the conventional method of adjusting the length, diameter, etc. of the wire.

なあ、第８図に示すようなインピーダンス特性の場合、
これを調整するためにはパッド５の面積を増大し、対地
静電容量を増やすことにより解決するが、これでは微妙
な調整が困難であるばかりでなく、自由度もないため、
実用的ではない。By the way, in the case of impedance characteristics as shown in Figure 8,
In order to adjust this, the solution is to increase the area of the pad 5 and increase the ground capacitance, but this not only makes delicate adjustments difficult, but also lacks flexibility.
Not practical.

〔実施例２〕 第４１！ｌは本発明の第２実施例の主要部を示す平面図
である。[Example 2] 41st! FIG. 1 is a plan view showing main parts of a second embodiment of the present invention.

本実施例は、第１図の構成における調整用ボンディング
パッド８を除去し、パッド５の面積を約２倍に拡大し、
パッド２に隣接させて調整用ボンディングパッド１２を
設ける構成にしたところに特徴がある。この場合、調整
用ボンディングワイヤ９は、パッド５と調整用ボンディ
ングパッド１２の間に接続される。In this embodiment, the adjustment bonding pad 8 in the configuration shown in FIG. 1 is removed, and the area of the pad 5 is approximately doubled.
The feature is that the adjustment bonding pad 12 is provided adjacent to the pad 2. In this case, the adjustment bonding wire 9 is connected between the pad 5 and the adjustment bonding pad 12.

このように、インダクタンスＬ１　が大きくなる傾向に
より高くなったインピーダンスが、パッケージ７の面積
の拡大による浮遊静電容量の増加により、インピーダン
ス整合を取ることが可能になる。In this way, it becomes possible to match the impedance, which has become higher due to the tendency of the inductance L1 to increase, due to the increase in stray capacitance due to the increase in the area of the package 7.

〔実施例３〕 第５図は本発明の第３実施例の主要部を示す平面図であ
る。[Embodiment 3] FIG. 5 is a plan view showing the main parts of a third embodiment of the present invention.

本実施例は、第２図の構成の特徴部分と４図の構成の特
徴部分を兼ね備えたところに特徴がある。This embodiment is characterized in that it combines the characteristic parts of the configuration shown in FIG. 2 and the characteristic parts of the configuration shown in FIG. 4.

すなわち、浮遊静電容量をパッケージ側とチップ側に１
個づつ配した構成を持ち、チップ３側には面積を拡大し
たパッド５に隣接して調整用ボンディングパッド８を設
け、リード側にはパッド２に隣接させて調整用ボンディ
ングパッド１２を設ける。そして、パッド５と調整用ボ
ンディングパッド１２及びパッド２との間に第１の調整
用ボンディングワイヤ９ａを接続し、パッド２と調整用
ボンディングパッド８間に第２の調整用ボンディングワ
イヤ９ｂを接続する。In other words, the stray capacitance is 1 on the package side and the chip side.
Adjustment bonding pads 8 are provided adjacent to pads 5 of enlarged area on the chip 3 side, and adjustment bonding pads 12 are provided adjacent to pads 2 on the lead side. Then, a first adjustment bonding wire 9a is connected between the pad 5 and the adjustment bonding pad 12 and the pad 2, and a second adjustment bonding wire 9b is connected between the pad 2 and the adjustment bonding pad 8. .

第６図は第５図の構成の等価回路図を示している。FIG. 6 shows an equivalent circuit diagram of the configuration shown in FIG.

パッド２とパッド５の間にボンディングワイヤ４による
インダクタンスＬｌ、パッド５と調整用ボンディングパ
ッド１２の間に調整用ボンディングワイヤ９ａによるイ
ンダクタンスＬ３　、パッド２と調整用ボンディングパ
ッド８の間に調整用ボンディングワイヤ９ｂによるイン
ダクタンスＬ２の各々が形成される。Inductance Ll due to bonding wire 4 between pad 2 and pad 5; inductance L3 due to adjusting bonding wire 9a between pad 5 and adjusting bonding pad 12; adjusting bonding wire between pad 2 and adjusting bonding pad 8. 9b are formed by each inductance L2.

さらに、パッド５、調整用ボンディングパッド８、及び
調整用ボンディングパッド１２の各々とアース（または
グランド）間には、静電容量Ｃ１、Ｃ２、Ｃ３の各々が
形成される。Furthermore, capacitances C1, C2, and C3 are formed between each of the pad 5, the adjustment bonding pad 8, and the adjustment bonding pad 12 and the earth (or ground).

この構成では、調整用インピーダンス回路が２段になる
ため、インピーダンス調整を微細に行うことが可能にな
る。In this configuration, since the adjustment impedance circuit has two stages, it becomes possible to finely adjust the impedance.

以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。Above, the invention made by the present inventor has been specifically explained based on Examples, but it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. stomach.

〔発明の効果〕〔Effect of the invention〕

本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記の通りであ
る。Among the inventions disclosed in this application, the effects obtained by typical ones are as follows.

すなわち、リードフレーム側のパッドと半導体チップ側
のパッドとを信号伝送用ボンディングワイヤによって接
続して超高周波信号の伝送路を形成する半導体装置であ
って、前記信号伝送用ボンディングワイヤのインダクタ
ンス及び前記信号伝送用ボンディングワイヤの端部の対
地静電容量を伝送インピーダンスに整合させる調整手段
を設けるようにしたので、ボンディングワイヤ部分のイ
ンピーダンスをその前後の信号伝送路のインピーダンス
に一致させることができ、信号の劣化を抑え、かつ周波
数特性を劣化させることがない。また、パッケージ設計
の自由度を向上させることもできる。That is, it is a semiconductor device in which a pad on a lead frame side and a pad on a semiconductor chip side are connected by a bonding wire for signal transmission to form a transmission path for an ultra-high frequency signal, and the inductance of the bonding wire for signal transmission and the signal Since an adjustment means is provided to match the ground capacitance at the end of the transmission bonding wire to the transmission impedance, the impedance of the bonding wire portion can be matched to the impedance of the signal transmission path before and after it, and the signal Deterioration is suppressed and frequency characteristics do not deteriorate. Furthermore, the degree of freedom in package design can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による半導体装置の主要部を示す平面図
、 第２図は第１図の構成の等価回路、 第３図は本発明による信号伝送路のインピーダンス特性
図、 第４図は本発明の第２実施例の主要部を示す平面図、 第５図は本発明の第３実施例の主要部を示す平面図、 第６図は第５図の構成の等価回路図、 第７図は従来の半導体装置の超高周波域における等価回
路図、 第８図は第７図の構成のインピーダンス特性図である。 １　・　・　・　リード、２・　・　・パッド、３　・
　・　・チップ、４・・・ボンディングワイヤ、５・・
・ノぜラド、６・・・浮遊静電容量、７・・・パッケー
ジ、８・・・調整用ボンディングパッド、９，９ａ、９
ｂ・・・調整用ボンディングワイヤ、１０・・・浮遊静
電容量、１１・・・伝送線、１２・・・調整用ボンディ
ングパッド。 第１図 ４：ホンディングワイヤ　　９：調整用ボンディングワ
イヤ第２図 ６．１０：浮遊静電容量　　　　１１：伝送線第３図 ワイヤ４の区間　　　　　　　　第　４　図第５図 第６図FIG. 1 is a plan view showing the main parts of a semiconductor device according to the present invention, FIG. 2 is an equivalent circuit of the configuration shown in FIG. 1, FIG. 3 is an impedance characteristic diagram of a signal transmission path according to the present invention, and FIG. FIG. 5 is a plan view showing the main parts of the third embodiment of the invention; FIG. 6 is an equivalent circuit diagram of the configuration shown in FIG. 5; FIG. is an equivalent circuit diagram of a conventional semiconductor device in an ultra-high frequency range, and FIG. 8 is an impedance characteristic diagram of the configuration of FIG. 7. 1 ・ ・ ・ Lead, 2 ・ ・ Pad, 3 ・
・ ・Chip, 4... Bonding wire, 5...
・Nozerad, 6... Stray capacitance, 7... Package, 8... Adjustment bonding pad, 9, 9a, 9
b...Adjustment bonding wire, 10...Stray capacitance, 11...Transmission line, 12...Adjustment bonding pad. Figure 1 4: Bonding wire 9: Adjustment bonding wire Figure 2 6.10: Stray capacitance 11: Transmission line Figure 3 Section of wire 4 Figure 4 Figure 5 Figure 6

Claims (1)

【特許請求の範囲】 １、リードフレーム側のパッドと半導体チップ側のパッ
ドとを信号伝送用ボンディングワイヤによって接続して
超高周波信号の伝送路を形成する半導体装置であって、
前記信号伝送用ボンディングワイヤのインダクタンス及
び前記信号伝送用ボンディングワイヤの端部の対地静電
容量を伝送インピーダンスに整合させる調整手段を設け
たことを特徴とする半導体装置。 ２、前記調整手段は、前記リード部または前記半導体チ
ップの一方に調整用ボンディングパッドを設け、このパ
ッドと前記信号伝送用のボンディングワイヤの何れか一
端との間に調整用ボンディングワイヤを接続するもので
あることを特徴とする請求項１記載の半導体装置。 ３、前記調整手段は、前記リード部および前記半導体チ
ップの各々に調整用ボンディングパッドを設け、前記調
整用ボンディングワイヤの前記調整用ボンディングパッ
ドに接続されていない側を前記信号伝送用ボンディング
ワイヤの遠方側端に接続するものであることを特徴とす
る請求項１記載の半導体装置。 ４、前記半導体チップの前記信号伝送用ボンディングワ
イヤが接続されるパッドに隣接させて、インピーダンス
調整用のボンディングパッドを設けたことを特徴とする
半導体チップ。 ５、前記リードフレームの信号伝送用のパッドに隣接さ
せて、インピーダンス調整用のボンディングパッドを設
けたことを特徴とするリードフレーム。[Claims] 1. A semiconductor device in which a pad on a lead frame side and a pad on a semiconductor chip are connected by a bonding wire for signal transmission to form a transmission path for an ultra-high frequency signal, comprising:
A semiconductor device comprising: an adjusting means for matching the inductance of the signal transmission bonding wire and the ground capacitance of the end of the signal transmission bonding wire to transmission impedance. 2. The adjustment means includes an adjustment bonding pad provided on one of the lead portion or the semiconductor chip, and connects the adjustment bonding wire between the pad and one end of the signal transmission bonding wire. The semiconductor device according to claim 1, characterized in that: 3. The adjustment means provides adjustment bonding pads on each of the lead portion and the semiconductor chip, and connects a side of the adjustment bonding wire that is not connected to the adjustment bonding pad to a far side of the signal transmission bonding wire. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to a side end. 4. A semiconductor chip, characterized in that a bonding pad for impedance adjustment is provided adjacent to a pad to which the signal transmission bonding wire of the semiconductor chip is connected. 5. A lead frame characterized in that a bonding pad for impedance adjustment is provided adjacent to a pad for signal transmission of the lead frame.
JP2225058A 1990-08-29 1990-08-29 Semiconductor device and its component parts Pending JPH04107940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2225058A JPH04107940A (en) 1990-08-29 1990-08-29 Semiconductor device and its component parts

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2225058A JPH04107940A (en) 1990-08-29 1990-08-29 Semiconductor device and its component parts

Publications (1)

Publication Number Publication Date
JPH04107940A true JPH04107940A (en) 1992-04-09

Family

ID=16823383

Family Applications (1)

Application Number Title Priority Date Filing Date
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US6459343B1 (en) * 1999-02-25 2002-10-01 Formfactor, Inc. Integrated circuit interconnect system forming a multi-pole filter
US6501343B2 (en) 1999-02-25 2002-12-31 Formfactor, Inc. Integrated circuit tester with high bandwidth probe assembly
US6538538B2 (en) * 1999-02-25 2003-03-25 Formfactor, Inc. High frequency printed circuit board via
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US6606014B2 (en) 1999-02-25 2003-08-12 Formfactor, Inc. Filter structures for integrated circuit interfaces
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US6816031B1 (en) 2001-12-04 2004-11-09 Formfactor, Inc. Adjustable delay transmission line
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