JPH0410767A - Contour emphasizing circuit - Google Patents
Contour emphasizing circuitInfo
- Publication number
- JPH0410767A JPH0410767A JP2111964A JP11196490A JPH0410767A JP H0410767 A JPH0410767 A JP H0410767A JP 2111964 A JP2111964 A JP 2111964A JP 11196490 A JP11196490 A JP 11196490A JP H0410767 A JPH0410767 A JP H0410767A
- Authority
- JP
- Japan
- Prior art keywords
- difference
- signal
- value
- data
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 238000001514 detection method Methods 0.000 claims description 5
- 230000015654 memory Effects 0.000 abstract description 6
- 230000003111 delayed effect Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はビデオ信号をテシタル化して、画像の輪郭の強
調を行う回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit that converts a video signal into digital signals and emphasizes the outline of an image.
[従来の技術]
従来ビデオ信号をテジタル化して画像の輪郭を強調する
方法として特許出願公開昭59=23974等か、提案
されている。[Prior Art] Conventionally, a method for emphasizing the outline of an image by digitizing a video signal has been proposed, such as in Japanese Patent Application Publication No. 59/23974.
[発明か解決しようとしている課題]
しかしながら、上記従来例ては、順次1水平岡期ずつ時
間のずれた複数の遅延信号を出力する遅延回路を用い、
それらの信号の相関関係を演算し、出力している。従っ
て高価なラインメモリーを複数要するため高価でありま
た、ライン間の相関を演算しなけれはならず画像の内容
によっては充分な特性が得られないという欠点があった
。[Problem to be solved by the invention] However, in the above conventional example, a delay circuit that outputs a plurality of delayed signals sequentially shifted by one horizontal interval is used,
The correlation between these signals is calculated and output. Therefore, it is expensive because it requires a plurality of expensive line memories, and it is also necessary to calculate the correlation between lines, which has the disadvantage that sufficient characteristics cannot be obtained depending on the content of the image.
[課題を解決するための手段及び作用]本発明によれば
、現画素の値と1画素前の値の差分を検出する回路を設
けることにより画像の輪郭を強調するようにしたもので
ある。この為、高価なラインメモリを必要とせず、又前
画素との差分検出を行い、演算する為、ライン間の画像
の相関のない場合においても高画質の輪郭強調か得られ
る。[Means and effects for solving the problem] According to the present invention, the outline of an image is emphasized by providing a circuit that detects the difference between the value of the current pixel and the value of the previous pixel. Therefore, an expensive line memory is not required, and since the difference between the previous pixel and the previous pixel is detected and calculated, high-quality contour enhancement can be obtained even when there is no image correlation between lines.
[実施例]
第1し1は本発明の実施例であり、
1はビデオ信号の入力端子、
2はビデオ信号をデジタル化する為に所望の帯域に制限
する為のローパス、フィルター3はアナロク/テシタル
変換器
4はナシタル/デジタルの変換を行う為の変換テーブル
てあり非線形の特性をもつ、また変換テーブルの値(非
線形の特性)を書き換え可能とする為、RAM (ラン
ダム、アクセス、メモリー)か用いられる。[Embodiment] The first embodiment is an embodiment of the present invention, in which 1 is a video signal input terminal, 2 is a low pass for limiting the video signal to a desired band for digitizing, and filter 3 is an analog/analog/video signal input terminal. The digital converter 4 has a conversion table for performing digital/digital conversion and has non-linear characteristics, and in order to be able to rewrite the conversion table values (non-linear characteristics), it uses RAM (random, access, memory). used.
5は好みの輪郭強調を得る為、4の変換テーブルの値を
書き換えるデータを供給する為のコントロー99合b、
6は現サンプル時点の画素のデータと、1画素前のデー
タを比較1ノ差分を得る為の差分検出器、及び規定差分
レベル検出後、差分レベルの極性のN転又は所定レベル
以下の差分値をイよ)だ場合、前差分値と同値て極性の
反転した差分値を加える為のデータ処理回路
7は遅延されたヒテオイ菖号のデータに差分データな加
える為の加算回路、
8は黒レベル及び白のピークレベル時 テシタルテータ
の最小値及び最大値を越えない為のリミッタ回路
9はテジタル/アナロク変換器、
】Oはビデオ信号を所望の帯域で制限する為のローパス
フィルタ
11は1画素分のデータを遅延する為の遅延素子(メモ
リー)である。5 is a controller 99 combination b for supplying data to rewrite the value of the conversion table in 4 in order to obtain the desired contour enhancement. 6 is a comparison between the data of the pixel at the current sample time and the data of one pixel before, and there is a difference of 1. After detecting the difference detector and the specified difference level, if the polarity of the difference level is N-inverted or the difference value is less than the predetermined level, add a difference value that is the same as the previous difference value but with the polarity reversed. The data processing circuit 7 is an adder circuit for adding differential data to the delayed Hiteoi Iris data, and the limiter circuit 8 is a limiter circuit 9 to prevent the minimum and maximum values of the tesital data from being exceeded at the peak levels of black and white. is a digital/analog converter; ]O is a low-pass filter 11 for limiting the video signal to a desired band; a delay element (memory) for delaying data for one pixel;
次に上記構成において、
1の入力端子に人力されたビデオ信号は2のLPFで所
望の帯域に帯域制限された後3のA/D変換器により標
本化、量子化されテシタル信号に変換され6の差分検出
器に供給される。Next, in the above configuration, the video signal inputted to the input terminal 1 is band-limited to a desired band by the LPF 2, and then sampled and quantized by the A/D converter 3 and converted into a digital signal 6. is fed to a differential detector.
6の差分検出W Lは、3よつの現画素のデータとjl
の遅延素子を経由した1画素前のデータか供給され、差
分か比較検出される。The difference detection WL of 6 is the data of the current pixel of 3 and jl
Data from one pixel before is supplied via the delay element, and a difference is compared and detected.
第3図において、1画素前のデータBより現画素のデー
タAを引き算する事により差分C(斜線部を除く)か得
られる。(T l 、 T 2T、、T、、及び丁、、
・・・T、7.は標本化の為のサンフリンクのタイミン
ク例である)
第1図6により得られた差分値は、4の変換テーブルに
よりテシタル/テシタルの非線形変換か行われる。変換
チーツルの特性は、第2図に示す様な特性を1ノており
、差分値のレベルか小さい時には次段への出力はなく、
特定のレベル以−1−においても所定のレベルて制限さ
れたレベルの差分値か出力される様な非線形の特性であ
る。In FIG. 3, the difference C (excluding the shaded area) is obtained by subtracting the data A of the current pixel from the data B of the previous pixel. (T l, T 2T,, T, and Ding,,
...T, 7. is an example of Sunflink timing for sampling) The difference value obtained from FIG. The characteristics of the conversion cheatle are as shown in Figure 2.When the level of the difference value is small, there is no output to the next stage.
This is a non-linear characteristic such that a differential value of a limited level is output at a predetermined level even below a specific level.
又4の変換テーブルの値(非線形特性)は5のコン)・
ロール部て、好みの輪郭強調レベルに書き換え可能な構
成とする為に、RAM (ランタム、アクセス、メモリ
ンか)T4いられる。Also, the value of the conversion table in 4 (nonlinear characteristics) is
The roll section requires RAM (random, access, memory) T4 so that it can be rewritten to the desired edge enhancement level.
6の差分検S」回路及び4の変換テーブルで得られた差
分信号(第2図のC>は差分信号か得られ、た後所定の
17ヘル以下、又は極性の反転1ツた差分値が得られた
場合前差分値と同値て極性の反転したレベルの差分値か
データ処理回路により伺加される。The difference signal obtained by the difference detection circuit 6 and the conversion table 4 (C> in Figure 2 is the difference signal obtained, after which the difference value is less than the predetermined 17 Herre, or the polarity is reversed by 1). If obtained, a difference value of the same level as the previous difference value but with inverted polarity is added by the data processing circuit.
第2図Cの刺li!部分か伺加された差分信号である。Figure 2 C's sting! It is a differential signal with partial addition.
この差分信号Cは次段の7の加算回路に供給されると共
に、この加算回路には11の遅延回路により遅延された
ビデオ信号か供給され、加算される。This difference signal C is supplied to an adder circuit 7 at the next stage, and the video signal delayed by an 11 delay circuit is also supplied to this adder circuit and added.
ビデオ信号Bと差分信号Cか加算される事により輪郭強
調された信号りか得られ、8のリミッタ回路に供給され
る。By adding the video signal B and the difference signal C, an edge-enhanced signal is obtained, which is supplied to the limiter circuit 8.
8のリミッタ回路ては白ピーク(デジタル化信号て表わ
される最大値)及び黒レベル(デジタル化信号て表わさ
れる最小値又は同期信号先端値までデジタル化される場
合においてはベテスタルレベル以下てかつ同期か不安定
にならないレベルに規定する)のリミッタかかけらねる
。更に9のデジタル/アナロタ変換器でアナロタ信号に
変換された後、10のLPFにより帯域制限か行われ輪
郭強調されたヒテオ信号か得られる。The limiter circuit of 8 has a white peak (the maximum value represented by the digitized signal) and a black level (the minimum value represented by the digitized signal or the leading edge value of the synchronization signal, when it is digitized, the maximum value is below the best value level and synchronization The limiter (specified at a level that does not cause instability) cannot be applied. Further, after being converted into an analog signal by 9 digital/analog converters, band-limiting is performed by 10 LPFs, and a contour-enhanced hiteo signal is obtained.
第4図は中域の周波数帯において、なたらかにヒデオ信
号かI:、−!l′lする場合の木発]町の各部の波形
(実際はテシタル信号であるか、説明をわかりやずくす
る為、第3図、第4図、第5図についてはアナロタ信号
て表示している)を示している。Figure 4 shows that in the mid-range frequency band, the video signal is I:, -! Waveforms of various parts of the town (Actually, they are digital signals, but to make the explanation easier to understand, Figures 3, 4, and 5 are shown as analog signals. ) is shown.
第5図においては更に低い周波数域でのヒテオ信号か処
理される波形を示している。これらの図てわかる通り、
なたらかに変化する信号については輪郭強調は行わず、
画質をそこなう一°19はない。FIG. 5 shows a waveform in which the hiteo signal is processed in an even lower frequency range. As you can see from these figures,
Contour enhancement is not performed for signals that change smoothly,
There is no harm in image quality.
「発明の効果」
以」−説明したようにヒテオ信号をデジタル化した後、
現画素の値と]画素前の値との差分検出を行い演算処理
を行うことにより、低コス1−て、画像のライン間の相
関によらず高品質の輪郭強調かてきるという効果かある
。``Effects of the invention'' - After digitizing the hiteo signal as explained,
By detecting the difference between the value of the current pixel and the value of the previous pixel and performing arithmetic processing, it is possible to perform high-quality contour enhancement at a low cost, regardless of the correlation between lines of the image. .
第1図は本発明による輪郭強調回路の実施例第2図は非
線形変換テーブルの特性の一例第3図、第4図、第5図
に)本発明を説明する為の図である。
1は入力端子
2はローパス・フィルタ
3はアナログ/デシタル変換器
4は非線形変換テーブル
5はコントロール部
6は差分検出及びテータ処理回路
7は加算回路
8はリミッタ
9はデジタル/アナロタ変換器
10はローパスフィルタ
11は遅延回路である
訴4−図
Q′FIG. 1 shows an embodiment of an edge enhancement circuit according to the present invention. FIG. 2 shows an example of characteristics of a nonlinear conversion table (see FIGS. 3, 4, and 5) for explaining the present invention. 1 is an input terminal 2 is a low-pass filter 3 is an analog/digital converter 4 is a nonlinear conversion table 5 is a control section 6 is a difference detection and data processing circuit 7 is an addition circuit 8 is a limiter 9 is a digital/analog converter 10 is a low-pass The filter 11 is a delay circuit.
Claims (3)
値の差分値を検出する検出手段と、差分値が所定のスレ
ツシユホールドレベル以下又は極性が反転した場合にお
いて、 前差分値と同値で極性の反転したデータに置換するデー
タ処理回路とを含んだ輪郭強調回路。(1) A detection means for detecting a difference value between the current pixel value and the previous pixel value of a digital video signal, and when the difference value is less than a predetermined threshold level or the polarity is reversed, the detection means detects the difference value between the current pixel value and the previous pixel value, and a data processing circuit that replaces data with data of the same value and inverted polarity.
許請求の範囲第(1)項記載の輪郭強調回路。(2) The contour emphasizing circuit according to claim (1), further comprising a table for non-linearly converting the difference value.
ルにより、非線形の傾きのレベルを所望の値に変更の可
能なものであることを特徴とする特許請求の範囲第(1
)項記載の輪郭強調回路。(3) The nonlinear conversion table is capable of changing the level of the nonlinear slope to a desired value by external control.
Contour enhancement circuit described in ).
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2111964A JPH0410767A (en) | 1990-04-27 | 1990-04-27 | Contour emphasizing circuit |
DE69123780T DE69123780T2 (en) | 1990-04-27 | 1991-04-18 | Device for processing image signals to improve edge steepness |
EP91303461A EP0454355B1 (en) | 1990-04-27 | 1991-04-18 | Image signal processing apparatus for edge enhancement |
CA002040881A CA2040881C (en) | 1990-04-27 | 1991-04-19 | Image signal processing apparatus |
US08/414,572 US5696852A (en) | 1990-04-27 | 1995-03-31 | Image signal processing apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2111964A JPH0410767A (en) | 1990-04-27 | 1990-04-27 | Contour emphasizing circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0410767A true JPH0410767A (en) | 1992-01-14 |
Family
ID=14574555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2111964A Pending JPH0410767A (en) | 1990-04-27 | 1990-04-27 | Contour emphasizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0410767A (en) |
-
1990
- 1990-04-27 JP JP2111964A patent/JPH0410767A/en active Pending
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