JPH04106639A - Watch dog performing method for system using cpu - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a fatal accident in a system caused by the run-out-of-control of a CPU without using any IC for watch dog by making the CPU to make an illegal process by using the value of an internal counter in an interrupting process and setting the internal counter to its initial value at every ordinary processing cycle of the CPU. CONSTITUTION:An interrupting process is actuated by the interrupt of an internal (external) timer 12 and the value of a software timer set in a system RAM 13 is read. When the value of the software timer is not '0', the interrupting process is terminated by decreasing the value of the software timer. When the value of the software timer is '0', a CPU 11 terminates the interrupting process by performing an illegal process. In addition, the software timer is set to its initial value at every one cycle of a main processing routine. Therefore, the occurrence of a fatal accident in the system caused by the run-out-of- control of the CPU can be prevented without using any IC for watch dog.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of implementing a watchdog in a system using a CPU.

[Prior Art] FIG. 4 is a block diagram showing a conventional method of implementing a watchdog.

The CPU 41 has a watchdog timer (subtraction counter) 4
Connected to 2. Further, a clock CLK is input to each of the CPU 41 and the watchdog timer 42. The watchdog timer 42 decrements the timer value by 1 every clock.

Figure 5 shows a CP with a conventional watchdog implementation method.
FIG. 6 is a flowchart showing the main processing routine of the U system, and FIG. 6 is a flowchart showing interrupt processing. In the main processing routine, one cycle, that is, processing A,
A program is provided in which the watchdog timer 42 is set to an initial value each time B and C end (step 5.1). Now, if the count time of the watchdog timer is tl, and the maximum processing time of the main processing routine is t, then 1. , < 1. If the CPU 41 operates normally and the software processing is normal, the watchdog timer 42 has no effect on the CPU 41. However, if some abnormality occurs in the software processing, such as a runaway, the processing time of the main processing routine becomes longer and exceeds the count time of the watchdog timer 42. At this time, the value of the watchdog timer 42 becomes O, and the value of the watchdog timer 42 becomes O.
2 interrupts the CPU 41. In the interrupt processing, illegal processing (step 601) is performed. Here, illegal processing is a general term for processing that returns the CPU to normal operation, notifies the outside of the CPU, or stops the operation when an abnormality is detected.

[Problems to be Solved by the Invention] However, the conventional method described above always requires a watchdog IC, which has the problem of complicating the hardware configuration. Furthermore, when the watchdog timer is not used, there is a problem in that it is difficult to prevent a fatal system accident due to a runaway CPU.

The present invention has been made in view of the above problems, and is a CPU that can prevent fatal system accidents caused by CPU runaway without using a watchdog IC.
The purpose of this paper is to provide a method for implementing a watchdog in a system using U.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a system using a CPU that includes a CPU and a storage device, and includes: an interrupt means for generating an interrupt by an internal or external timer of the CPU; and the interrupt means. has an internal counter that is decremented by an interrupt caused by the interrupt, and in the interrupt processing caused by the interrupt, illegal processing of the CPU is performed according to the value of the internal counter, and the CPU
The present invention is characterized in that the internal counter is set to an initial value every cycle of normal processing of U.

[Action] By configuring the watchdog implementation method in a system using a CPU as described above, an internal counter is used as a watchdog timer, and when the value of the internal counter is not O during interrupt processing, the internal counter is decremented. However, when the value of the internal counter is O,
Performs illegal processing, and also executes main processing routine 1.
Since the internal counter is set to the initial value every cycle, the watchdog interface can be used as hardware.
This means that the watchdog can be implemented without using C.

[Example code] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing an embodiment of a system using a CPU having a watchdog implementation method according to the present invention.

The internal (external) timer is activated by CPUI 2 interrupt (INTI).
) terminal and interrupts the CPUI2 at regular intervals.

FIG. 2 is a flowchart showing interrupt processing of a system using a CPU according to the present invention. Interrupt processing is started by an internal (external) timer 120 interrupt, and reads the value of the software timer that has been set on the system RAM 13 (step 201). If the software timer value is not O, the software decrements the timer value (step 203) and ends the interrupt processing (
Step 204).

If the software timer value is 0, the CPU II
performs illegal processing (step 205) and ends the interrupt processing (step 206). Interrupt processing is repeated by periodic interrupts from the internal (external) timer 12.

FIG. 3 is a flowchart showing the main processing routine of a system using a CPU according to the present invention. A series of normal processes, e.g. processes A-C (steps 301-303)
When the software timer is finished, the value of the software timer is set to the initial value.
/Display processing is performed (step 304). Here, the initial value of the software timer is the count time of the software to, and the maximum processing time of the main processing routine t. This is a value that can be set so that to<t+. Note that the period of interrupt processing by the internal (external) timer 12 is a sufficiently small value compared to t, , t.

If the normal processing of -J (steps 301 to 303) is performed without error, the initial value is set to the software timer every cycle of the main processing routine, so the value of the software timer will never become 0. Therefore, illegal processing is not performed in interrupt processing and CP
Does not affect the operation of U11.

However, an error occurred in the main processing routine and CFULL
When the software timer goes out of control, the software timer is not set to its initial value and continues to be decremented during interrupt processing, so the timer value of the software timer becomes O. At this time, if there is an interrupt by the internal (external) timer 12, illegal processing is performed in the interrupt processing, and the CPU 11 is returned to a normal state. [Effects of the Invention] As described above, according to the present invention, In a system using a CPU, an internal counter is used as a watchdog timer, and when the internal counter value is not O during interrupt processing, the internal counter is decremented, and when the internal counter value is 0, illegal processing is performed. In addition, since the software timer is structured to be set to the initial value every cycle of the main processing routine, the watchdog can be implemented with a simple circuit configuration without using a watchdog IC as hardware. Effects can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a system using a CPU having a watchdog implementation method according to the present invention, FIG. 2 is a flowchart showing interrupt processing of a system using a CPU according to the present invention, Figure 3 shows C according to the present invention.
A flowchart showing the main processing routine of a system using a PU, Fig. 4 is a block diagram showing a conventional method of implementing a watchdog, and Fig. 5 shows a main processing of a system using a CPU having a conventional method of implementing a watchdog. A flowchart showing the routine, and FIG. 6 is a flowchart showing interrupt processing. In the figure, 11...CPU, 12...Internal (external) timer, 13...System RAM. JJ! aQt・Too・) Yasu・/Teto/'7 Rihai i
Nohe゛♂λ・No. Fukuchi・7n Patent applicant Oki Electric Industry Co., Ltd. Representative Patent attorney Takashi Kumagai (1 other person) End kidney? tl) Kan 19 snoring ff1. Figure 2 Tree 9Ev4 (: Assignment menu iO, η) p+
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Claims (1)

[Scope of Claims] A system using a CPU comprising a CPU and a storage device, comprising an interrupt means for generating an interrupt by an internal or external timer of the CPU, and an internal counter that is decremented by an interrupt by the interrupt means, In interrupt processing due to an interrupt, CPU illegal processing is performed according to the value of the internal counter, and the CPU
A method for implementing a watchdog in a system using a CPU, characterized in that the internal counter is set to an initial value every cycle of normal processing of U.