JPH04106532A - Liquid crystal display device - Google Patents
Liquid crystal display deviceInfo
- Publication number
- JPH04106532A JPH04106532A JP2224741A JP22474190A JPH04106532A JP H04106532 A JPH04106532 A JP H04106532A JP 2224741 A JP2224741 A JP 2224741A JP 22474190 A JP22474190 A JP 22474190A JP H04106532 A JPH04106532 A JP H04106532A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- signal line
- semiconductor thin
- liquid crystal
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 13
- 239000010409 thin film Substances 0.000 claims abstract description 53
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 239000010408 film Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 claims description 5
- 230000007547 defect Effects 0.000 abstract description 4
- 230000012447 hatching Effects 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は液晶表示装置に係わり、特にアクティブマトリ
クス型の装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a liquid crystal display device, and particularly to an active matrix type device.
（従来の技術）
従来のアクティブマトリクス型の液晶表示装置として、
「日経エレクトロニクス１９８４年９月１０日号、９．
２１１−２４０Ｊに掲載されたものがある。第６図に、
その一画素分の構成を示す。(Conventional technology) As a conventional active matrix type liquid crystal display device,
“Nikkei Electronics September 10, 1984 issue, 9.
There is one published in 211-240J. In Figure 6,
The configuration of one pixel is shown.
列方向に信号線１３が配線され、行方向に走査線１２が
配線されている。信号線１３と走査線１２との交点には
薄膜トランジスタ（以下、ＴＦＴと称する）１４が配置
され、またマトリクス状に画素電極１１が形成されてい
る。そして、ＴＦＴ１４と信号線１３とはコンタクトホ
ール１５において接続され、ＴＦＴ１４と画素電極１１
とはコンタクトホール１６において接続されている。Signal lines 13 are wired in the column direction, and scanning lines 12 are wired in the row direction. A thin film transistor (hereinafter referred to as TFT) 14 is arranged at the intersection of the signal line 13 and the scanning line 12, and pixel electrodes 11 are formed in a matrix. The TFT 14 and the signal line 13 are connected through the contact hole 15, and the TFT 14 and the pixel electrode 11 are connected to each other through the contact hole 15.
and are connected through a contact hole 16.
この第６図のＤ−Ｄ線に沿う縦断面は、第７図に示され
るようである。ＴＰＴ基板２１の表面にＴＦＴ１４のソ
ース部２２、走査線１２が形成され、層間絶縁膜２４を
介して信号線１３か形成されている。ソース部２２の表
面には、図示されていないゲート電極との間に設けるゲ
ート絶縁膜２３か形成されており、コンタクトホール１
５が開孔されて信号線１３とソース部２２とが接続され
ている。A longitudinal section taken along line DD in FIG. 6 is as shown in FIG. 7. A source portion 22 of a TFT 14 and a scanning line 12 are formed on the surface of a TPT substrate 21, and a signal line 13 is formed via an interlayer insulating film 24. A gate insulating film 23 is formed on the surface of the source part 22 to be provided between it and a gate electrode (not shown), and a contact hole 1 is formed on the surface of the source part 22.
5 is opened to connect the signal line 13 and the source section 22.
第６図のＥ−Ｅ線に沿う縦断面は第８図のようである。A longitudinal section taken along line E-E in FIG. 6 is as shown in FIG. 8.
ＴＰＴ基板２１の表面に、半導体薄膜から成るソース部
２２、チャネル部３２およびドレイン部３３が形成され
、さらにチャネル部３２の上部には、ゲート絶縁膜２３
を介してゲート電極１２が形成されている。層間絶縁膜
２４を介して形成された画素電極１１が、コンタクトホ
ール１６においてドレイン部３３に接続されており、信
号線１３がコンタクトホール１５においてソース部２２
に接続されている。A source part 22, a channel part 32, and a drain part 33 made of semiconductor thin films are formed on the surface of the TPT substrate 21, and a gate insulating film 23 is formed on the upper part of the channel part 32.
A gate electrode 12 is formed through the gate electrode. The pixel electrode 11 formed through the interlayer insulating film 24 is connected to the drain part 33 in the contact hole 16, and the signal line 13 is connected to the source part 22 in the contact hole 15.
It is connected to the.
（発明が解決しようとする課題）
しかしこのような構成を有する従来の装置には、信号線
１３上に断線が発生しやすく、線欠陥を生じやすいとい
う問題があった。信号線を多層化することて防止するこ
とも考えられるか、信号線の基本的な構造には変化がな
く、断線を有効に防止することはできなかった。(Problems to be Solved by the Invention) However, the conventional device having such a configuration has a problem in that disconnections are likely to occur on the signal line 13 and line defects are likely to occur. It may be possible to prevent this by making the signal lines multi-layered, but there is no change in the basic structure of the signal lines, and it has not been possible to effectively prevent disconnections.
本発明は上記事情に鑑みてなされたものであり、信号線
の断線を防止し、歩留まりの向上及びコスト低減を達成
し得る液晶表示装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a liquid crystal display device that can prevent disconnection of signal lines, improve yields, and reduce costs.
（課題を解決するための手段）
本発明の液晶表示装置は、第１の絶縁基板上に複数の走
査線と信号線とが配置され、走査線により走査され信号
線により信号を入力される薄膜トランジスタが走査線と
信号線との交点にマトリクス状に配置され、第１の絶縁
基板に対向して設けられ対向電極が配置された第２の絶
縁基板との間に液晶が挟持された装置であって、薄膜ト
ランジスタと信号線との各々の接続部分が、半導体薄膜
によって相互に接続されていることを特徴としている。(Means for Solving the Problems) A liquid crystal display device of the present invention includes a thin film transistor in which a plurality of scanning lines and signal lines are arranged on a first insulating substrate, and a thin film transistor is scanned by the scanning lines and inputted with a signal by the signal line. are arranged in a matrix at the intersections of scanning lines and signal lines, and a liquid crystal is sandwiched between a second insulating substrate facing the first insulating substrate and having a counter electrode arranged thereon. The thin film transistor and the signal line are connected to each other by a semiconductor thin film.
ここで、薄膜トランジスタと画素電極との各々の接続部
分の半導体薄膜が前段の走査線と絶縁膜を介して重なり
合い、容量が形成されていてもよい。Here, the semiconductor thin film at each connecting portion between the thin film transistor and the pixel electrode may overlap with the preceding scanning line via an insulating film, thereby forming a capacitor.
（作 用）
薄膜トランジスタと信号線との各接続部分が、半導体薄
膜によって相互に接続されているため、信号線に断線が
発生しても接続が確保され、信号線としての機能が維持
される。(Function) Since the connection parts between the thin film transistor and the signal line are mutually connected by the semiconductor thin film, even if a disconnection occurs in the signal line, the connection is ensured and the function as a signal line is maintained.
また、薄膜トランジスタと画素電極との各接続部分の半
導体薄膜が、前段の走査線と絶縁膜を介して重なり合う
場合には保持容量となり、開孔率の減少を抑制しつつ、
ＴＰＴの保持動作を改善することができる。In addition, when the semiconductor thin film at each connection portion between the thin film transistor and the pixel electrode overlaps the previous scanning line via the insulating film, it becomes a storage capacitor, suppressing the decrease in the aperture ratio.
The holding operation of TPT can be improved.
（実施例）
以下、本発明の一実施例について図面を参照して説明す
る。第１図は、本発明の第１の実施例による液晶表示装
置の平面構造を示したものである。(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a planar structure of a liquid crystal display device according to a first embodiment of the present invention.
この実施例では、ＴＰＴはセルフ・アライン構造により
形成されている。In this embodiment, the TPT is formed by a self-aligned structure.
第６図に示された従来の装置と比較しＴＦＴ１４のソー
ス部同志が、ハツチングの施された半導体薄膜１７によ
って信号線１３と平行に接続されている点が異なってい
る。この第１図のＡ−Ａ線に沿う縦断面を第２図に示す
。ＴＰＴ基板２１とソース部２２との間に半導体薄膜１
７が形成されており、ソース部２２同志が相互に電気的
に接続されている。これに伴い、走査線１２と半導体薄
膜１７とを電気的に絶縁する必要が生じ、ゲート絶縁膜
２３が間に形成されている。This device differs from the conventional device shown in FIG. 6 in that the source portions of the TFTs 14 are connected in parallel to the signal line 13 by a semiconductor thin film 17 with hatching. FIG. 2 shows a longitudinal section taken along line A--A in FIG. 1. A semiconductor thin film 1 is placed between the TPT substrate 21 and the source section 22.
7 is formed, and the source portions 22 are electrically connected to each other. Accordingly, it becomes necessary to electrically insulate the scanning line 12 and the semiconductor thin film 17, and a gate insulating film 23 is formed therebetween.
さらに、第１図のＢ−Ｂ線に沿う縦断面を第３図に示す
。これは、ＴＦＴ１４がセルフ滲アライン構造の場合に
相当する。第８図に示された従来の装置と同様に、ソー
ス部２２、チャネル部３２及びドレイン部３３が一体の
半導体薄膜に形成されているが、ＴＰＴ基板２１とソー
ス部２２との間に半導体薄膜１７が形成され、同様にド
レイン部３３との間に半導体薄膜１８が形成されている
。Further, FIG. 3 shows a longitudinal section taken along the line B--B in FIG. 1. This corresponds to the case where the TFT 14 has a self-bleed alignment structure. Similar to the conventional device shown in FIG. 17 is formed, and a semiconductor thin film 18 is similarly formed between it and the drain part 33.
このように、信号線１３に断線が生じた場合にもソース
部２２同志が半導体薄膜１７によって接続されている。In this way, even if a disconnection occurs in the signal line 13, the source parts 22 are connected to each other by the semiconductor thin film 17.
この半導体薄膜１７は、信号線１３との間にゲート絶縁
膜２３と層間絶縁膜２４とをはさんで、独立した配線パ
ターンで形成されていることを考慮すると、信号線１３
が断線している同一箇所において半導体薄膜１７までが
断線する確率は極めて小さく、無視することができる。Considering that this semiconductor thin film 17 is formed in an independent wiring pattern with a gate insulating film 23 and an interlayer insulating film 24 sandwiched between it and the signal line 13, it is assumed that the signal line 13
The probability that the semiconductor thin film 17 will be disconnected at the same location where the semiconductor thin film 17 is disconnected is extremely small and can be ignored.
これにより、信号線１３に欠陥が生じても救済が可能で
、歩留まりが向上する。Thereby, even if a defect occurs in the signal line 13, it can be repaired, and the yield can be improved.
一般に、チャネル部３２の半導体薄膜の膜厚を薄くする
と、ＴＦＴＩ４のオン時のインピーダンスが低く、オフ
時のインピーダンスが高くなって、伝達特性が向上する
。しかし、第８図に示された従来の装置においてチャネ
ル部３２の膜厚を薄くすると、必然的にソース部２２及
びドレイン部３３の膜厚も薄くなり、信号線１３及び画
素電極１１とのコンタクト抵抗が高くなるという問題が
生じる。これに対し本実施例では、ソース部２２及びド
レイン部３３の膜厚が薄くとも半導体薄膜１７及び１８
が積層されており、コンタクト抵抗を小さくすることが
できるため、チャネル部３２の膜厚を薄くして伝達特性
を改善することが可能である。Generally, when the thickness of the semiconductor thin film of the channel portion 32 is reduced, the impedance when the TFTI 4 is on is low, and the impedance when the TFTI 4 is off is high, and the transfer characteristics are improved. However, in the conventional device shown in FIG. 8, if the thickness of the channel portion 32 is made thinner, the thickness of the source portion 22 and the drain portion 33 will also be made thinner, and the contact with the signal line 13 and the pixel electrode 11 will be reduced. A problem arises in that the resistance becomes high. On the other hand, in this embodiment, even if the film thickness of the source part 22 and the drain part 33 is thin, the semiconductor thin films 17 and 18
are stacked, and the contact resistance can be reduced, so it is possible to reduce the film thickness of the channel portion 32 and improve the transmission characteristics.
ここでソース部２２の抵抗は高いが、一画素分のソース
部２２同志を接続する上で、選択時間内にビデオ信号を
印加するという信号線としての機能は十分に果たすこと
かできる。Although the resistance of the source section 22 is high, it can sufficiently function as a signal line for connecting the source sections 22 for one pixel and applying a video signal within a selected time.
この第１の実施例のように、ＴＦＴＩ４がセルフ・アラ
イン構造の場合には、インピーダンスが高いチャネル部
３２とソース部２２とが一体をなし、同一の半導体薄膜
より成っている。従って、ソース部２２同志を接続する
には、本実施例のようにこの半導体薄膜とは別に不純物
濃度の高い半導体薄膜１７を追加するか、あるいは延長
した半導体薄膜に不純物イオンを注入して低抵抗化する
必要がある。When the TFTI 4 has a self-aligned structure as in the first embodiment, the channel section 32 and the source section 22, which have high impedance, are integrated and made of the same semiconductor thin film. Therefore, in order to connect the source parts 22, it is necessary to add a semiconductor thin film 17 with a high impurity concentration in addition to this semiconductor thin film as in this embodiment, or to implant impurity ions into the extended semiconductor thin film to reduce the resistance. It is necessary to
前者の場合には、半導体薄膜１７を形成するための堆積
工程やパターニング工程が必要となり、後者の構造では
不純物イオンを注入する工程が増えることになる。In the former case, a deposition process and a patterning process are required to form the semiconductor thin film 17, whereas in the latter structure, the process of implanting impurity ions is increased.
第４図に、本発明の第２の実施例による液晶表示装置の
平面構造を示す。この実施例では、第１の実施例同様に
ＴＦＴＩ４のソース部同志が半導体薄膜１７で接続され
ているか、さらにドレインと画素電極１１との接続部の
半導体薄膜４１が延長されて、前段の信号線１２とゲー
ト絶縁膜を介して重なり合っている点に特徴がある。こ
の信号線１２と半導体薄膜４１が重なり合った領域には
、保持容量が形成される。ドレインと画素電極１１との
間に保持容量を形成すると、ＴＦＴＩ４の各電極間に存
在する寄生容量の影響で、ＴＦＴＩがオフする瞬間に生
じるオフセット電圧が減少し保持特性や画質の向上がも
たらされるが、一般に画素電極１１の開孔率の低下を招
く。これに対し、本実施例のように半導体薄膜４１を延
長して形成することにより、開孔率を殆ど減少させるこ
となく十分な保持容量を形成することができる。FIG. 4 shows a planar structure of a liquid crystal display device according to a second embodiment of the present invention. In this embodiment, as in the first embodiment, the source parts of the TFTIs 4 are connected to each other by the semiconductor thin film 17, or the semiconductor thin film 41 at the connection part between the drain and the pixel electrode 11 is extended, and the signal line of the previous stage is It is characterized in that it overlaps with 12 with the gate insulating film interposed therebetween. A storage capacitor is formed in the region where the signal line 12 and the semiconductor thin film 41 overlap. When a storage capacitor is formed between the drain and the pixel electrode 11, the offset voltage generated at the moment the TFTI is turned off due to the influence of the parasitic capacitance existing between each electrode of the TFTI 4 is reduced, resulting in improvements in retention characteristics and image quality. However, this generally causes a decrease in the aperture ratio of the pixel electrode 11. On the other hand, by forming the semiconductor thin film 41 in an extended manner as in this embodiment, a sufficient storage capacity can be formed without substantially reducing the porosity.
また、ＴＦＴをノン・セルファライン構造で形成する場
合にも、本発明の適用は可能である。この場合の装置を
、第３の実施例として縦断面構造を第５図に示す。第３
図に示された第１の実施例では、ゲート電極１２をマス
クとして一体の半導体薄膜のソース部２２とドレイン部
３３とに不純物イオンを注入しているが、本実施例では
ソース部５２、ドレイン部５３とチャネル部５４とを別
にパターニングして形成している。他の第１の実施例と
同様な構成要素には、同一の番号を付して説明を省略す
る。この場合には、ソース部５２の半導体薄膜が直接延
長されて、信号線１３と平行に各ソース部同志を接続し
ている。従って第１の実施例のように、ソース部２２の
下部に別に半導体薄膜１７を形成する必要がなく、半導
体薄膜の堆積及びパターニングの工程が不要となる。Further, the present invention can also be applied when forming a TFT with a non-self-line structure. The vertical cross-sectional structure of the device in this case is shown in FIG. 5 as a third embodiment. Third
In the first embodiment shown in the figure, impurity ions are implanted into the source part 22 and drain part 33 of an integrated semiconductor thin film using the gate electrode 12 as a mask. The portion 53 and the channel portion 54 are formed by patterning separately. Other components similar to those in the first embodiment are given the same numbers and their explanations will be omitted. In this case, the semiconductor thin film of the source section 52 is directly extended to connect the source sections in parallel with the signal line 13. Therefore, unlike the first embodiment, there is no need to separately form the semiconductor thin film 17 under the source section 22, and the steps of depositing and patterning the semiconductor thin film are not necessary.
上述した実施例はいずれも一例であって、本発明を限定
するものではない。半導体薄膜によりソース部同志が信
号線に平行に接続されていればよく、その接続構造はＴ
ＰＴの形成法によっても異なり、実施例と別構造のもの
であってもよい。The embodiments described above are merely examples and do not limit the present invention. It is sufficient that the source parts are connected in parallel to the signal line by a semiconductor thin film, and the connection structure is T.
It varies depending on the method of forming PT, and may have a different structure from the example.
以上説明したように本発明の液晶表示装置によれば、薄
膜トランジスタと信号線との各接続部分が半導体薄膜に
よって相互に接続されているため、信号線に断線が発生
しても接続か確保されて自動的に線欠陥が救済され、歩
留まりの向上及びコスト低減が達成される。また薄膜ト
ランジスタと画素電極との各接続部分の半導体薄膜が、
前段の走査線と絶縁膜を介して重なり合う場合には、開
孔率をあまり減少させることなく保持容量を得ることが
でき、ＴＰＴの保持動作が改善されて高画質化が可能と
なる。As explained above, according to the liquid crystal display device of the present invention, since the connection parts between the thin film transistor and the signal line are mutually connected by the semiconductor thin film, the connection is maintained even if a disconnection occurs in the signal line. Line defects are automatically repaired, yield improvement and cost reduction are achieved. In addition, the semiconductor thin film at each connection part between the thin film transistor and the pixel electrode is
When overlapping with the previous scanning line via an insulating film, a storage capacity can be obtained without reducing the porosity much, and the holding operation of the TPT is improved, making it possible to achieve high image quality.
図である。It is a diagram.
１１・・・画素電極、１２・・・走査線、１３・・・信
号線、１４・・・ＴＰＴ、１５．１６・・・コンタクト
ホール、１７．１８．４１・・・半導体薄膜、２１．５
１・・・ＴＰＴ基板、２２．５２・・・ソース部、２３
・・・ゲート絶縁膜、２４・・・層間絶縁膜、３２．５
４・・・チャネル部、３３．５３・・・ドレイン部、５
６・・・ゲート電極。11... Pixel electrode, 12... Scanning line, 13... Signal line, 14... TPT, 15.16... Contact hole, 17.18.41... Semiconductor thin film, 21.5
1... TPT substrate, 22.52... Source part, 23
... Gate insulating film, 24... Interlayer insulating film, 32.5
4...Channel part, 33.53...Drain part, 5
6...Gate electrode.
Claims (1)
され、前記走査線により走査され前記信号線により信号
を入力される薄膜トランジスタが前記走査線と前記信号
線との交点にマトリクス状に配置され、前記第１の絶縁
基板に対向して設けられ対向電極が配置された第２の絶
縁基板との間に液晶が挟持された液晶表示装置において
、前記薄膜トランジスタと前記信号線との各々の接続部
分が、半導体薄膜によって相互に接続されていることを
特徴とする液晶表示装置。 ２、前記薄膜トランジスタと前記画素電極との各々の接
続部分の半導体薄膜が前段の走査線と絶縁膜を介して重
なり合い、容量が形成されていることを特徴とする請求
項１記載の液晶表示装置。[Claims] 1. A plurality of scanning lines and a plurality of signal lines are arranged on a first insulating substrate, and a thin film transistor scanned by the scanning line and inputting a signal by the signal line is connected to the scanning line and the signal line. A liquid crystal display device in which a liquid crystal is sandwiched between a second insulating substrate that is arranged in a matrix at intersections with lines and that is provided opposite to the first insulating substrate and has a counter electrode arranged thereon, the thin film transistor A liquid crystal display device characterized in that respective connecting portions of the signal line and the signal line are connected to each other by a semiconductor thin film. 2. The liquid crystal display device according to claim 1, wherein the semiconductor thin film at each connection portion between the thin film transistor and the pixel electrode overlaps the preceding scanning line via an insulating film to form a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474190A JP3044762B2 (en) | 1990-08-27 | 1990-08-27 | Liquid crystal display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22474190A JP3044762B2 (en) | 1990-08-27 | 1990-08-27 | Liquid crystal display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04106532A true JPH04106532A (en) | 1992-04-08 |
| JP3044762B2 JP3044762B2 (en) | 2000-05-22 |
Family
ID=16818513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22474190A Expired - Fee Related JP3044762B2 (en) | 1990-08-27 | 1990-08-27 | Liquid crystal display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3044762B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5546204A (en) * | 1994-05-26 | 1996-08-13 | Honeywell Inc. | TFT matrix liquid crystal device having data source lines and drain means of etched and doped single crystal silicon |
| US5867242A (en) * | 1994-04-28 | 1999-02-02 | Xerox Corporation | Electrically isolated pixel element in a low voltage activated active matrix liquid crystal display and method |
| JP2008224806A (en) * | 2007-03-09 | 2008-09-25 | Mitsubishi Electric Corp | Display device and manufacturing method thereof |
| JP2009122256A (en) * | 2007-11-13 | 2009-06-04 | Seiko Epson Corp | Electro-optical device and electronic equipment |
| JP2013037126A (en) * | 2011-08-05 | 2013-02-21 | Japan Display Central Co Ltd | Liquid crystal display device |
| US9752630B2 (en) | 2014-09-09 | 2017-09-05 | Kawasaki Jukogyo Kabushiki Kaisha | Centrifugal clutch |
-
1990
- 1990-08-27 JP JP22474190A patent/JP3044762B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5867242A (en) * | 1994-04-28 | 1999-02-02 | Xerox Corporation | Electrically isolated pixel element in a low voltage activated active matrix liquid crystal display and method |
| US5546204A (en) * | 1994-05-26 | 1996-08-13 | Honeywell Inc. | TFT matrix liquid crystal device having data source lines and drain means of etched and doped single crystal silicon |
| JP2008224806A (en) * | 2007-03-09 | 2008-09-25 | Mitsubishi Electric Corp | Display device and manufacturing method thereof |
| JP2009122256A (en) * | 2007-11-13 | 2009-06-04 | Seiko Epson Corp | Electro-optical device and electronic equipment |
| JP2013037126A (en) * | 2011-08-05 | 2013-02-21 | Japan Display Central Co Ltd | Liquid crystal display device |
| US9752630B2 (en) | 2014-09-09 | 2017-09-05 | Kawasaki Jukogyo Kabushiki Kaisha | Centrifugal clutch |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3044762B2 (en) | 2000-05-22 |
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