JPH04105724U - Square wave doubler circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Convert a square wave input signal to a square wave with twice the frequency. [Structure] The variable delay circuit 2 delays the square wave input signal 1 with a period T by a time t using the output 7 of the duty ratio detection circuit 6. The exclusive OR gate 4 inverts the output 5 when the logic level of either one of the two inputs 1 and 3 changes exclusively. The duty ratio detection circuit 6 feeds back a control signal 7 corresponding to the duty ratio of the output 5 to the variable delay circuit 2 to control the delay time to t=T/4. Therefore,
The output 5 of the gate 4 is a square wave whose frequency is twice that of the input signal. [Effect] A square wave with a duty ratio of exactly 50% and twice the frequency can be created with a simple circuit.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

This idea is a square wave doubler that inputs a square wave and converts it into a square wave with twice the frequency. Regarding circuits.

0002

[Conventional technology]

In a digital circuit, a rectangular wave of frequency f is input, and frequencies f/2, f/ Frequency dividing circuits that convert into rectangular waves of 3, . . . are often used. Also, on the contrary , a rectangular wave with a duty ratio of 50% (%) at a frequency f, that is, a square wave with a frequency of A doubling circuit is used to convert the signal into a 2f rectangular wave.

0003 FIG. 3 shows an example of a conventional doubler circuit.

0004 In Figure 3 (A), 1 is an input signal, which is cycled as shown in Figure 3 (B). It is a square wave with period T. 31 is a delay circuit with a delay time t0 (<T/2). 32 is an exclusive OR (hereinafter abbreviated as XOR) gate, and 33 is an output signal.

[0005] The operation of the doubler circuit shown in FIG. 3(A) is as follows. Square wave input signal with period T No. 1 is input to one input terminal of the delay circuit 31 and the XOR gate 32. delay circuit 31 is a square wave delayed by the delay time t0 from the input signal 1, and the XOR gate 32 and other output to the other input terminal.

[0006] The XOR gate 32 performs the exclusive OR of the input signal 1 and the output signal of the delay circuit 31. The output signal 33 is taken as the output signal 33. The output signal 33 becomes a rectangular wave with a period of T/2, and has a period of T/2. The frequency is doubled with respect to the square wave input signal 1. Here, XOR gate 32 occurs only when the logic level of one of the two input signals changes exclusively. It operates as a transition detection circuit that inverts the output level.

[0007] Note that the delay time t0 in the delay circuit 31 is determined by, for example, a capacitor, as is well known. This can be easily realized using a CR delay circuit that combines C and a resistor R (both not shown). Wear.

[0008]

[Problem that the idea aims to solve]

In a digital circuit, for example, a drive circuit such as a piezoelectric buzzer, a square wave of frequency f is used. Double the input signal to create a square wave with a frequency of 2f, that is, a square wave with a duty ratio of 50%. There are cases where you want to do this.

[0009] However, the output signal of the conventional doubler circuit described above is a rectangular signal whose frequency is doubled. It is a shaped wave, and the duty ratio t0/2T is generally not 50%. CR delay time If the CR constant of the road is adjusted each time and the delay time t0=T/4, the duty ratio is It seems possible to realize a 50% doubler circuit (hereinafter referred to as a square wave doubler circuit). Ru. However, the output signal from a square wave doubler circuit with such a simple configuration can vary widely. Due to these factors, the duty ratio fluctuates greatly. Furthermore, if the frequencies of the square wave input signals are If not, set the duty ratio to 50% for all output signals. I can't.

0010 Therefore, this device can maintain the duty ratio even when the frequencies of the square wave input signals are different. This paper proposes a simple square wave doubler circuit that can reliably obtain a 50% output signal. Ru.

[0011]

[Means to solve the problem]

The square wave doubler circuit according to this invention is controlled by a feedback signal and receives a square wave input. A variable delay circuit that delays the signal, and a square wave input signal and the output of the variable delay circuit. input, and inverts the output level only when one of the logic levels changes exclusively. A transition detection circuit that doubles the frequency of a square wave input signal, and a transition detection circuit that doubles the frequency of a square wave input signal. Detects the duty ratio of the double output signal and sends it as a delay control signal to the variable delay circuit. and a duty ratio detection circuit that provides feedback.

0012

[Effect]

In this invention, as shown in FIG. 1, the variable delay circuit 2 includes a duty ratio detection circuit. The square wave input signal 1 is delayed by the output signal 7 of the line 6. Square wave input signal 1 and There are two exclusive OR gates 4 which receive the delay output 3 from the variable delay circuit 2 as input. The output is output only when the logic level of one of the input signals changes exclusively. The level is inverted and output signal 5 is obtained. The duty ratio detection circuit 6 is an exclusive OR gate. The output signal 5 of output 4 is input, and the output signal 7 proportional to the duty ratio is input to the variable delay It is fed back to the extension circuit 2 and controlled so that the duty ratio of the output signal 5 is 50%. .

[0013]

【Example】

Next, an embodiment of the square wave doubler circuit according to this invention will be explained in detail with reference to the drawings. Explain in detail.

[0014] FIG. 1 is a block diagram showing an embodiment of this invention, where 1 indicates the period T, the duty ratio 50% square wave input signal, 2 is variable delay circuit, 3 is delayed output from variable delay circuit 2 4 is an exclusive OR gate, 5 is an output signal with period T/2, and 6 is the output signal of output signal 5. A duty ratio that detects the duty ratio and returns the delay control signal 7 to the variable delay circuit 2. This is a ratio detection circuit.

[0015] In addition, 11, 12, and 13 are inverters (NOT gates), and 14 and 15 are detection circuits. 16 are differential amplifiers, which constitute the duty ratio detection circuit 6.

[0016] The variable delay circuit 2 receives the square wave input signal 1 with a period T and delays it by a time t. Outputs a shape wave signal 3. Exclusive OR (XOR) gate 4 receives square wave input signal 1 and The delayed square wave signal 3 is input, and the logic level of one of the input signals is exclusive. The output level is inverted only when there is a change. Therefore, the output signal of XOR gate 4 5 has a period of T/2 and a duty ratio of t/2T.

[0017] The detection circuit 14 inputs the output signal 5 via the NOT gates 11 and 12, and outputs the output signal. A DC signal V1 proportional to the duty ratio t/2T of No. 5 is output. On the other hand, the detection time The path 15 inputs the inverted signal of the output signal 5 via the NOT gate 13, and outputs the output signal. A DC signal V2 proportional to the off time rate (1-t/2T) of 5 is output. differential amplification The device 16 subtracts V2 from the DC signal V1 and outputs the result as a delay control signal 7.

[0018] Therefore, the delay control signal 7 fed back to the variable delay circuit 2 is V1-V2=2(t /2T-0.5), and subtract 50% from the duty ratio t/2T of output signal 5. It will be proportional to the difference. That is, the duty ratio of the output signal 5 is t/2T< 50% is negative polarity, t/2T=50% is zero, and t/2T>50% is positive polarity. The return signal becomes 7.

[0019] The variable delay circuit 2 increases the delay time t when the delay control signal 7 has negative polarity, and increases the delay time t when the delay control signal 7 has negative polarity. If so, it is configured to reduce the delay time t. Therefore, output signal 5 has a duty The doubler circuit is balanced when the ratio is 50%, ie, a double square wave. Also , as is clear from the above explanation, when the period T of the square wave input signal 1 changes, Also, the delay time t of the variable delay circuit 2 is controlled by the feedback signal 7 so that it becomes T/4. A double square wave with a duty ratio of 50% can be obtained as the output signal 5. .

[0020] Note that the signal delay time t can be increased or decreased by using, for example, a CR provided in the variable delay circuit 2. This is done by automatically controlling the CR constant of the delay circuit (not shown) using the feedback signal 7. This is a well-known prior art, and its explanation will be omitted.

[0021] FIG. 2 is a waveform diagram showing various signals of this embodiment. FIG. 2(A) shows the delay time t< Indicates an overwave state of T/4, and the duty ratio of output signal 5 is t/2T<50%. , the outputs of the detection circuits 14 and 15 become V1<V2, and the delay time t is controlled in the extending direction. be done.

[0022] FIG. 2(B) shows that the delay time t of the output signal 5 is controlled as a result of the control of the delay time t in FIG. 2(A). It shows an equilibrium state with a ratio of 50%. In other words, the delay time t=T/4, and the detection The outputs of the wave circuits 14 and 15 become V1=V2, and the feedback signal 7 becomes zero, resulting in a balanced state. It becomes a state.

[0023] In this example, the purpose of outputting a double square wave was described, but the detection The DC outputs V1 and V2 of circuits 14 and 15 are connected to a differential amplifier via an appropriate weighting circuit. 16 to output a double square wave with an arbitrary duty ratio. You may.

[0024]

[Effect of the idea]

As mentioned above, according to the square wave doubler circuit according to this invention, the square wave of frequency f can be converted into a square wave with a frequency of 2f and a duty ratio of exactly 50%, so the conventional Compared to the case where only a frequency divider is used, the design of the digital circuit is easier. In addition, by using the appropriate frequency divider circuit and multiplier circuit in the appropriate place, the device can be improved. The configuration of the digital circuit becomes simpler.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a doubler circuit according to the invention.

FIG. 2 is a waveform diagram showing the operation of the circuit.

FIG. 3 is a block diagram showing a conventional doubling circuit.

[Explanation of symbols]

1 Square wave input signal 2 Variable delay circuit 3 Delayed square wave signal 4 Exclusive OR (XOR) gate 5 Square wave double output signal 6 Duty ratio detection circuit 7 Delay control signal 11, 12, 13 Inverter (NOT gate) 14, 15 Detection circuit 16 Differential amplifier

Claims (1)

[Scope of utility model registration request] 1. A variable delay circuit that is controlled by a feedback signal and delays a square wave input signal; the square wave input signal and the output of the variable delay circuit are input, and the logic level of either one is changed exclusively. A transition detection circuit inverts the output level only when the frequency of the square wave input signal is doubled, and detects the duty ratio of the doubled output signal from the transition detection circuit and returns it to the variable delay circuit as a delay control signal. A square wave 2 characterized in that it has a duty ratio detection circuit that converts a square wave input signal into a square wave with a double frequency.
Multiplier circuit.