JPH04105190A - Voltage detecting circuit and ic card provided with same - Google Patents

Abstract

PURPOSE:To execute the setting of detecting voltage to have arbitrary temperature characteristic and value by providing a comparing circuit to compare reference voltage generated in a reference voltage circuit and divided voltage generated in a voltage dividing circuit. CONSTITUTION:Reference voltage VREF obtained in a reference voltage circuit 4 and divided voltage VDIV obtained in a voltage dividing circuit 7 are supplied to the non-inversion input terminal (+) and the inversion input terminal (-) of a comparing circuit (voltage comparator) 8 respectively. The voltage comparator 8 generates a logical signal to correspond to the scale relation of the both input voltage, moreover, the logical output of the voltage comparator 8 is inverted by an inverter 9 and is outputted as a detecting signal VH. Thus, the setting of detecting voltage to have arbitrary temperature characteristic and value can be executed.

Description

[Detailed Description of the Invention] [Objective of the Invention (Industrial Application Field) This invention relates to a voltage detection circuit built into an integrated circuit,
In particular, the present invention relates to a voltage detection circuit suitable for detecting power supply voltage in IC cards and the like.

(Prior Art) Generally, integrated circuits driven by batteries often include a built-in voltage detection circuit. The reason for this is that if the power supply voltage falls below a certain reference voltage, the integrated circuit may malfunction. Therefore, it is necessary to use a voltage detection circuit to detect that the power supply voltage has fallen below a reference voltage, and use this detection output to perform control such as stopping the operation of the integrated circuit.

FIG. 16 shows a conventional reference voltage circuit that forms the reference voltage used in the voltage detection circuit. This reference voltage circuit is described in the document rIEEE JOURNAL OF 5O.
LID-8TATE CIRCUIT, VOL, 5C
-14,N0,3. rA CMO8Ban described on pages 655 to 657 of JUNE1979J
dgap Voltage ReferenceJ
This reference voltage circuit is shown in FIG. 1, and this reference voltage circuit will be briefly explained below. This circuit generates a predetermined reference current in a constant current circuit consisting of four MOS transistors T1 to T4 and one resistance element R1, and a constant voltage obtained by flowing the reference current in this constant current circuit. By supplying as a gate bias to the MOS transistor T6, a constant current proportional to the reference current generated in the constant current circuit is supplied to the MOS transistor T6.
6 and is further connected in series with the reference resistance element R2.
and diode-connected bipolar transistor T5
By passing this constant current through, a reference voltage is formed by the sum of the voltage drop across the reference resistance element R2 and the forward voltage between the base and emitter of the bipolar transistor T5.

The above reference voltage circuit uses the fact that the temperature characteristic of the voltage drop of the reference resistance element R2 is positive, and the temperature characteristic of the forward voltage between the emitters of the bipolar transistor T5 is negative. It is characterized by being small.

(Problem to be solved by the invention) However, the purpose of the reference voltage circuit described above is to make the temperature characteristics very small, almost zero, and in order to achieve this, there are restrictions on the circuit constants. be. Therefore, it can only be used with a reference voltage that has a value such that the temperature characteristics are approximately zero. Therefore, there is a drawback that the value of the detection voltage cannot be set arbitrarily.

Furthermore, when a voltage detection circuit is constructed using the above-mentioned reference voltage circuit, there is also a drawback that arbitrary temperature characteristics of the detected voltage cannot be obtained.

The second invention was made in consideration of the above circumstances, and its purpose is to provide a voltage detection circuit that can set a detection voltage having arbitrary temperature characteristics and values, and an IC card equipped with the voltage detection circuit. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) The voltage detection circuit of the present invention includes a reference current connected between a first power supply voltage and a second power supply voltage, and including a reference current whose value is adjustable. a voltage circuit, a voltage dividing circuit connected between the first power supply voltage and the second power supply voltage to divide the first power supply voltage and the second power supply voltage, and a voltage generated by the reference voltage circuit. The present invention is characterized by comprising a comparison circuit that compares the reference voltage generated by the voltage dividing circuit with the divided voltage generated by the voltage dividing circuit.

Further, the IC card of the present invention has a first power supply voltage and a second power supply voltage.
a reference voltage circuit connected between the first power supply voltage and the second power supply voltage and including a reference current circuit whose value is adjustable; A voltage divider circuit that divides the power supply voltage of 2 and a comparison circuit that compares the reference voltage generated by the reference voltage circuit and the divided voltage generated by the voltage divider circuit are integrated on the same semiconductor chip. a first integrated circuit, a second integrated circuit whose operation is controlled according to a voltage detection signal of the first integrated circuit, and a first power source for the first and second integrated circuits; The present invention is characterized in that it includes a battery that supplies the voltage and the second power supply voltage.

(Function) According to the present invention, arbitrary temperature characteristics can be obtained by adjusting the values of the reference current circuit included in the reference voltage circuit. Moreover, any detection voltage can be set by adjusting the value of the reference current circuit.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing a schematic configuration of an embodiment of a voltage detection circuit according to the present invention. Positive power supply voltage V
+ is connected to one end of a constant current circuit 1 whose value I RBP is adjustable. The other end of the constant current circuit 1 is connected to one end of a resistance circuit 2 whose resistance value can be adjusted. Furthermore, a diode 3 is connected in the forward direction between the other end of this resistance circuit 2 and the ground voltage. A reference voltage circuit 4 is constituted by the constant current circuit 1, the resistance circuit 2, and the diode 3.
A predetermined reference voltage V R1! is applied to the connection point with V R1! P is obtained.

Further, two resistance elements 5.6 are connected in series between the power supply voltage V4 and the ground voltage. These two resistive elements 5.6 constitute a voltage dividing circuit 7, and this voltage dividing circuit 7 divides the value of the power supply voltage v4 at a voltage dividing ratio according to the resistance values of the two resistive elements 5.6. A predetermined divided voltage V DIV is obtained at the connection point of the resistance element 5.6.

The reference voltage V REF obtained by the reference voltage circuit 4 and the divided voltage VDIv obtained by the voltage dividing circuit 7 are supplied to the non-inverting input terminal (+) and the inverting input terminal (-) of the voltage comparator 8, respectively. be done. Second voltage comparator 8
generates a logic signal according to the magnitude relationship between both input terminals.

Furthermore, the logic output of this voltage comparator 8 is inverted by an inverter 9 and output as a detection signal vH.

In such a configuration, now the detection signal V.

The power supply voltage V is such that the voltage becomes the "]" level. Assuming that the value of is the detection voltage V det of this voltage detection circuit, as shown in the characteristic diagram of FIG. 2, the reference voltage V REP and the divided voltage V:
l[V, etc. 1-(゛When the power supply type, !'EV. becomes the detection voltage V det.3 That is, when the power supply voltage V. is smaller than the detection voltage V det, the detection signal V1.
When l becomes the "0" level and exceeds the detection voltage V det, the detection signal VH is inverted to the "1" level.

In the above embodiment circuit, I REF of the constant current circuit 1 at an arbitrary set temperature 0 is IEFO, forward voltage VF of the diode 3 is VFQs, and reference voltage V of the reference voltage circuit 4 is
When MEI' is V, EF, and the values of the resistor element 'F5.6 in the voltage divider circuit 7 are RH and RL, the detection voltage V deLゎ at the detection temperature 0 is calculated by the following formula % formula % )] The temperature characteristic of the detection voltage Vdet is the above voltage Vdetn
It is obtained by differentiating T with respect to temperature T, which is expressed by the following formula.

Next, let's consider the temperature characteristics of diode Kq.

Figure 3 shows the forward voltage VF when the temperature T is changed with a predetermined I<Iasumi current IF flowing through the diode.
FIG. As shown in the figure, the diode has a temperature characteristic of -2 to -3 mV/'C (the value of ΔV in the figure), and the value of in the above two equations is determined by physical constants, so T is very Shows stable characteristics.

Next, the above two equations are transformed to obtain the following three equations.

Next, consider the temperature characteristics of resistance element 5.6. Resistance elements in integrated circuits are usually manufactured by low-concentration impurity diffusion or ion implantation, and the resistance value R, including temperature characteristics, of resistance elements manufactured by these methods is expressed by the following formula: .

Here, ρ0 is the sheet resistance of the resistance element, which is called sheet resistance, and is usually 1 to 8 Ω/mouth, L is the length of the resistance element, W is the width, and KT is the coefficient of temperature change of the resistance element. Usually +0. It is 1 to +1%/°C.

Next, using the above 4 equations, calculate the resistance temperature eRRp in the above 3 equations.
,p Next, let's find the temperature characteristics of the reference current. Here, as the constant current circuit 1, 91 Rap having the same configuration as in FIG. 16 is used.
.

Well, when To=300°, if To>3.3%/°C, the temperature characteristic will be negative, and if To<3.3%/°C, the temperature characteristic will be positive.

I REFO By substituting the equation into the above three equations, the following six equations are obtained.

Here, as shown in the characteristic diagram of FIG. 4, the above-mentioned equation 1 indicates the detected voltage Vdeto at the set temperature of 0, and the above-mentioned equation 6 indicates the temperature characteristic passing through this point. Therefore, in order to set the detection voltage with the desired temperature characteristics and value, by combining the above equations 1 and 6, the voltage drop RREFO/I REFO, which is the voltage drop ratio in the voltage dividing circuit 7 that satisfies the desired characteristics, is determined. Obtainable.

After determining the desired detection voltage V det and its temperature characteristics, it is possible to determine RREFO'' I R O. using the above-mentioned formula 8.

What you should be careful about here is RREP.・I REF. The other characteristics are the desired characteristics, voltage division ratio, and diode characteristics.The voltage division ratio and diode characteristics have very little manufacturing variation, and extremely stable products can be realized on integrated circuits. However, there are variations in the characteristics of the MOS transistors that make up the constant current circuit 1, asymmetry, and sheet resistance ρ when the resistance circuit 2 is made up of resistance elements.
. RREF.・I REFO
There is a risk that the value of will vary widely. However, in the case of this embodiment circuit, since the values of both the constant current circuit 1 and the resistance circuit 2 are adjustable, it is possible to easily set the values to the target values.

Next, the setting states of each of the above circuits will be explained using specific numerical values.

Generally, integrated circuits used in IC cards are programmable memories (E2F) that can be electrically written and erased.
It has a built-in ROM. Due to constraints from the internal circuitry within this E2FROM, normal operation cannot be expected if the power supply voltage drops below a certain value, so it is necessary to detect a specific power supply voltage V det and prohibit write operations. There is.

Furthermore, since the battery built into the IC card depends on its output voltage value or temperature and has a predetermined temperature gradient, the temperature characteristics of the detected voltage V det are also required to match this. Now, Vdet o = 2. 5V.

+3.3mV/'C is required as a temperature characteristic, and the characteristics of the parasitic diode in the integrated circuit are such that the forward voltage V
po"" 0. 65 V (forward via 2, Om
If V/'C, then the voltage division ratio is the equation 7 above, and the voltage drop in the resistor circuit 2 is RREP.・The value of I REFo is RR6, from the above formula 8.・I REFO-2, 5X O, 8280,
65-1,42(V)...10. Due to manufacturing variations, the above RREPO・I
Even if the value of REPO fluctuates, its value is exactly 1.42.
By adjusting the resistance value in the resistor circuit 2 so that the voltage becomes V, the value of the detected voltage and its temperature characteristics can be satisfied at the same time.

Now, suppose that the value of constant current circuit 1 fluctuates in the range of several minutes to several times the set value, or that the value of the sheet resistance in resistor circuit 2 fluctuates by ±30% of the set value. For example, the reference current adjustment range can be adjusted in 4 ways (1 relative value).
．． 2, 4.6) If the adjustment range of the resistance value in the resistance circuit 2 is determined, for example, the adjustment can be made to match the target value with sufficient accuracy. Furthermore, the number of bits of the digital signal required for adjustment in this case is 8 bits, which is a number of bits that is very easy to handle in an integrated circuit for an IC cart mainly based on a microcomputer.

Furthermore, in the above embodiment circuit, the setting range of the detection voltage and its temperature characteristics is determined depending on the manufacturing process of the diode 3, and is therefore subject to restrictions such as Vdet>Vp. However, it can be sufficiently set within the commonly used range of about 0.8<30 mV/°C.

Next, the specific configuration of each circuit when the above-described embodiment circuit is actually integrated is explained.

The constant current circuit 1 generates a predetermined reference current internally,
A constant voltage generation circuit that generates a constant voltage corresponding to this reference current, and a current adjustment circuit that is supplied with the constant voltage obtained by this constant voltage generation circuit and generates a current with a value corresponding to a multi-bit digital signal. It is configured. Figure 5 (a
) to (d) are specific circuit diagrams of the constant voltage generating circuit, respectively.

In the constant voltage generating circuit shown in FIG. 5(a), each source has a positive polarity power supply voltage ■. two P-channel MOS transistors IL 12 whose gates are connected to each other;
a current mirror circuit 13 consisting of a current mirror circuit 13; a resistance element 14 for setting a current value, one end of which is connected to the drain of the MOS transistor 11; a drain is connected to the other end of the resistance element 14; are connected to each other, and the source is connected to ground voltage.
The channel MOS transistor 15 and the drain of the MOS transistor 12 have a drain connected to the resistor element 1.
4, and an N-channel MOS transistor 16 whose gate is connected to the other end of the transistor 4 and whose source is connected to the ground voltage. In a circuit having such a configuration, the current value of the current mirror circuit 13 is set according to the value of the resistive element 14, and a current equal to this current value flows through the N-channel MOS transistor 16. And M.O.
The gate voltage of the S transistor 12.16 is the gate bias voltage VBIASP on the P channel side and the N channel side.
% Output as VBIASN.

The constant voltage generating circuit shown in FIG. 5(b) is constructed by constructing the current mirror circuit shown in FIG. 5(a) using an N-channel MOS transistor. That is,
This circuit consists of a current mirror circuit 13' consisting of two N-channel MOS transistors 11' and 12' whose sources are commonly connected to the ground voltage and whose gates are connected to each other, and a current mirror circuit 13' which is made up of two N-channel MOS transistors 11' and 12' whose gates are connected to each other, and the drain of the MOS transistor 11'. A resistor element 14 for setting a current value is connected to one end, a drain is connected to the other end of the resistor element 14, and a gate is connected to the drain of the MOS transistor 11'.
P-channel MOS whose source is connected to the power supply voltage V+
transistor 15' and the MOS transistor 12
The drain is connected to the drain of , the gate is connected to the other end of the resistor element 14, and the source is connected to the power supply voltage ■. A P-channel MOS transistor 16' is connected to the P-channel MOS transistor 16'.

Even in a circuit having such a configuration, the current value of the current mirror circuit 13' is set according to the value of the resistive element 14, and a current proportional to this current value flows through the P-channel MOS transistor 16'. Then, the gate voltage of MO3) transistor 1B'12' is applied to the P channel side and N
Channel side gate bias voltage V BIASP , V
BIASN and output output.

The constant voltage generating circuit shown in FIG. 5(c) includes a current mirror circuit 23 consisting of two P-channel MOS transistors 21 and 22 whose sources are commonly connected to the power supply voltage V+ and whose gates are connected to each other. , a current mirror circuit 26 consisting of two N-channel MOS transistors 24 and 25 whose drains are respectively connected to the drains of the MO transistors 21 and 22 and whose gates are connected to each other;
The resistor element 27 for setting a current value is connected between the source of the MOS transistor 24 and the ground voltage.

Note that the source of the MOS transistor 25 is directly connected to the ground voltage. In a circuit with such a configuration, the two current mirror circuits 2
The current value of 3.26 is set to the same value.

Then, the gate voltages of the MO5I transistors 22 and 25 are output as gate bias voltages vBIASP and VBIASN on the P-channel side and the N-channel side.

The constant voltage generating circuit shown in FIG. 5(d) is constructed by constructing the current mirror circuit shown in FIG. 5(C) using MOS transistors having opposite channel types. That is, this circuit includes a current mirror circuit 23' consisting of two N-channel MOS transistors 21' and 22' whose sources are commonly connected to the ground voltage and whose gates are connected to each other; Two P-channel MOs connected to the drains of 21' and 22', respectively, and whose gates are connected to each other.
A current mirror circuit 26' consisting of S transistors 24' and 25' and a source of the MOS transistor 24'
and a resistance element 27 for setting a current value connected between the power supply voltage V4 and the power supply voltage V4. Note that the source of the MOS transistor 25' is directly connected to the power supply voltage V+. Even in a circuit with such a configuration, the two current mirror circuits 23' and 2B
' is set to the current value or the same value, and the MOS transistor 2
Gate voltages of 5' and 22' or gate bias voltages of P channel side and N channel side V RIASP , V BI
Output as ASN.

FIGS. 6(a) and 6(b) are specific circuit diagrams of the current adjustment circuit in the constant current circuit 1, respectively.

The current adjustment circuit shown in FIG. 6(a) is based on the current adjustment circuit shown in FIGS.
P output from any one of the constant voltage generation circuits in d)
The gate bias voltage V BIASP on the channel side and 4
As mentioned above, the relative value is 1.2,
It generates 11 flows in 4 ways with a value of 4.6. This circuit obtains a power supply voltage V+ and an output current. node 3
It is composed of two P-channel MOS transistors 31, 32, 33, 34, 35, 36, 37, and 38, which are connected in series between each other. Transistor 31.33.35.
A gate bias voltage V BIASP is supplied in parallel to the gate of 37, and each other MOS) transistor 32.3
Four types of control signals are supplied to the gates of 4.38.38. The dimensions of each of the above two elements connected in series are, assuming that each of the MOS transistors 31 and 32 is "1", 33 and 34 are both rlJ, and 35 and 36 are both "1".
2'', and 37 and 38 are both set to be ``2''.

In this circuit, when the control signal supplied to the gate of the MOS transistor 32 is set to "O" level, the M
The OS transistor 32 turns on, and the MOS transistor 3
1.32 from the power supply voltage ■ to node 30,
A current having the value "1" is supplied. Further, when the control signals supplied to each gate of the MOS transistors 32 and 34 are both set to the "0" level, both the MOS transistors 32 and 34 are turned on, and the "2" level is applied to the node 30.
A current of value is supplied. Similarly, by selectively setting the control signal supplied to each gate to the "O" level, the MOS transistors 32, 34, 36, and 38 are selectively turned on, and the respective element dimensions are adjusted. A corresponding value of current is supplied to node 30.

The current adjustment circuit of FIG. 6(b) replaces the P-channel MOS transistor in the circuit of FIG. 6(a) above.
This uses an N-channel MOS transistor. It should be noted that the parts corresponding to those in FIG. 6(a) are marked with "'" at the end of the reference numerals, and detailed explanation thereof will be omitted. In the case of this circuit, the N-channel side gate bias voltage VBIASN output from any one of the constant voltage generating circuits shown in FIGS. , 37' is different from FIG. 6(a) only in that it is supplied in parallel to each gate.

FIG. 7(a) is a circuit diagram showing a specific configuration of the resistor circuit 2 and diode 3 in the reference voltage circuit 4. FIG. The diode 3 is constructed using a PNP type bipolar transistor 40 parasitically formed by a CMOS process, and is used with its base B and collector C both connected to the ground voltage. Note that a cross-sectional view of this bipolar transistor 40 is shown in FIG. 8(a). Furthermore, the resistance circuit 2 includes a plurality of resistance elements 41 . . . . and N for a plurality of switches connected in parallel between each series connection point of these resistance elements and the emitter of the bipolar transistor 40.
Channel MOS transistor 42. It is composed of... The MOS transistor 42.・
Each of the plurality of control signals is supplied to each gate of .

In this circuit, the above-mentioned MOS) transistor 42. . . are selectively controlled on and off, the resistance elements 41 . . . connected in series within the resistance circuit 2 . . is selected, and a voltage drop corresponding to the selected number is obtained across the resistor circuit 2.

FIG. 7(b) is a circuit diagram showing another specific configuration of the resistor circuit 2 and diode 3 in the reference voltage circuit 4.

This circuit is constructed using a PNP type bipolar transistor 40' parasitically formed by a CMOS process, and is used with its base B and collector C both connected to the power supply voltage V+. Furthermore, in this circuit, an N-channel MOS transistor 4 for the switch is used.
2 1. .

Instead of P-channel MOS transistor 42'...
I try to use A cross-sectional view of the bipolar transistor 40' is shown in FIG. 8(b).

FIGS. 9(a), (b), and (c) are circuit diagrams showing specific configurations of the voltage dividing circuit 7, respectively.

In the voltage divider circuit of FIG. 9(a), a plurality of resistive elements 51. ... are connected in series, and voltages of different values generated at each series connection point of these resistance elements are connected to a plurality of switch elements 52. ...
By selectively turning on the voltage, the voltage is extracted as a divided voltage VDIv. In this case, the values of the resistive elements R and R5 are equal to the power supply voltage V, with the switch element 52 selectively turned on as a boundary. This corresponds to the sum of the resistance values of all the resistance elements 51 existing on the side and the sum of the resistance values of all the resistance elements 51 existing on the ground voltage side.

On the other hand, in the voltage dividing circuits of FIGS. 9(b) and 9(c), the power supply voltage is V, respectively. A plurality of resistive elements 5 are connected between the
1. ... are connected in series, and each one end of a plurality of switch elements 52... is connected to each series connection point of these resistance elements, and these switch elements 52. A predetermined voltage is supplied to each other end of these switching elements 52. The divided voltage V whose value differs by selectively turning on...
The DIV is taken out.

FIGS. 10(a) and 10(b) show the reference voltage V RE
FIG. 2 is a circuit diagram showing a specific configuration of the voltage comparator 8 that compares F and a divided voltage VDIv.

The circuit of FIG. 10(a) has an N-channel side gate bias voltage V BI generated in the circuit of FIG. 5 at the gate.
An N-channel MOS transistor 61 for a current source to which ASN is supplied; two N-channel MOS transistors whose sources are commonly connected and each gate is supplied with the reference voltage V REP or divided voltage V DIV; 2.
63 differential pair 64. A differential amplifier stage 68 comprising two P-channel MOS transistors 65.6B and a current mirror circuit 67 serving as a load for the differential pair 64.
And the above gate bias voltage V B H^SN is applied to the gate.
This is a well-known device consisting of an N-channel MOS transistor 69 for a current source to which the differential amplifier stage 68 is supplied, and an output stage 71 consisting of a P-channel MOS transistor 0 whose gate is supplied with the output of the differential amplifier stage 68. be.

Further, the circuit of FIG. 10(b) uses an N-channel MOS transistor instead of the P-channel MOS transistor in the circuit of FIG. 10(a), and an N-channel MOS transistor.
S) P-channel MOS transistors are used instead of transistors. In addition, the first
For locations corresponding to Figure 0 (a), there is a ``''' at the end of the code.
, and detailed explanation thereof will be omitted. Note that in the case of this circuit, P-channel MOS transistors 81', 69
A P-channel side gate bias voltage VBt^sp generated in the circuit shown in FIG. 5 is supplied to each gate of .

FIG. 11 is a detailed diagram showing the overall configuration when the embodiment circuit shown in FIG. 1 is actually integrated using the specific circuits shown in FIGS. 5 to 10.

In the figure, IA is a constant voltage generating circuit within the constant current circuit 1. This constant voltage generating circuit IA basically has the same configuration as that shown in FIG. 5(a), but a standby function and a capacitor kick function are added to this basic circuit.

That is, a P-channel MOS transistor 17 is connected between the connection point of the gate and drain of the MOS transistor 12 where the P-channel side gate bias voltage VB18SP is obtained and the power supply voltage V+, and the N-channel side gate bias voltage N-channel MOS transistors 18 are connected between the connection point of the gate and drain of the MOS transistor 16 from which V BIASN is obtained and the ground voltage.

The standby control signal OP is supplied to the gate of one of the MOS transistors 18, and the standby control signal OP is supplied to the gate of the other MOS transistor 17.
Inverter 19 where P is an odd number. ... are supplied in series. Furthermore, one end of a capacitor 20 is connected to the common drain of the MOS transistors 12, 16, and the other end of this capacitor 20 receives a standby control signal OP from an even number of inverters 19. Supplied via...

In a circuit with such a configuration, when the standby control signal -1 is at the "1" level, the MOS transistors 18 and 17
are both turned on, and the gate bias voltage VB on the P channel side
IAsP is set to the power supply voltage V+, and the gate bias voltage VBIASN on the N-channel side is set to the ground voltage of OV, thereby entering a standby state.

When the standby control signal OP is inverted from the "1" level to the "0" level, the above MOS1-transistor 18.17
MO3I is also turned off through capacitor 20.
- common drain of transistors 12.16 is forced to “0”
He is pulled down by Rubel.

IB in FIG. 11 is a constant voltage generating circuit in the constant current circuit 1. This constant voltage generating circuit 1B basically has the same configuration as that shown in FIG. 6(a), but a standby function and a digital signal decoding function are added to this basic circuit.

The operation of this circuit is based on the standby control signal 0POP and the 2-bit digital signal B6. It is controlled from B7. The standby control signal OP is the MO
It is supplied to the gate of the S transistor 32. The above 2-bit digital signal B6. B7 is supplied to OR gate 81 in parallel.

The output of this OR gate 81 is supplied together with the standby control signal OP to a NAND gate 82, and the output of this NAND gate 82 is supplied to the gate of the MOS transistor 34. The one digital signal B7 is supplied to the NAND gate 83 together with the standby control signal OP,
The output of this N A N D 83 is supplied to the gate of the MOS transistor 34 . Further, 2-bit digital signals B6 and B7 are supplied to an AND gate 84 in parallel. The output of this AND gate 84 is supplied to a NAND gate 85 together with the standby control signal OP, and this
The output of A N D 85 is the MO8) transistor 3.
8 gates.

A circuit with such a configuration operates when the standby control signal OP is at the "1" level and when OP is at the 0" level, and a predetermined current flows through the node 30. Now, both the 2-bit digital signals B6 and B7 When it is “0” level, MOS
The transistor 32 turns on, and the node 30 receives the "1".
A current corresponding to flows. Furthermore, when the lower digit signal B6 of the 2-bit digital signals B6 and B7 is at the "1" level, the output of the NAND gate 82 is at the "0" level, and the MOS transistor 34 is turned on. Therefore, at this time, the two MOS transistors 32 and 34 are both turned on, and a current corresponding to "2" flows through the node 30. Further, when the signal B7 of the upper digit is at the "1" level, the output of the NAND gate 83 is at the "0" level, and the MOS transistor 36 is turned on. Therefore, at this time, the three MOS transistors 32, 34, and 36 are all turned on, and a current corresponding to "4" flows through the node 30. Furthermore, a 2-bit digital signal B
6. When both B7 are at the "1" level, the output of the NAND gate 85 is at the "0" level, and the MOS transistor 38 is turned on. Therefore, at this time, all four MOS transistors 32, 34, 36, and 38 are turned on, and a current corresponding to the above "6" flows through the node 30.

The resistance circuit 2 in FIG. 11 is basically the same as that shown in FIG.
), but a standby function and a digital signal decoding function are added to this basic circuit. These functions are controlled by the standby control signal OP.
and 6-bit digital signals BO-B5. It is controlled based on BO to B5.

That is, each output of a plurality of NOR gates 43 is supplied in parallel to the gate of the N-channel MOS transistor 42 for the switch. These NO
Between each input terminal of the R gate 43 and the power supply voltage V+, a plurality of P-channel MOS transistors 4 for charging are controlled based on the standby control signal OP.
4 is connected. Further, between each one input terminal of the NOR gate 43 and the ground voltage, the six 6-pin N-channel MOS transistors 45. ... are connected in series. Further, a standby control signal OP is supplied in parallel to each other input terminal of the NOR gate 43.

In this circuit, when the standby control signal OP is at the "0" level, each MOS transistor 44 is turned on, and the NO.
Each one input terminal of the R gate 43 is charged to the "1" level, that is, the power supply voltage V+. At this time, each other input terminal of the NOR gate 43 is set to the "0" level by the signal OP. In this state, the six series-connected MOS transistors 45.
When any one set of . . . is all turned on, one NOR gate 4 is
One input terminal of NO.3 is discharged to “0” level, and this NO.
Only the output of the R gate 43 becomes "1" level. Then, the switch MO3I-transistor 42 to which the output of the NOR gate 43 is supplied is selectively turned on, and the number of the plurality of resistance elements 41 is determined.

The diode 3 in FIG. 11 is basically the diode 3 shown in FIG.
Like the one in a), it is constructed using PNP type bipolar transistors, but a standby function is added to this basic circuit. An N-channel MOS transistor 46 is connected in parallel between the emitter and collector of the bipolar transistor constituting the diode 3, and a standby control signal OP is supplied to the gate of the MOS transistor 46.

This circuit enters a standby state when the standby control signal OP is at the "1" level. That is, in this standby state, the MOS transistor 46 is turned on,
Both ends of diode 3 are shorted.

However, when the standby control signal OP is at the "0" level, the MOS transistor 46 is turned off and the diode 3 generates a predetermined forward voltage.

The voltage dividing circuit 7 in FIG. 11 is basically constructed using resistive elements 5 and 6 in the same way as the one in FIG. 1, but a standby function is added to this basic circuit. is added. That is, a P-channel MOS transistor 47 whose gate is supplied with a standby control signal OP is connected in series to the resistance element 5.

In this circuit, when the standby control signal OP is at the "1" level, the MOS transistor 47 is turned off and the circuit is in a standby state.

The voltage comparator 8 shown in FIG. 11 has basically the same structure as that shown in FIG. 10(a), but a standby function is added to this basic circuit. That is, in this circuit, a P-channel MOS transistor 91 is connected between the gate of the MOS transistor 0 of the output stage 71 and the power supply voltage V+, or an N transistor is connected between the logic signal output terminal of the output stage 71 and the ground voltage. The MOS transistors 92 of the channels are connected to each other, and the standby control signal oP is applied to the gate of one MOS transistor 91.
A standby control signal OP is supplied to the gates of the other MOS transistors 92, respectively. In such a configuration, the standby control signal OP is at “0” level, OP
In the standby state of 1 level, both the MOS transistors 91 and 92 are turned on, and the logic output signal goes to the "0" level without any delay in response to the input.

In FIG. 11, the inverter 9 is constituted by a CMOS inverter consisting of a P-channel MOS transistor 93 and an N-channel MOS transistor 94 as shown. FIG. 12 shows details of the overall configuration, which is different from that shown in FIG. 11, when the embodiment circuit shown in FIG. 1 is actually integrated using the specific circuits shown in FIGS. 5 to 10. It is a diagram.

This detailed circuit operates the resistor circuit 2 using a standby control signal OP and 4-bit digital signals BO to B3. B-B
3, and the voltage dividing circuit 7 is controlled based on the standby control signal OP and 2-bit digital signals B4, B5 .
Control is performed based on B4 and B5.

That is, the resistance circuit 2 has the NOR gate 43
The 4-bit digital signals BO to B3 . are connected between each other input terminal and the ground voltage. Four N-channel MOS transistors 45, . . . are connected in series, each of which receives a combined signal of BO to B3 to each gate.

On the other hand, the voltage dividing circuit 7 basically operates as shown in FIG. 9(a).
However, a standby function and a digital signal decoding function are added to this basic circuit. That is, in this voltage dividing circuit 7,
The switch element 52 is composed of N-channel MOS transistors 53, and the outputs of a plurality of NOR gates 54 are supplied in parallel to the gates of these MOS transistors 53. A plurality of P-channel MOS transistors 55 for charging, which are controlled based on the standby control signal OP, are connected between one input terminal of each of these NOR gates 54 and the power supply voltage V+. Furthermore, two N-channel MOS transistors 56 . ... are connected in series. Further, a standby control signal OP is supplied in parallel to each other input terminal of the NOR gate 54.

Furthermore, a standby control signal OP is connected between the terminal end of the resistive element 51 and the ground voltage through an inverter 57 at the gate.
An N-channel MOS) transistor 58 is connected to the N-channel MOS transistor 58.

In this circuit, when the standby control signal OP is at the "0" level, the MOS transistor 58 is turned on, and current flows through the plurality of resistive elements 51 connected in series. Also, when this standby control signal OP is at "0" level, each MO
The S transistor 55 is turned on, and one input terminal of the NOR gate 54 is at the "1" level, that is, the power supply voltage V4.
is charged to. At this time, each other input terminal of the NOR gate 54 is set to the "0" level by the signal OP. In this state, the 2-bit digital signal B4. B
5° Depending on the logic state of B4 and B5, the two series-connected MOS) transistors 56. When any one set of . only is at the “1” level. Then, the switching MOS transistor 53 to which the output of the NOR gate 54 is supplied is selectively turned on, and the voltage at any connection point of the plurality of resistance elements 51 is taken out as a divided voltage.

FIG. 13 is a block diagram showing the configuration of an applied example of the present invention, in which the voltage detection circuit of the present invention is applied to an IC card. In the figure, 100 is an integrated circuit for a voltage detection circuit in which a voltage detection circuit as shown in FIG. 11 or 12 is integrated on one chip. The detection signal (the V
H) is supplied to the calculation integrated circuit 110 as a hold signal. Note that power supply voltage is supplied from a battery 130 to the image integrated circuits 100 and 110. Further, the 8-bit digital signals BO-B7 and BO-B7 used in the voltage detection circuit integrated circuit +00 are set by a switch circuit 140 provided externally.

As mentioned above, in the IC card, the arithmetic integrated circuit 11O
This B2 FROM has a built-in E2PROM.
Due to constraints from the internal circuit of the device, normal operation cannot be expected when the power supply voltage falls below a certain value. For this reason, as in the application example above, an integrated circuit in which a voltage detection circuit is configured is provided in the IC card, and this integrated circuit detects the output voltage of the battery, and this detection signal is used to hold the output voltage in the calculation integrated circuit. By multiplying by , it is possible to prevent the occurrence of erroneous writing to the E2FROM. Furthermore, since the output voltage of the battery 130 built into the IC card changes depending on the temperature, by using a voltage detection circuit that can change the temperature characteristics of the detected voltage as described above,
Improves detection reliability.

FIG. 14 is a block diagram showing the configuration of another application example of the present invention, in which the voltage detection circuit of the present invention is applied to an IC card. In this application example, the 8-bit digital signals BO to B7, BO to B7 used in the voltage detection circuit integrated circuit 100 are supplied to the voltage detection circuit integrated circuit 100 as stored data in the memory 140. This is what I did. Note that this memory 140 is the voltage detection circuit integrated circuit 100 or the calculation integrated circuit 11.
It is also possible to use the one built in 0.

FIG. 15 is a circuit diagram showing the configuration of still another application example of the present invention. In this application example circuit, the output of the voltage comparator 8 is supplied to the gate instead of connecting the constant current circuit 1 and the resistance element 5 in the voltage dividing circuit 7 to the power supply voltage V+ in the example circuit shown in FIG. MO of P channel to be
Power supply voltage ■ via the S transistor 10. By connecting it to the circuit, a constant voltage output with any value and any temperature characteristics can be obtained.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a voltage detection circuit that can set a detection voltage having arbitrary temperature characteristics and values, and an IC card equipped with the voltage detection circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a schematic configuration of an embodiment of a voltage detection circuit according to the present invention, and Fig. 2 shows the relationship among the reference voltage, divided voltage, power supply voltage, and detection voltage in the above embodiment circuit. 3 is a characteristic diagram of the diode used in the above embodiment circuit, FIG. 4 is a temperature characteristic diagram of the above embodiment circuit, and FIGS. 5 to 10 are respective circuits of the above embodiment circuit. FIGS. 11 and 12 are circuit diagrams showing the detailed configuration of the embodiment circuit shown in FIG. FIG. 15 is a circuit diagram showing the configuration of another application example of the present invention, and FIG. 16 is a circuit diagram of a conventional reference voltage circuit. DESCRIPTION OF SYMBOLS 1... Constant current circuit, 2... Resistance circuit, 3... Diode, 4... Reference voltage circuit, 5, 6... Resistance element, 7... Voltage divider circuit, 8... Voltage comparator, 9.
...Inverter. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Phantom IF Figure 3 Figure (a) (a) (c) (b) Figure (b) (d) (a) (b) Figure 8 Figure 10

Claims (13)

[Claims] (1) A reference voltage circuit connected between a first power supply voltage and a second power supply voltage and including a reference current whose value is adjustable, and between the first power supply voltage and the second power supply voltage. connected to,
a voltage divider circuit that divides a first power supply voltage and a second power supply voltage; and a comparison circuit that compares a reference voltage generated by the reference voltage circuit and a divided voltage generated by the voltage divider circuit. A voltage detection circuit characterized by comprising: (2) The reference voltage circuit is connected between the first power supply voltage and the reference voltage output node, and includes a reference current circuit whose value is adjusted according to a control signal; a reference resistance circuit connected between the reference voltage output node and the second power supply voltage, the value of which is adjusted according to the control signal; and a reference resistance circuit connected between the reference voltage output node and the second power supply voltage in the forward direction, 2. The voltage detection circuit according to claim 1, further comprising a diode connected in series with the reference resistance circuit. (3) The voltage detection circuit according to claim 1, wherein the voltage division ratio of the voltage division circuit is adjusted according to a control signal. (4) The value of the forward voltage of the diode is V_F, the value of V_F at a predetermined temperature T_0 is V_F_0, the detection voltage which is the difference voltage between the first power supply voltage and the second power supply voltage is Vdet, and the value of V_F at a predetermined temperature T_0 is V_F_0. The value of Vdet at temperature T_0 is Vdet_0, and the temperature change in Vdet is ∂/(∂T).
When the temperature change of Vdet, V_F is ∂/(∂T)V_F, the voltage division ratio D of the voltage dividing circuit is: 4. The voltage detection circuit according to claim 3, wherein the voltage detection circuit is set to have the following relationship. (5) The voltage division ratio of the voltage dividing circuit is D, and the detection voltage Vde is the difference voltage between the first power supply voltage and the second power supply voltage.
When the value of t at a predetermined temperature T_0 is Vdet_0, the forward voltage of the diode V_F is the value at a predetermined temperature T_0 is V_F_0, the voltage generated across the reference resistance circuit is set to Vdet_0×D−V_F_0. The voltage detection circuit according to claim 3, characterized in that: (6) The value of the forward voltage of the diode is V_F, the value of V_F at a predetermined temperature T_0 is V_F_0, the detection voltage which is the difference voltage between the first power supply voltage and the second power supply voltage is Vdet, and the value of V_F at a predetermined temperature T_0 is V_F_0. The value of Vdet at temperature T_0 is Vdet_0, and the temperature change in Vdet is (∂/∂T).
When the temperature change of Vdet, V_F is (∂/∂T)V_F, the voltage division ratio D of the voltage dividing circuit is: ▼, and the voltage division ratio of the voltage dividing circuit is D, and the detection voltage Vdet, which is the difference voltage between the first power supply voltage and the second power supply voltage, is set at a predetermined temperature T_0. When the value is Vdet_0 and the value of the forward voltage V_F of the diode at a predetermined temperature T_0 is V_F_0, the voltage generated across the reference resistance circuit is set to Vdet_0×D−V_F_0. The voltage detection circuit according to claim 3. (7) The voltage detection circuit according to claim 1, wherein the reference voltage circuit, voltage dividing circuit, and comparison circuit are formed on the same semiconductor chip. (8) a reference voltage circuit connected between a first power supply voltage and a second power supply voltage and including a reference current circuit whose value is adjustable;
a voltage dividing circuit connected between the first power supply voltage and the second power supply voltage and dividing the first power supply voltage and the second power supply voltage; and a reference voltage generated by the reference voltage circuit. a first integrated circuit in which a comparison circuit for comparing the divided voltages generated by the voltage dividing circuit is integrated on the same semiconductor chip;
a second integrated circuit whose operation is controlled in accordance with the voltage detection signal of the first integrated circuit; An IC card characterized in that it is equipped with a battery that supplies. (9) The reference voltage circuit is connected between the first power supply voltage and the reference voltage output node, and includes a reference current circuit whose value is adjusted according to a control signal; a reference resistance circuit connected between the reference voltage output node and the second power supply voltage, the value of which is adjusted according to the control signal; and a reference resistance circuit connected between the reference voltage output node and the second power supply voltage in the forward direction, 9. The IC according to claim 8, further comprising a diode connected in series to the reference resistance circuit.
card. (10) The IC card according to claim 8, wherein the voltage dividing ratio of the voltage dividing circuit is adjusted according to a control signal. (11) The value of the forward voltage of the diode is V_F, the value of V_F at a predetermined temperature T_0 is V_F_0, the detection voltage which is the difference voltage between the first power supply voltage and the second power supply voltage is Vdet, and the value of V_F at a predetermined temperature T_0 is V_F_0. The value of Vdet at temperature T_0 is Vdet_0, and the temperature change in Vdet is (∂/∂T
)Vdet, the temperature change of V_F is (∂/∂T)V_F
A claim characterized in that the voltage division ratio D of the voltage dividing circuit is set to the following relationship: ▲There is a mathematical formula, chemical formula, table, etc.▼ or ▲There is a mathematical formula, chemical formula, table, etc.▼ The IC card described in Section 10. (12) The voltage division ratio of the voltage dividing circuit is D, and the detection voltage Vd is the difference voltage between the first power supply voltage and the second power supply voltage.
When the value of et at a predetermined temperature_0 is Vdet_0, and the value of the forward voltage V_F of the diode at a predetermined temperature T_0 is V_F_0, the voltage generated across the reference resistance circuit is Vdet_0×D−V_F_0. The IC card according to claim 10, wherein the IC card is set. (13) The value of the forward voltage of the diode is V_F, the value of V_F at a predetermined temperature T_0 is V_F_0, the detection voltage that is the difference voltage between the first power supply voltage and the second power supply voltage is Vdet, and the value of V_F at a predetermined temperature T_0 is V_F_0. The value of Vdet at temperature T_0 is Vdet_0, and the temperature change in Vdet is (∂/∂T
)Vdet, the temperature change of V_F is (∂/∂T)V_F
When, the voltage division ratio D of the voltage divider circuit is set to the relationship ▲There is a mathematical formula, chemical formula, table, etc.▼ or ▲There is a mathematical formula, chemical formula, table, etc.▼, and the said partial pressure The voltage division ratio of the circuit is D, the value of the detection voltage Vdet, which is the difference voltage between the first power supply voltage and the second power supply voltage, at a predetermined temperature T_0 is Vdet_0, and the forward voltage of the diode is V_
When the value of F at a predetermined temperature T_0 is V_F,
The IC card according to claim 10, wherein the voltage generated across the reference resistance circuit is set to Vdet_0×D−V_F_0.