JPH04103000A - Alarm detecting circuit - Google Patents
Alarm detecting circuitInfo
- Publication number
- JPH04103000A JPH04103000A JP22151390A JP22151390A JPH04103000A JP H04103000 A JPH04103000 A JP H04103000A JP 22151390 A JP22151390 A JP 22151390A JP 22151390 A JP22151390 A JP 22151390A JP H04103000 A JPH04103000 A JP H04103000A
- Authority
- JP
- Japan
- Prior art keywords
- alarm
- resistors
- terminals
- circuit
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Landscapes
- Alarm Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は警報検出回路に関し、特に警報発生源から伝達
されたN個の警報のうち、任意の2個以上の警報か発生
したときにそれを認識する警報検出回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an alarm detection circuit, and particularly to an alarm detection circuit that detects when any two or more alarms occur among N alarms transmitted from an alarm source. This invention relates to an alarm detection circuit that recognizes.
警報検出において、警報発生源よりの警報のうち2個以
」二の警報発生かあった場合のみ警報として認識したい
ということかまれに存在する。例えは、3台〜4台の電
源装置を並列運転していたとき、1台の電源装置か故障
しても並列運転なので装置全体としては影響ないか、2
台が故障すると電源供給能力か足りなくなり、重大障害
として警報を発しなければならないといったような場合
である。In alarm detection, there are rare cases where it is desired to recognize as an alarm only when two or more alarms are generated from the alarm source. For example, when three or four power supplies are operated in parallel, even if one power supply fails, will it not affect the entire system because it is running in parallel?
This is the case when the power supply capacity becomes insufficient when the stand malfunctions, and an alarm must be issued as a serious failure.
このような警報処理上の要求に対して、従来ては、第3
図に示すように、警報発生源1から発せられるN個の警
報信号は、0本の情報伝達線を用い警報信号をそのまま
警報処理回路2bへ転j−Xし、警報処理回路2の中で
論理演算により122個以−の警報発生jという判定を
行うというのか一殻的であった。Conventionally, in response to such alarm processing requirements, the third
As shown in the figure, N alarm signals emitted from the alarm source 1 are transferred as they are to the alarm processing circuit 2b using 0 information transmission lines, and are then transmitted within the alarm processing circuit 2. It was rather simple to use logical operations to determine whether 122 or more alarms had occurred.
」二連しノに従来の警報検出では、警報処理回路が高度
な論理演算の行える複雑な回路になっていたり、あるい
は、マイクロコンピュータを内蔵してインテリジエン1
〜な処理を行うなと、警報処理回路の負担か大きいとい
う欠点の他、複数の警報情報を発生源から警報処理回路
まで転送するため、発生源が増加ずと配線数が多くなり
装置内の配線か煩雑になるという問題点があった。In conventional alarm detection systems, the alarm processing circuit is a complex circuit that can perform advanced logical operations, or an intelligent one with a built-in microcomputer.
In addition to the disadvantage that the burden on the alarm processing circuit is large, the number of wiring increases without increasing the number of sources, which causes problems within the device. There was a problem that the wiring was complicated.
本発明の目的は、警報処理回路の負担を軽減し、且つ警
報処理回路への配線本数を1本ですまずことができる警
報検出回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide an alarm detection circuit that can reduce the burden on the alarm processing circuit and reduce the number of wires to the alarm processing circuit by only one.
本発明の警報検出回路は、一方か警報信号を受信する入
力端子に接続され他方か複式接続され同抵抗値を有する
N個の抵抗器と、一方を前記N個の抵抗器が複式接続さ
れた側に接続し他方を電源に接続し前記抵抗器と同抵抗
値を有する第1の抵抗器と、前記電源の三分の一より低
く且つ三分の一より高くなるような基準電位に設定する
だめの第2の抵抗器と、前記基準電位と前記N側内抵抗
器の複式接続された側の電位との電圧比較を行う比較器
とを備える構成である。The alarm detection circuit of the present invention includes N resistors having the same resistance value, one of which is connected to an input terminal for receiving an alarm signal and the other of which is double-connected, and the N resistors are double-connected to one side. a first resistor connected to one side and the other to a power source and having the same resistance value as the resistor; and a reference potential set to be lower than one-third and higher than one-third of the power source. This configuration includes a second resistor, and a comparator that performs a voltage comparison between the reference potential and the potential of the N-side inner resistor that is double-connected.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例を示す回路図、第2図は第1
図におけるA、B点及び出力端子80の電圧波形を示す
図である。第1図において、g報検出回路は警報発生源
]と暫報処理回路2aとの間に設けられ、警報発生源1
は、N個の発生源を有し、警報が発せられると地気か出
力されるものとする。警報検出回路は、一方か警報信号
を受信する入力端子31〜3nに接続され他方か複式接
続されるN個の抵抗器41〜4nと、このN個の抵抗器
41〜4nか複式接続された側に一方を接続し他方を電
源V。0に接続される抵抗器50と、電源Vcoの三分
の一より低く且つ三分の一より高くなるような基準電位
に設定するだめの抵抗器61.62と、この基準電位と
抵抗器41〜4nか複式接続された側の電位との電圧比
較を行う比較器70とを備える。ここで、抵抗器41〜
4n、50はそれぞれ同一の抵抗値を有している。Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
It is a figure which shows the voltage waveform of the A, B point and the output terminal 80 in a figure. In FIG. 1, the g-alarm detection circuit is provided between the alarm generation source 1 and the temporary alarm processing circuit 2a.
has N generation sources, and when an alarm is issued, it is assumed that earth air is output. The alarm detection circuit includes N resistors 41 to 4n, one of which is connected to the input terminals 31 to 3n that receive the alarm signal, and the other of which is connected in multiple ways. Connect one side to the power supply V and the other side. 0, resistors 61 and 62 for setting a reference potential that is lower than one-third and higher than one-third of the power supply Vco, and this reference potential and resistor 41. .about.4n and a comparator 70 that performs a voltage comparison with the potential of the dual-connected side. Here, resistors 41~
4n and 50 have the same resistance value.
以下に、動作を説明する。警報発生源1から地気による
1個の警報信号が、入力端子31〜3nのいずれかに入
力されると、入力端子に接続された抵抗器41〜4nの
いずれが]つと抵抗器50とによって電源V。0の三分
の−の電圧かB点に発生ずる。又、発生した警報が2個
の場合には、電源Vccの三分の−の電圧がB点に発生
する。警報発生源1からの警報信号の数が3個以上にな
ればB点の電圧は電源V。Cの三分の一よりも更に低く
なっていく。ここで、B点は比較器70の負極性入力端
子に接続され、A点は比較器70の正極性入力端子に接
続されており、A点は電源V。0の分の一より低く且つ
電源Vcoの三分の一より高い電位に抵抗器8]−及び
62によって設定されている。従って、警報発生源1か
らの警報信号入力の数か「0及び]」のときは比較器7
0の出力端子80はローレベルであるか、警報信号入力
数が「2個以上」になると、B点とA点の電位差が逆転
し、出力端子80は第2図に示すようにハイレベルとな
る。すなわち、12個以上」の警報信号の入力かあるこ
とを示す信号か出力端子80から取出せる。このように
して得られた警報情報は、1本の線で警報処理回路2a
に入力される。The operation will be explained below. When one earth alarm signal from the alarm source 1 is input to any of the input terminals 31 to 3n, which one of the resistors 41 to 4n connected to the input terminal is Power supply V. A voltage of -3/0 is generated at point B. Further, when two alarms are generated, a voltage of -3/3 of the power supply Vcc is generated at point B. If the number of alarm signals from alarm source 1 is 3 or more, the voltage at point B is the power supply V. It becomes even lower than one-third of C. Here, point B is connected to the negative input terminal of the comparator 70, point A is connected to the positive input terminal of the comparator 70, and point A is connected to the power supply V. It is set by resistors 8 and 62 to a potential lower than one-third of zero and higher than one-third of the power supply Vco. Therefore, when the number of alarm signal inputs from alarm source 1 is "0 and ]", comparator 7
When the output terminal 80 of 0 is at low level or the number of alarm signal inputs becomes "2 or more", the potential difference between point B and point A is reversed, and the output terminal 80 becomes high level as shown in Fig. 2. Become. In other words, a signal indicating that 12 or more alarm signals are input or present can be taken out from the output terminal 80. The alarm information obtained in this way is transmitted to the alarm processing circuit 2a via one line.
is input.
本発明は以」二説明したように、警報発生源からの警報
のうち2個以」二の警報信号を受信した場合に限り警報
として認識するように構成したので、警報処理回路での
論理演算処理が不要となり警報処理回路の負担を軽減し
、且つ警報処理回路への配線本数を1本ですますことか
できる。As explained below, the present invention is configured so that it is recognized as an alarm only when two or more alarm signals are received from the alarm source. No processing is required, the burden on the alarm processing circuit is reduced, and the number of wires connected to the alarm processing circuit can be reduced to one.
第1図は本発明の一実施例を示す構成図、第2図は第1
図のA、B点及び出力端子における電圧波形を示す図、
第3図は従来の警報検出回路を説明するための図である
。
]、 −−−一警報発生源、2a、2b−回路 31〜
3n−一−−−−入力端子、450.6]、、62−−
・−抵抗器、70・80−・−出力端子。
警報処理
1〜4 n 。
・−・比較器、FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
A diagram showing voltage waveforms at points A and B and the output terminal in the diagram,
FIG. 3 is a diagram for explaining a conventional alarm detection circuit. ], ---One alarm source, 2a, 2b-circuit 31~
3n-1---input terminal, 450.6], 62--
・-Resistor, 70/80-・-Output terminal. Alarm processing 1-4 n.・−・Comparator,
Claims (1)
複式接続され同抵抗値を有するN個の抵抗器と、一方を
前記N個の抵抗器が複式接続された側に接続し他方を電
源に接続し前記抵抗器と同抵抗値を有する第1の抵抗器
と、前記電源の二分の一より低く且つ三分の一より高く
なるような基準電位に設定するための第2の抵抗器と、
前記基準電位と前記N個の抵抗器の複式接続された側の
電位との電圧比較を行う比較器とを備えたことを特徴と
する警報検出回路。One side is connected to the input terminal that receives the alarm signal, and the other side is connected in multiples and has N resistors having the same resistance value, and one side is connected to the side where the N resistors are connected in multiples, and the other is connected to the power source a first resistor connected and having the same resistance value as the resistor; a second resistor for setting a reference potential lower than one-half and higher than one-third of the power supply;
An alarm detection circuit comprising: a comparator that compares a voltage between the reference potential and a potential on a side of the N resistors that are double-connected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22151390A JPH04103000A (en) | 1990-08-23 | 1990-08-23 | Alarm detecting circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP22151390A JPH04103000A (en) | 1990-08-23 | 1990-08-23 | Alarm detecting circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04103000A true JPH04103000A (en) | 1992-04-03 |
Family
ID=16767893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP22151390A Pending JPH04103000A (en) | 1990-08-23 | 1990-08-23 | Alarm detecting circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04103000A (en) |
-
1990
- 1990-08-23 JP JP22151390A patent/JPH04103000A/en active Pending
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