JPH04102295A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent operating speed lowered while providing with a redundancy function by driving the opening/closing of each transfer gate by a complementary output signal from a redundant cell selection circuit. CONSTITUTION:The semiconductor memory is equipped with the redundant cell selection circuit 11 which selects a storage cell in a redundant cell area 3 when a preset redundant address is selected by replacing it by the storage cell in an ordinary storage cell area 2 in accordance with the redundant address, and the transfer gates TrD are provided at bit lines BLD, the inverse of BLD in the ordinary cell area 2, and the transfer gates Trj at bit lines BLj, the inverse of BLj in the redundant cell area 3, and the opening/closing of the transfer gates TrD, Trj are driven by the complementary output signals JD, the inverse of JD from the redundant cell selection circuit 11. Either the transfer gates TrD, Trj is selected and turned on, and either the storage cell in the ordinary cell area 2 or that in the redundant cell area 3 is selected.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor memory device with a redundant function that does not reduce operating speed while having a redundant function. A semiconductor memory device comprising a redundant cell selection circuit that selects a memory cell in a redundant cell area in place of a memory cell in a normal memory cell area corresponding to the redundant address when a redundant address is selected, A transfer gate is provided for each bit line in the area, a transfer gate is provided for the bit line in the redundant cell area,
Each of the transfer gates is configured to be driven to open and close using complementary output signals from the redundant cell selection circuit.

[Industrial application field]

The present invention relates to a semiconductor memory device with a redundant function.

In a semiconductor memory device, redundant cells are provided in advance among the many cells that make up the storage area, and if a defective cell is discovered during the inspection process during the manufacturing process, access to the defective cell is changed to the redundant cell. However, there is a demand for faster access.

[Conventional technology]

The basic configuration of a conventional SRAM will be explained with reference to FIG. 4. A cell area 1 is provided with a normal cell 2 and a redundant cell 3. Each column is selected via the column selection gate 5 or the redundant column selection gate 6 based on the selection signal, and a predetermined cell is selected from the selected columns based on the output signal of the row decoder 7.

A column address buffer 8 is connected to the column decoder 4, and a row address buffer 9 is connected to the row decoder 7.
A block address buffer 10 is connected to the column decoder 4 and row decoder 7. Then, a predetermined memory cell in the cell area 1 is selected based on the address selection signal inputted to the column address buffer 8 and the row address buffer 9, and a cell area is selected based on the block selection signal inputted to the block address buffer 10. A predetermined storage cell within one is selected for each block.

A redundant ROMII is connected to the column address buffer 8, and the output signal of the redundant ROMII is sent to the column decoder 4.
It is output to . In the redundant ROM II, the address of the defective cell in the normal cell area 2 can be set by cutting a fuse, for example, and when the set address matches the address signal output from the column address buffer 8, the redundant ROM II The ROMII outputs, for example, an H-level redundant address match signal to the column decoder 4, and based on the redundant address match signal, the column decoder 4 selects the column containing the defective cell in the normal cell area 2 and selects the redundant cell area 3 instead. A column within the column is selected, and a predetermined cell within the column is selected by the output signal of the row decoder 7.

An output buffer circuit 13 and an input buffer circuit 14 are connected to the cell area 1 via data buses DB and DB, and when data is written to the cell area 1, data input from the outside via the input buffer circuit 14 is connected to the cell area 1. The data written to the selected memory cell and read from the selected memory cell at the time of data reading is transferred to the data bus DB,
It is output via the DB and output buffer circuit 13.

However, in the SRAM configured in this way, when an address selection signal is input to the row address buffer 9 and the column address buffer 8, for example, the address signal is output from the column address buffer 8 to the column decoder 4, but the column decoder 4 Its address signal and redundant ROM
Based on the redundant address match signal from II, either the column in the normal cell area 2 or the column in the redundant cell area 3 is selected. That is, the column decoder 4 does not operate immediately based on the address signal from the column address buffer 8, but waits for a redundant address match signal from the redundant ROM 11 to operate. Therefore, it is necessary to delay the operation of the column decoder 54 by a time corresponding to the operating time of the redundant ROM 11.
There was a problem in that the operating speed of the SRAM decreased.

In order to solve these problems, an SRAM as shown in FIG. 5 has been proposed. That is, each bit line BLD of each column CI, C2, etc. of the normal cell area 2,
Nc is connected to the base end of the common bus CB, σ■ connected to the BLD and the base end of the bit line BLj, BLj in the redundant cell area 3.
hMO3) Transfer gates Trl to Tr4 composed of transistors are interposed in series to connect common buses CB and C.
B transfer gates T rl, T r2 and bit line BLj.

BLj transfer gate T r3. T r4
By inputting complementary output signals (JD, JI) from the redundant ROM as gate signals, either the normal cell area 2 or the redundant cell area 3 is selected.

With this configuration, the H level output signal JD is input from the redundant ROMII to the transfer gates T rl and T r2, and the transfer gate T r3゜T
When an L level output signal JD is input to r4, the common buses CB, CB are connected to the data buses DB, DB, and data can be read and written to the selected memory cell in the normal cell area 2. When the redundant ROMII output signals JD and JD are inverted, the common bus CB, σ■
and data bus DB.

The connection with DB is cut off, and the bit lines BLj, BLj of the redundant cell area 3 and the data bus DB.

The DB becomes connected and data can be read from and written to the selected memory cell in the redundant cell area 3.

Therefore, the redundant address match signal output from the redundant ROM II is directly output to the transfer gates Tr1 to Tr4 in the cell area 1 without going through the column decoder 4. There is no need to delay the operation, and as a result, the operating speed of the SRAM can be improved.

[Problem to be solved by the invention]

However, in the SRAM shown in FIG. 5 above, the common bus CB
, a transfer gate Trl in series with the σ stone,
Since Tr2 is interposed and data writing and reading are all performed through transfer gates T rl and T r2, the transfer gate Tri.

Tr2 becomes the resistance component of the common buses CB and CB. Therefore, common buses CB and C for memory cells in normal cell area 2
When writing and reading are performed via the common bus CB, the rise and fall speeds of the write data or read data decrease based on the resistance component and the time constant due to the parasitic capacitance under the common bus CB, and as a result, the operating speed decreases. There was a problem in that the value decreased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that has a redundant function but does not reduce its operating speed.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention. That is, when a preset redundant address is selected, the redundant cell selection circuit 11 selects a memory cell in the redundant cell area 3 instead of a memory cell in the normal memory cell area 2 corresponding to the redundant address. In a semiconductor memory device with a normal cell area 2
A transfer gate Trj) is provided for each bit line BLD, BLD in the redundant cell area 3, and a transfer gate Trj) is provided for each bit line BLj,
A transfer gate Trj is provided in Lj, and each of the transfer gates TrD and Trj is driven to open and close by complementary output signals JD and JD from the redundant cell selection circuit 11.

[Effect]

Complementary output signals JD and JD of the redundant cell selection circuit 11 are used to transfer the normal cell area 2 and the redundant cell area 3)T
Either rD or Trj is selected and turned on, and either the memory cell in the normal cell area 2 or the memory cell in the redundant cell area 3 is selected.

〔Example〕

An embodiment embodying this invention is shown in FIGS. 2 and 3 below.
This will be explained according to the diagram. Note that the same components as those in the conventional example will be described with the same numbers.

The SRAM shown in FIG. 2 selects a column based on the output signal of the redundant ROMII by inputting the output signal of the redundant ROMII to the column selection gate 5 via the inverter 15 and directly inputting it to the redundant column selection gate 6. This embodiment differs from the conventional example only in that complementary signals JD and JD are input to the gate 5 and the redundant column selection gate 6.

That is, as shown in FIG.
The output signal JD of the redundant ROMII is input to rj, and the bit lines BLD and BL of each column in the normal cell area 2 are input to rj.
Column selection transfer game interposed in D) T
Redundancy selection transfer gates TrD are connected in series to r5 to Trn, respectively, the output signal of the column decoder 4 is input to the column selection transfer gates Tr5 to Trn, and the redundancy selection transfer gate t-TrD is connected in series. an output signal of the inverter 15;
JD is input.

With this configuration, the redundant ROM II is in a state where the redundant address match signal is not output, that is, the redundant ROM
When an L level signal is output from II, normal cell area 2
Since an H level signal is output from the inverter 15 to the redundancy selection transfer gate TrD of the column, and an L level signal is input to the transfer gate Trj of the redundant cell area 3, the redundant cell area 3 is not selected and the column A predetermined column within the normal cell area 2 is selected by the output signal of the decoder 4.

On the other hand, when an H level signal is output from the redundant ROMII, an L level signal is outputted to the redundant selection transfer gate TrD in the normal cell area 2 via the inverter 15, and an L level signal is output to the transfer gate Trj in the redundant cell area 3. Since an H level signal is input, the column in the normal cell area 2 is not selected regardless of the output signal of the column decoder 4, but the column in the redundant cell area 3 is selected.

Therefore, in this SRAM, complementary output signals JD, JD from the redundant ROMII and the inverter 15 are applied to the bit lines BLD, BLD, BLj,
Redundant selection gates TrD and Trj interposed in BLj
Since it is input directly to the column decoder 4, there is no need to delay the operation of the column decoder 4, and there is no need to interpose a transfer gate between the common buses CB and CB.
Since the bit lines BLD and BLD are directly opened and closed at D, the data of the defective cell in the normal cell area 2 will not be read out by mistake.

Further, the transfer gate TrD formed on each bit line BLD, B'T in the normal cell region 2 is connected to the same bit line BL.
Since it is formed by adding a gate electrode on the diffusion region forming the column selection transfer gates Tr5 to Trn formed in D and BLD, it does not reduce the degree of integration of this SRAM.

Furthermore, even if the cell area 1 is divided into a large number of blocks and redundancy is performed for each block, if the output signal of the redundant ROM 11 is input to each block and the above operation is performed, the column Redundant operation can be performed for each block without providing the decoder 4.

〔Effect of the invention〕

As described in detail above, the present invention exhibits an excellent effect of preventing a reduction in operating speed while providing a redundant function in a semiconductor memory device.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of an embodiment embodying the invention, Fig. 3 is a circuit diagram showing a cell area of one embodiment, and Fig. 4 is a conventional example. FIG. 5 is a circuit diagram showing a cell area of a conventional example. 2 is a normal cell area, 3 is a redundant cell area, 11 is a redundant cell selection circuit, TrD, Trj are transfer gates, JD, J
D is a complementary output signal. In the figure, Figure 2 is a block diagram showing a conventional example.

Claims (1)

[Claims] 1. When a preset redundant address is selected, a redundant cell selects a memory cell in the redundant cell area (3) instead of a memory cell in the normal memory cell area (2) corresponding to the redundant address. A semiconductor memory device equipped with a selection circuit (11), in which each bit line (BL) in a normal cell area (2)
D, ■■■) is provided with a transfer gate (TrD), and the bit line (BLj, ■■■) of the redundant cell area (3) is
A semiconductor memory device characterized in that a transfer gate (Trj) is provided, and each transfer gate (TrD, Trj) is driven to open and close by a complementary output signal (JD, ■■) from a redundant cell selection circuit (11). .