JPH0410149A - Multi-cpu system - Google Patents

Abstract

PURPOSE:To reduce the processing of software by providing a CPU detecting means, which detects the CPU never requesting the use of a bus till then, and a CPU existence discriminating means which discriminates the existence of the CPU based on the detection result. CONSTITUTION:A multi-CPU system is provided with plural CPUs CPUm (m=0 to n), a bus arbiter 21, busses 12 and 13, etc. A bus use request detecting circuit 41 and a CXPU existence discriminating parts 51m of CPUs CPUm are provided as CPU detecting means. The bus use request detecting circuit 41 consists of a D-FF, and the bus request signal from each of CPUs CPUm is stored. Trhat is, the bus use request detecting circuit 41 has the on-bit output for each of CPUs CPUm, and its initial value is '0', and outputs '1' for the CPU which issues the bus request signal once or more. Each of CPUm reads data of the bus use request detecting circuit 41 and judges that the CPU corresponding to bit '1' does not exist.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a multi-CPU system that determines whether each of a plurality of CPUs exists or does not exist at a predetermined location.

(Prior Art) Conventionally, in a multi-CPU system, there have been two methods shown below as methods for determining whether each CPU exists or not.

First, in the first method, a setting pin is provided corresponding to each CPU, and the existence or non-existence of the CPU is determined based on the 0N10FF of this setting pin.

Next, the second method is to provide one interrupt signal for each CPU in advance, and use an interrupt processing program to generate an interrupt for the CPU whose presence or absence is to be determined. Set to process specific bits. and the CPU where the interrupt occurred
Then, after a certain period of time has elapsed, the existence or non-existence of each CPU is determined by checking the specific bit of the specific address set in advance.

(Problem to be Solved by the Invention) However, in the method of determining the presence or absence of each CPU using the first setting pin, the tester observes which CPU is mounted and sets the pin. However, there is a problem in that a pin setting error may occur, and there is a risk that a circuit formed by the setting pins may malfunction.

In addition, in the above-mentioned second determination method using an interrupt processing program, an interrupt is provided for each CPU, a specific bit of a specific address is manipulated, and after a certain amount of time has elapsed,
There is a problem in that the processing becomes very complicated, such as checking the specific bit of the specific address set in advance, and the software processing increases.

Therefore, the present invention determines the presence or absence of each CPU by
It is an object of the present invention to provide a multi-CPU system that can perform processing without human intervention and without increasing software processing.

(Means for Solving the Problems) In order to solve the above problems, the present invention eliminates the use of a bus even once in a multi-CPU system that determines whether a plurality of CPUs exist or do not exist at predetermined locations. The present invention is characterized by providing a CPU detection means for detecting a CPU that is not requested, and a CPU presence determination means for determining whether or not a CPU exists based on the detection result of the CPU detection means.

(Operation) According to the above configuration, the CPU detection means detects a CPU that has never requested the use of the bus. In this case, the CPU detecting means may manually store bus use request signals and bus use signals output by each CPU, and detect CPUs that have never requested use of the bus. It also manually memorizes the bus use permission signal output from a so-called bus arbiter that arbitrates the right to use the bus.
A CPU that has never requested use of the bus may be detected.

Based on the detection result of the CPU detection means, the CPU presence determination means determines that, for example, a CPU that has never requested the use of the bus is not present.

Therefore, the presence/absence of the CPU can be detected by the CPU detection means and the CPU detection means.
Since the determination can be made using hardware using the PU presence determining means, software processing is reduced.

(Embodiment) Hereinafter, an embodiment of the multi-CPU system according to the present invention will be described based on the accompanying drawings.

In the multi-CPU system of this embodiment, as shown in Fig. 1, a plurality of CPUs (m = 1 to n) operate in parallel, and each CPU m shares common resources (memory, various controllers, etc.). It is called a resource-sharing type tightly coupled multiprocessor system that is connected so that it can be accessed via an address bus 12 and a common data bus 13.

As shown in the figure, the multi-CPU system of this embodiment has a bus arbiter 2 that arbitrates the use of the bus for each CPU.
1, an address decoder 31 that decodes the address signal output from each CPU and outputs a select signal (tete) for selecting a memory and data storage location based on the address, and a bus used as a CPU detection means. It has a request detection circuit 41, and a CPU in each CPU.
A CPU existence determination section 51 is provided as a U existence determination means.

The path arbiter 21 receives a bus use request signal (BR,) output from a certain CPU (0<■ i<n), and based on the bus use request signal (BR,), the CPU,
and send the bus permission signal (BG,) and bus busy signal (BB,) to allow that CPU to use the bus.
This outputs the following.

At this time, the path arbiter 21 sends a bus use request signal (■π
) in the order received or in advance for each CPU.

CPU based on the priority set
The bus use permission signal (BG
) to output.

As shown in FIG. 2, the bus use request detection circuit 41 of this embodiment includes a signal inverter 42 that inverts the bus use request signal (100π) manually inputted from each CPU, and Required to use the bus
D flip-flop (hereinafter referred to as D-FF) 4 whose CLK input is the m-required signal (BRn)
3, and a three-state driver 44 which receives the signal output from the DFF 43 and outputs data D corresponding to each CPU to the common data bus 13 using the select signal input from the address decoder 31 as control power. As shown in the figure, in this D-FF43m, a +5V human power signal is always input to the 0 human power input, a reset signal (RESET) is input to the CLR human power input, and a +5V input signal is always input to the PR2 human power input. It is set not to be preset while inputting.

Furthermore, a CPU presence determination unit 51 provided in each CPU
is the logical product of the data register 52 that stores the data output from the memory space use request circuit 41 via the common data bus 13, the data D stored in the data register 52, and "1".
m, and based on the result, each CP
It has an existence determination circuit 53 that determines the existence/absence of U.

Next, the operation of this embodiment will be explained using the timing chart shown in FIG.
This will be explained with reference to the flowchart of FIG. 4 showing the process of U. However, in Figure 1, from CPU to CPU
CPUkl n-1 (k=0-n-1) up to and including the CPUkl exists in a predetermined location,
The following explanation assumes that there are no CPUs, and that through arbitration by the bus arbiter 21, first the CPUo acquires the right to use the bus, and then the CPU1 acquires the right to use the bus. Note that in the timing chart shown in FIG. 3, the shaded area is a don't care area.
This indicates that the status can be either "0" or "1".

When you first turn on the power to this system, a reset signal (R
F:SET) becomes true, this reset signal is input to the CIR input of each D-FF 43 of the bus use request detection circuit 41, and each D-FF 43m is reset as shown in FIG. The output of is “0” (TO
).

After the power is turned on, the reset is canceled after a certain period of time has elapsed (T1). At this time, since CPUk is mounted at a predetermined location, it outputs the bus use request signal (BRk) as true, that is, "0", and requests the use of the bus (T2
). On the other hand, since CPUn is not implemented, CPUk
The bus use request signal (■1.) output by is always false, that is, "1" due to the pull-up resistor (T2).

When the bus use request signal (B R, , ) of the CPUk is input to the signal inverter 42k in the bus use request detection circuit 41 in the state of "0", it is inverted and the CL signal to the D-FF 43 is inputted.
The K input is always "1" (T3).

On the other hand, the bus use request signal (ππ) of the CPU is n
Since n is always "1", it is input to the signal inverter 42 and is inverted.
0", and the CLK power of D-FF43 is always "0".
” (T3).

Next, the D-FF43 captures the state of the D input at the rising edge of the input signal to the CLK input, stores the zero input state, and outputs it until the next input signal to the CLK input, and uses the bus. Detect whether a request has been made even once.

In other words, since "1" is always input to the D input of each D-FF43, even if "0" or "1" is subsequently input to the CLK input, the state of the Q output is not stored in the D-FF43. “
1” (T4), bus use request signal (B Rk
') is entered at least once.

On the other hand, D-FF43 takes in 0 human power data at the rising edge of the CLK human power signal, but since the CLK input of D-FFn is always "0", D-FF43. The output from the Q output remains reset and is always “0” (T4), and the bus request signal (π ball
) detects things that require no human effort.

Next, when each CPU accesses the address of the bus use request detection circuit 41 (T5), the address decoder 3
1, the select signal (C8) becomes true, and the three-state driver 44 is controlled manually.

Each three-state driver 44 receives a select signal (U3
) is input, it becomes an output state, and the Q of each -FF43m
The output state is output to each bit D of the common data bus 13 (T6).

In other words, D-FF43□. Since the state of the Q output of D-F is "1", "1" is output to Dl (f! I), that is, D1 to Dn-1, which are output to the common data bus 13.
Since the state of Q output of F43 is “0”, D is “
0” is output.

Therefore, “1”, “1”, etc. are transmitted via the data bus 13.
・Data D of “0” is not installed on the CPU
(input to each CPUk and stored in the data register 52k of each CPU (STI)).

Then, CPU1-presence determination circuit 53. However, the data register 52,. Read data Dm from
and "1", and the result is stored in the data register 52 again (ST2). And each CPU
lc existence determination circuit 53. determines the presence/absence of the CPU based on the above results stored in the respective data registers 52k (5T3), CPU1 to CPUn-
For 1, Dk of the corresponding bit is “1”
Therefore, it can be determined that it exists (5T4), CPU
Regarding n, since the corresponding bit D is "0", it is determined that it does not exist (S T 5).

Therefore, each CPUk other than the CPU recognizes a CPU that is not installed in a predetermined location, that is, a CPU that does not exist, by the respective CPU presence determination unit 53k, and
C, PUo, and C under the arbitration of bus use by the bus arbiter 21 while sharing the work with C, PUo, and C.
Common address bus 12 and data bus 13 in the order of PU1
You can use them to perform your own processing.

Therefore, according to this embodiment, in a multi-CPU system, the CPU detecting means inputs and stores the bus use request signal output from each CPU, and detects which CPU has never requested the use of the bus. Since each CPU determines the presence/absence of other CPUs based on the detection result, software such as an interrupt processing program is no longer required, reducing software processing and processing of the entire system. It can be made faster.

Furthermore, in this embodiment, each CPU automatically determines the presence/absence of other CPUs without human intervention, so human errors are eliminated and the processing of the entire system becomes more accurate.

In the above embodiment, the CPU usage request detection circuit is connected to each CPU.
Manually memorize the bus use request signal output from U,
Although the present invention detects which CPU has never requested the use of the bus, the present invention also detects the right to use the bus by inputting and storing the bus-in-use signal output by each CPU. By manually storing the bus use permission signal output from the path arbiter that arbitrates, it is also possible to detect whether the bus has never been requested to use the bus (J'U).

In addition, in this embodiment, a CPU presence determination unit is provided in each CPU in hardware, but in the present invention, the presence/absence of a CPU is determined in software by a microprogram having the same function as the CPU presence determination unit described above. You can do it like this.

Furthermore, the CPU presence determination unit of this embodiment detects each CPU from the bus request detection circuit sent via the common data bus.
Store the data corresponding to in the data register, and “
However, in the present invention, for example, the data stored in the data register is once shifted to the right by n bits, and the data is logically ANDed with "1".
Alternatively, the presence/absence of the CPU may be determined based on the data without performing a logical AND with "1" on the data stored in the data register.

(Effects of the Invention) As explained above, according to the present invention, in a multi-CPU system, the CPU detection means detects which CPU has never requested the use of the bus, and based on the detection result, each CPU Since the CPU determines the existence or non-existence of other CPUs, software such as an interrupt processing program is not required, and the processing of the entire system can be speeded up by reducing software processing.

Furthermore, in the present invention, each CPU automatically determines the presence/absence of other CPUs without human intervention, so human errors are eliminated and the processing of the entire system becomes more accurate.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing the multi-CPU system of this embodiment, and FIG. 2 is a bus use request detection circuit 4 of this embodiment.
1 is a detailed functional block diagram of FIG. 1, FIG. 3 is a timing chart showing the states of signals in the bus use request detection circuit of this embodiment, and FIG. 4 is a flowchart showing the processing of each CPU in this embodiment. 12...Common address bus 13...Common data bus 41...Bus use request detection circuit (CPU detection means) 51...CPU presence determination unit (CPU presence determination means)

Claims (1)

[Claims] 1. In a multi-CPU system that determines whether each of a plurality of CPUs exists or does not exist at a predetermined location, a CPU that detects a CPU that has never requested the use of a bus.
A multi-CPU system comprising: a PU detecting means; and a CPU presence determining means for determining whether or not a CPU exists based on the detection result of the CPU detecting means.