JPH04101148U - serial data transmitter - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a serial data transmitting device that does not require special programming operations and has small-scale hardware. [Configuration] A reference clock generation circuit 1 that generates a clock that serves as a reference for the speed at which serial data is transmitted, a memory circuit 3 that stores data to be transmitted in the order in which it is output, and a memory circuit that generates a clock that is used as a reference clock each time a reference clock is input. 3, and a latch circuit 4 that temporarily holds and outputs data from the memory circuit 3 in response to a reference clock.

Description

[Detailed explanation of the idea]

0001

[Industrial application field]

The present invention relates to a control device for equipment using serial data transmission, and in particular to a device controlling device using serial data transmission. The present invention relates to a data transmitting device.

0002

[Conventional technology]

Conventionally, serial data was used to control various terminal devices by transmitting serial data. As shown in Figure 2, the data transmitting device includes a microprocessor 21 and a memory circuit. It consists of a circuit 22, a reference clock generation circuit 23, and a serial data transfer controller 24. It is. The reference clock generation circuit 23 is connected to the microprocessor 21 and serial data transfer. A clock for operating timing of the controller 24 is generated. The microprocessor 21 was previously stored in the memory circuit 22. Data to be transmitted operated by a program and stored in advance in the memory circuit 22 It reads out and sends it to the serial data transfer controller 24, and also displays this data in the diagram. The serial data transfer controller 24 controls the operation of the serial data transfer controller 24 in order to transfer the data to a terminal device that is not available.

0003

[Problem that the idea aims to solve]

The conventional serial data transmitting device shown in FIG. 2 includes a microprocessor 21 and a serial Since the configuration is equipped with a data transfer controller 24, the scale of the hardware can be reduced. It has the disadvantage of being large. Furthermore, in order to transmit serial data, the microprocessor 21 is operated. There was a problem in that it required a lot of programming man-hours and knowledge.

0004 Therefore, the purpose of the present invention is to create a small-scale program that does not require any special programming operations. We provide a serial data transmitter that can transmit serial data using hardware. There are many things.

[0005]

[Means to solve the problem]

Therefore, in order to achieve the above objectives, the present invention provides a A reference clock generation circuit that generates a clock that serves as a reference for the a counter circuit that generates a read address that changes sequentially as the time passes; A memory circuit that outputs data based on the read address generated by the A latch that temporarily holds and outputs data from the memory circuit according to the clock. It is equipped with a circuit.

[0006]

[Effect]

According to the present invention, data to be transmitted is stored in advance in the memory circuit. , the counter circuit sequentially changes the read address every time a clock is input. Therefore, the counter circuit changes the read address according to the clock input. It becomes possible to read data from the memory circuit in the desired order, and the microprocessor There is no need to use a processor or serial data transfer controller, and no special programming is required. It solves the problem of large hardware without requiring any programming operations.

[0007]

【Example】

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of the serial data transmitting device of the present invention. A reference clock generation circuit 1 that generates a clock that serves as a reference for the transmission speed of the A counter circuit 2 that generates addresses and a memo that stores data to be sent in advance. It is composed of a recircuit 3 and a latch circuit 4.

[0008] Next, the operation will be explained. The counter circuit 2 is predetermined in the memory circuit 3. In order to generate read addresses corresponding to data stored in sequence, the basic Read address every time the clock output from quasi-clock generation circuit 1 is input are changed sequentially. The memory circuit 3 transmits data as serial data according to the order in which it is output. is stored in advance and corresponds to the read address given from counter 2. The data is read out and output to the latch circuit 4. The latch circuit 4 is a counter circuit in response to the clock from the reference clock generation circuit 1. At the same timing as 2, the data from memory circuit 3 is temporarily held and a terminal (not shown) Output to device. This latch circuit 4 has the value of the data output from the memory circuit 3. The output may become unstable at the address change point, so the memory circuit 3 The value when the data output is fixed is maintained, and unstable values are not output. It is designed to do this. Note that the counter changes depending on the period of the clock from the reference clock generation circuit 1. The read address of the data circuit 2 corresponds to the data read cycle from the memory circuit 3. Therefore, this clock period corresponds to the serial data transmission speed.

[0009]

[Effect of the idea]

As explained above, the present invention stores data to be transmitted in the order in which it is output. data stored in the memory circuit each time the reference clock is input. A counter circuit that generates the same read address as the order is provided, so the micro There is no need to use a processor or serial data transfer controller, so there is no need for a special program. This eliminates the need for logging operations and has the effect of reducing the scale of hardware.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a serial data transmitting device of the present invention.

FIG. 2 is a block diagram showing an embodiment of a conventional serial data transmitting device.

[Explanation of symbols]

1,23 Reference clock generation circuit 2 Counter circuit 3,22 Memory circuit 4 Latch circuit 21 Microprocessor 24 Serial data transfer controller

Claims (1)

[Scope of utility model registration request] 1. A reference clock generation circuit that generates a clock serving as a reference for the speed of transmitting serial data, a counter circuit that generates a read address that sequentially changes in accordance with the clock, and a read address generated by the counter circuit. A serial data transmitting device comprising: a memory circuit that outputs data based on an address; and a latch circuit that temporarily holds and outputs data from the memory circuit in response to the clock.