JPH0410055A - Digital signal processor - Google Patents

Abstract

PURPOSE:To shorten a processing time when multiplying the value of a digital signal data by plural coefficients by connecting the output of the multiplying means of a second arithmetic part to the input of one digital signal data of the multiplying means of a first arithmetic part. CONSTITUTION:The first and second arithmetic parts are respectively composed of digital multiplying means 13 and 18, which multiply the values of the two digital signal data, and digital accumulating means 14, 15, 19 and 20 to accumulate the output values of these multiplying means 13 and 18, and the output from the multiplying means 18 of the second arithmetic part is connected to the input of one digital signal value to the multiplying means 13 of the first arithmetic part. Thus, when multiplying the value of the signal data by plural coefficients, the time for processing can be shortened by reducing the number of program steps for transferring the data in the middle of the processing.

Description

DETAILED DESCRIPTION OF THE INVENTION BACKGROUND OF THE INVENTION The present invention relates to a digital signal processor (hereinafter referred to as DSP).

BACKGROUND ART An audio signal processing device capable of controlling a sound field in order to create reverberation and a sense of presence in an acoustic space such as a concert hall or a theater at home or in a car is known, for example, as disclosed in Japanese Patent Laid-Open No. 72615/1983. It is shown in the official gazette. Such an audio signal processing device performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner.
SP is provided. The DSP includes an arithmetic unit that performs arithmetic processing such as four arithmetic operations, a data RAM that stores digital audio signal data supplied to the arithmetic unit, and digital coefficient signal data (hereinafter simply referred to as coefficient data) to be multiplied by the audio signal data. Coefficient RAM that stores
Equipped with memory such as. The DSP is configured to transfer signal data between each memory and from the memory to an arithmetic unit according to a predetermined program so that arithmetic processing of signal data can be repeatedly performed at high speed. Further, the program is written in a rewritable program memory such as RAM in the DSP, and the program is changed by a microcomputer outside the DSP each time the sound field mode is switched by operation. In other words, by changing the program, you can create any acoustic space.

A conventional DSP is provided with buffer memories 1 and 2, a multiplier 3, an ALU 4, and an accumulator 5, as shown in FIG. Further, a signal data RAM 6 for storing input digital signal data and a coefficient data RAM 7 for storing a plurality of coefficient data are provided. During calculation, signal data is read from the signal data RAM 6 and supplied to the buffer memory 1 via the bus 8 and held therein, and coefficient data is sequentially read from the coefficient data RAM 7 at predetermined timing and stored in the buffer memory 2. Supplied and retained. The value indicated by the data held in the buffer memory 1.2 is multiplied by the multiplier 3. The multiplication result by the multiplier 3 is added to the value held in the accumulator 5 by the ALU 4 and is held in the accumulator 5. This ALU4 and accumulator 5
form the accumulating means. Also, accumulator 5
The held output of is connected to the buffer memory 1 and the signal data RAM 6 via the bus 8, so that the held data is transferred.

In such a conventional DSP, the operation of multiplying and accumulating a signal data value by two coefficient data values is a coefficient b that changes as the program progresses.

is a fixed coefficient. In this case, first, al Xl
is calculated by the multiplier 3, and the calculated al
It is transferred to buffer memory 1 via U4, accumulator 5, and bus 8, and alX1b1 is calculated by multiplier 3. At this time, the ALU 4 performs an operation of adding 0 to the multiplication result by the multiplier 3. calculated a
lbl xl is held in accumulator 5. Next, a2 x2 is calculated by multiplier 3, and the calculated a2
x2 is ALU4, accumulator 5, and bus 8
is transferred to buffer memory 1 via a2 x2 b
2 is calculated by the multiplier 3. al bl xl held in ALU4 and calculated a2 b2 x2
are added in the ALU 4 and held in the accumulator 5. However, in conventional DSPs that repeat such operations, there is a problem in that in the case of multiplication, the number of steps in the program increases and processing time is required.

Summary of the Invention [Object of the Invention] An object of the present invention is to reduce processing time in the case of an operation in which a signal data value is multiplied by a plurality of coefficients.
It is to provide SP.

[Structure of the Invention] The DSP of the present invention comprises first and second digital multiplication means for multiplying the values of two digital signal data, and digital accumulation means for accumulating the output value of the multiplication means.
A digital signal processor equipped with an arithmetic unit, and a second
The present invention is characterized in that the output of the multiplication means of the arithmetic section is connected to one digital signal data input of the multiplication means of the first arithmetic section.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the DSP which is an embodiment of the present invention shown in FIG.
Two calculation units are provided. The first calculation section includes buffer memories 11 and 12, a multiplier 13, an ALU 14, and an accumulator 15.

The outputs of the buffer memories 11, 12 are each connected to a multiplier 13. The output of the multiplier 13 is connected to one input of the ALU 14, and the output of the ALU 14 is connected to the accumulator 15. Accumulator 15 has two outputs, one output being connected to one input of ALU 14 and the other output being connected to bus 10 . Note that the buffer memory 12 has three inputs.

Further, the second calculation section includes buffer memories 16 and 17, a multiplier 18, an ALU 19, and an accumulator 20,
It is configured similarly to the first arithmetic unit.

However, the multiplier 18 of the second calculation section has two outputs, one output is connected to one input of the ALU 19, and the other output is connected to one input of the buffer memory 12.

The coefficient data RAM 21 contains coefficient data b1゜b2+ ・
...bn is stored, and the output of the coefficient data RAM 21 is connected to the buffer memory 11.

Signal data RAM 22 is connected to the other input of buffer memory 12. Further, coefficient data al+ a2+ . . . afi are stored in the coefficient data RAM 23, and the output of the coefficient data RAM 2B is connected to the buffer memory 16. Signal data RAM 24 is connected to buffer memory 17.

Signal RAM 21.24 and buffer memory 12.17 are also connected to bus 10.

In addition, three inputs of the buffer memory 12, two inputs of the buffer memory, two outputs of the multiplier 18 and accumulators 15 and 20, and two of the signal data RAMs 22 and 24.
One of the two outputs is selectively valid. These are configured, for example, by a switching circuit consisting of a plurality of three-state buffers and the like.

Reading operation of coefficient data from RAM21 and 23,
readout operation of signal data from RAMs 22 and 24;
Arithmetic operations of ALUs 14 and 19, accumulator 15.
Operations such as the output selection operation of the held data 20 and the output selection operation of the multiplier 18 are performed by the sequence controller (
(not shown). The sequence controller operates according to a program written in a program memory (not shown) within the DSP.

In a DSP having such a configuration, audio signal data X supplied from the outside. is written into a predetermined area of the signal RAM 24. When performing the operation ΣanbnXn in which two coefficient data values are multiplied by a signal data value and accumulated, first, in a first step, signal data x1 is read out from the signal data RAM 24 and supplied to the buffer memory 17. Ru. On the other hand, the buffer memory 16
Coefficient data a1 is read out from the coefficient data RAM 23 and supplied to. Therefore, the multiplier 18 receives the signal data X
1 and the value of coefficient data a1 are multiplied. The value Xl_al of the multiplication result by the multiplier 18 is supplied to the buffer memory 12 from the other output in a second step one step after the first step. In this second step, coefficient data b1 is read out from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, multiplier 13
multiplies Xl al by the coefficient data value b1.

The value a1b1x1 of the multiplication result by the multiplier 13 is sent to the accumulator 15 via the ALU 14 in the third step.
is maintained.

Further, in the second step, signal data x2 is read out from the signal data RAM 24 and supplied to the buffer memory 17. On the other hand, coefficient data R is stored in the buffer memory 16.
Coefficient data a2 is read out from AM23 and supplied. Note that since the reading of signal data and coefficient data is performed sequentially for each step, the reading of x2 and al is
This is done in the next step after the l and al reading step. Multiplier] 8 is the signal data value X2 and the coefficient value a2
Multiply by The value x2 of the multiplication result by this multiplier 18
al is supplied to the buffer memory 12 from the other output in the third step.

In this third step, coefficient data b2 is read out from the coefficient data RAM 21 and supplied to the buffer memory 11. Therefore, the multiplier 13 multiplies x2 al by the coefficient data value b2. The value a2 b2 x2 resulting from the multiplication by the multiplier 13 is supplied to the other input of the ALU 14 . In synchronization with this supply, the pig value al blxl held in the accumulator 15 is supplied to one input of the ALU 14 . Therefore, in the fourth step, the ALU
14 accumulates albl x1+a2 b2 x2, and the value of this accumulation result is held in the accumulator 15. By repeating such operations, in the case of n-6, the cumulative result is calculated in the eighth step. Note that the coefficient data a from the first step is stored in the coefficient data RAM 23.
++a2...an are sequentially read out step by step, and coefficient data bl is read from the coefficient data RAM 21 from the second step.

b2...bn are sequentially read out step by step.

Note that in the above embodiment, Σafi bnXf
Although the calculation of i has been described, the invention is not limited to this, and the present invention can be applied to other calculations as well.

Effects of the Invention As described above, in the DSP according to the present invention, the first and second channels each include a digital multiplication means for multiplying the values of two digital signal data, and a digital accumulation means for accumulating the output value of the multiplication means. A calculation section is provided, and the output of the multiplication means of the second calculation section is connected to one digital signal data input of the multiplication means of the first calculation section. Therefore,
In the case of an operation such as ΣanboXn in which a signal data value is multiplied by multiple coefficients, there is no need to transfer intermediate result data from the output of the accumulator to the multiplier via the bus during the operation, and the data can be transferred as digital signal data. Since the signal data and coefficient data of the present invention can be read out from the memory every step and efficient data processing can be performed, the number of program steps can be reduced compared to the conventional method, thereby shortening the processing time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a conventional DSP. Description of symbols of main parts 3.13.18 Multiplier 4.14.19 ALU 5.15.20 Accumulator Applicant Pioneer Corporation

Claims (1)

[Claims] A digital signal processor comprising first and second arithmetic units each consisting of a digital multiplication means for multiplying the values of two digital signal data and a digital accumulation means for accumulating the output value of the multiplication means, A digital signal processor characterized in that the output of the multiplication means of the two arithmetic units is connected to the digital signal data input of one of the multiplication means of the first arithmetic unit.