JPH0410010A - Nonlinear converting method for digital data and signal processor using said converting method - Google Patents

Abstract

PURPOSE:To decrease the quantity of data to be stored and to attain the high speed conversion of data by storing previously each coefficient of a linear equation connecting the points showing the nonlinear output data into a memory as the output data against the input data. CONSTITUTION:A function curve showing the nonlinear output data against the input data is approximately by a straight line connecting points having each input equal to 2<n-1> (n = 1-N). Then (a) and (b) in an equation y = aX + b showing each straight line are previously stored in a memory as the output data against the input data. Then these data (a) and (b) are read out of the memory and the equation y = aX + b is calculated for output of the conversion data. Thus it is possible to reduce the conversion error and the number of data and also to attain the high speed conversion of data with a small memory capacity and in a small number of program steps.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention relates to a method for nonlinear conversion of digital data to obtain nonlinear output data with respect to input data, and further relates to a method for converting audio signals using the data conversion method. The present invention relates to a signal processing device.

(b) Conventional technology In recent years, stereo systems have been developed that effectively realize three-dimensional sound field reproduction in movie theaters. Stereo devices have been developed that add surround channels to the rear of the left and right channels of conventional stereo devices, making it possible to reproduce a three-dimensional sound field even at home.

Furthermore, a more advanced surround stereo system has recently been announced that can produce a three-dimensional sound field reproduction effect almost equivalent to that of a movie theater. A major feature of this is that the audio signals of the left and right channels of the original sound are subjected to signal processing called directional enhancement to clarify the localization of the sound. In this method of reproduction, the left channel is created from the left and right audio signals, and a right channel R, surround channel S, and center channel C are created. Moreover, at that time, directional emphasis is added based on the level difference between the left and right signals.

FIG. 5 is a circuit block diagram of a signal processing device that performs directionality enhancement.

The audio signals of each channel L and R are input to a bandpass filter (1), and bands unnecessary for level detection are removed. From the output of the pantone filter (1), LR (surround channel S) and L+R (center channel C) signals are created by an addition and subtraction circuit (2). And the audio signal of each channel is
It is rectified by the full-wave rectifier circuit (3) and converted into voltages Lv, Rv, Sv, Cv indicating the level of each channel, and furthermore, the level of each channel Lv, Rv, Sv, Cv.
In the differential input logarithmic conversion circuit (4), the level difference of each channel, LvRv Cv Sv, is logarithmically converted. The logarithmically transformed level differences Lv-Rv and C-8v are integrated by an integrating circuit (5). The integrating circuit (5) is
The integration time constant is switched by a time constant switching circuit (6) that detects the speed of change in the level differences Lv-Rv and Cv-8v. Integrated level difference Lv Rv, CyS
v is determined by the four control signals EL by the polarity determination circuit (7).
, ER, Eo, and Es are created. That is, when R/L>1, a voltage corresponding to the integral value of LvRv is output to Et, and when R/L<1, a voltage according to the integral value of LvRv is output to E8, and, E if S/C>1. outputs a voltage according to the integral value of CvSv, and when S/C<1
In this case, a voltage corresponding to the integral value of Cv-Sv is outputted to E8. VCAI Voltage Condroldo Amplifier)
(8) amplifies the input left channel L and right channel R audio signals by amplifiers controlled by control signals EL, ER4Ec, and Es, respectively, and outputs eight signals. These eight signals and the left channel L and right channel R audio signals are added in an adder circuit (9) to create and output L, R, C, and S channel signals. This output becomes a directionally emphasized signal.

Regarding this technology, see Nikkei Electronics, 1988.
It is described in detail on pages 88 to 89 of June 27, 2015 (No. 450).

(C) Problems to be Solved by the Invention The audio signal processing device having directionality enhancement shown in FIG. 5 processes left and right channel audio signals input in analog form as they are in analog form.

However, recently, a DSP (digital signal processor) for audio signals has been developed, and it has become possible to easily perform processing such as a graphic equalizer and reverberation digitally without deteriorating the sound quality. That is, an analog audio signal is converted into a digital signal, this digital signal is processed to realize various sound effects inside the DSP, and the resulting digital output is converted back into an analog signal. Here, the sampling frequency of AD and DA conversion is 48KH2, 44, 1KH2 or 32KH2.
KH2 is used.

Therefore, it has been considered to use a DSP to realize an audio signal processing device with directional emphasis as shown in Fig. 5, but for example, for digital data input every 441KH2, Executing all the processes shown in FIG. 5 would require an enormous number of steps, making it difficult to implement. Or a DSP that operates at very high speeds
This requires high cost and makes it impossible to create an audio device that is acceptable to general consumers.

In addition, in order to realize the logarithmic conversion circuit (4) in FIG. Since the program step becomes very long and requires a lot of time, it is necessary to
This made it difficult to realize P.

On the other hand, there is a method of logarithmic transformation without performing approximate calculations. This method divides the input evenly, as shown in Figure 6,
This is a method in which converted values for each divided input are stored in a memory, and converted output data is obtained using the input data as an address. According to this method, all inputs within one divided range have the same output data, so the error from the true logarithmically transformed value becomes large. In particular, when the input is small, the error becomes large. Also, the error can be
In order to reduce the distance, the number of input divisions must be increased. However, as the number of input divisions increases, the amount of data increases, a large memory is required, and the memory usage efficiency deteriorates. This is a method of converting linear input data to nonlinear output data, in which a function curve representing nonlinear expansion specific force data with respect to input data is set to 2°−+(n=1.2, ・・ Approximate by a straight line connecting each point of N), and the equation representing each straight line, Y
= a This is a nonlinear data conversion method that reduces conversion errors, reduces the number of data, and can be realized with a small memory requirement and a small number of program steps.

(E) Effect According to the above-mentioned means, the output data for the input does not change stepwise, but the function curve is
Since the approximation is made by a straight line connecting each point of n=1.2-·Nl, the portions of the curve where the curvature is large are sampled finely, and the portions where the curvature is small are sampled largely. Then, the slope a of the straight line connecting each point and the data b of the height of the Y thin section are outputted as output data, whereby conversion data can be obtained by a simple calculation of Y=aX+su. Therefore, the error is the difference between the function curve to be converted and the polygonal line that approximates it.The error is much smaller than the error of output data that changes stepwise, and furthermore, 2t+
Since there is a relationship of -1, the maximum values of errors between each straight line and each curve are equal. Also, since the number of samplings is equal to the number of bits N of input data, the number of data decreases,
Data tables occupy less memory.

In addition, if the non-linear data conversion method is adopted in a signal processing device for audio signals with directionality emphasis to realize logarithmic conversion and anti-logarithmic conversion, the utilization efficiency of the memory built into the DSP will be increased, and the program The number of steps is also reduced, and an audio signal processing device with digital direction enhancement can be easily realized.

(F) Embodiment FIG. 1 is a graph for explaining the present invention in detail, and is an example of logarithmically transforming input data. input
A logarithmic curve is shown when the conversion data is taken as the Y axis. Starting from the intersection of the logarithmic curve and the X axis, 2
°, 2', 22.23... 2" (n=N-1:
The X-axis is sampled according to the relationship (N is the number of input data in focus), and points on the curve corresponding to each sampled input data are connected to approximate a logarithmic curve. Then, the slope a of the straight line connecting the two points on the curve corresponding to 20 to 21
, and Y thin slice S, are the output data of the input 20. Further, the slope a2 and the Y-slice b2 of the straight line connecting the two points on the curve corresponding to 21 and 22 are used as the output data of the input 21. Similarly, for each input 2'', the slope a and the Y thin intercept s are output data.Here, when the input data is N bits, the maximum value 2N of the input data is the output data. The output data on the Y axis is determined so that the maximum value Y expressed in bit number is 18.

In addition, in FIG. 1, each slope a and Y thin section are shown.

The relationship is ao=2al=4a2=...=2''
a m, and b, + b, -, =...=
b + - b 0 = h (constant), and according to this, if aO and h are memorized, each slope and Y thin intercept can be easily obtained by calculation.

The slope and Y-slice data obtained in Figure 1 are as follows:
1 stored in the memory with address N-n-1 for the input data. For example, for N; 16 bits, the slope a corresponds to 2°. The data of the Y thin slice b0 and Y are stored in the memory area whose address is 15, and the data of the slope al corresponding to 2' and the Y thin slice b0 are stored in the area whose address is 14, and in the same way. , 2 +5 and the Y thin slice b15 are stored in the memory area whose address is 0. The slope a memorized in this way. When extracting one Y thin slice, check which bit from the most significant bit of the input data has a '1'' as shown in the flow diagram shown in Figure 2.In other words, the most significant bit of the input data Determine whether the bit is 1'', II OI
When it is I, after incrementing the counter by 1, the input data is shifted by 1 bit in the direction of the upper bit. Then, it is determined again whether or not the topmost focus is at ``V''. At this time, if it is Bi, the input data is 2 + 4 + 21 (
l is less than 14), so the slope a1 corresponding to 214
4 and Y-axis intercept b14, address 1
All you have to do is access. That is, the count value of the counter can be used as address data.

Next, an audio signal processing device having directionality enhancement using the above-described data conversion method is shown in FIG. 3 and will be described.

In FIG. 3, (11) is a first block which receives left channel digital data LIN and right channel digital data RIM and operates at every sampling period 1/f3. (12) is a second block that inputs and processes the digital data output from the first block, and is a block that operates at a period N times the sampling period 1/fs. (+3) is the third block,
Like the first block, this block operates at every sampling period of 1/f8.

Each block will be explained in detail below.

The first block collects left channel digital data L1.1 and right channel digital data RI every sampling period 1/fs, e.g., f, = 44.1 KH.
Digital bandpass filters (14) each input with N
and an adder (15) that adds the outputs and R of the digital band pass filter (14) to create center channel data C;
), a subtracter (16) that creates surround channel data S by subtracting L−R from the eight values of
Digital high that inputs R, C, and S) < filter (1
7+, and a full-wave rectifier (18) for full-wave rectifying the output data of each digital bypass filter (17).

Here, the digital band pass filter (14) is for removing unnecessary frequency components for level detection of each channel, and is composed of three stages of continuously connected IIR digital filters, the first stage and the second stage. The digital filter in the third stage is a bypass filter with a cutoff frequency of 100H2, and the digital filter in the third stage is a low pass filter with a cutoff frequency of 5KH2.

Digital bypass filter (1) of the first block (11)
7), the cant-off frequency is set to 218 Hz.

Further, the full-wave rectifier (18) includes an absolute value calculation circuit and a digital low-pass filter with a cant-off frequency of 14H2. The absolute value calculation circuit detects whether the highest focus of the input digital data is '0' or '1', and if it is 'o', outputs the input digital data as is, and 1'', it works to full-wave rectify the input digital data by calculating and outputting the complement of the input digital data.This digital low-pass filter functions as an integrator for full-wave rectification. It functions as a filter to smooth the full-wave rectified output in the absolute value calculation circuit, and also acts as an anti-alias filter, so that when the second block operates at the sampling period N/fa, the output of the first block It also serves as a filter to prevent interference between the signal frequency and the sampling frequencies f and /H of the second block.

The second block (12) operates at a period N times the sampling period 1/f8. That is, sampling period 1/f
Since the output of the full-wave rectifier (18) that is output every time is the result of integration, the change in data is gradual, that is, the frequency is low, so the second block (12) that processes the output
) can lower the sampling frequency. In this embodiment, considering the output frequency of the full-wave rectifier (18),
/16 sampling frequency and 2.75KH are adopted.

Here, the second block (12) is a logarithmic converter (2) which inputs the digital data of each channel outputted from the first block every 16 pieces and logarithmically converts the digital data.
4) and the outputs Le, Re, Ce of each logarithmic converter (24)
, a subtracter (25) for calculating the level differences Le-Re and Ce-8e of Se, a level detector (26) for inputting Le-Re and Ce-3e, respectively, and
Digital low-pass filter (27) that inputs 3e respectively
a polarity discriminator (28) which inputs the outputs ELR and EC8 of the digital low-pass filter (27), and an antilogarithmic converter (2) which antilogarithmically transforms the output of the polarity discriminator (2B).
9) and a coefficient calculator (30) that calculates eight coefficients based on the output of the anti-logarithm converter (29).

Here, the logarithmic converter (24) performs logarithmic conversion according to the method shown in FIG. 1, and uses a ROM that stores slope data a and Y slice data b.

The level detector (26) has a digital low-pass filter with a cutoff frequency of 7H2, and has Le-Re and Ce
It is detected that the integral results of -3e are both below a predetermined value. Further, the digital low-pass filter (27) consists of a digital low-pass filter with a cut-off frequency of 0.34 Hz and a digital low-pass filter with a cut-off frequency of 7H2, and is configured to process level difference data Le-Re and Ce-
When both 3e are small (and the detection output is output from the level detector (26), the 0.34Hz and 7Hz digital Louvus filters are continuously connected, and otherwise the level difference data La-Re and Ce-9s are each applied to a 7H2 digital rhono Venue filter.

This second block (12) has a sampling frequency of 2
．． Since the frequency is as low as 75 KHz, the bit length of the filter coefficients of these digital low-pass filters can be kept to about 16 bits, and coefficient accuracy is ensured.

The polarity discriminator (28) includes a digital low-pass filter (28).
7) The polarity of each output ELR and ECS, that is, each output E
LR and EC8 determine whether it is positive or negative. For example, if E L'R is positive, -ELR is output to the output EL, and the other output ER' becomes 0. Conversely, when ELR is negative, O is output to EL' and E is output to ER''.
LR is output. The same applies to EC3.

The anti-logarithmic converter (29) performs anti-logarithmic conversion using the data conversion method shown in FIG. 1 in the same way as the logarithmic converter (24), but unlike the logarithmic curve shown in FIG. It is an anti-logarithmic curve for the input data. Then, using a ROM in which slope data a and Y slice data b are stored for the input data, the outputs EL', ER", ECo, and ES' from the polarity discriminator (28) are inverse logarithmically transformed. ,
Data EL, ER, EC, ES for directional emphasis
Create.

The coefficient calculator (30) uses data EL, ER, EC1ES
Eight coefficients are created to multiply the left channel digital data LHI and the right channel digital data RIM based on the constants LL and CL.

CR and RR are obtained by multiplying the data EL, ER, EC, and ES by respective predetermined constants, and adding the multiplication result to a predetermined constant.
The constants SL and SR are obtained by multiplying S by each predetermined constant and adding the multiplication results, and the constants SL and SR are the data EL.
, ER1EC are each multiplied by a predetermined constant, and the multiplication result is added to the predetermined constant.

The third block, like the first block, is a block that operates at the sampling frequency f, and the second block is a block that operates at the sampling frequency f.
Coefficient values LL, OL, RL, SL output from the block
a multiplier (43) that multiplies the right channel digital data RIM by the coefficient values LR, CR, RR, S, and R, respectively, and multipliers (43) and (44)
an adder (45) that adds the outputs of each to create digital data L', R', and C1S for each channel; and an adder (45) that inputs channel data C, removes the low frequency part, and outputs center channel data C0υ. The output data of the digital bypass filter (46) and the digital bypass filter (46) are subtracted from the channel data C° to obtain the low frequency part of the center channel, and this is added to the channel data L° and Ro to obtain the left channel digital signal. Data L.

U, a subtracter (47) and an adder (48) that output as right channel digital data ROIJT, a delay element (49) that delays channel data S°, and a high Surround channel digital data S by removing the area portion. It consists of a low pass filter (50) that outputs 0 filters. Here, the digital bypass filter (46) has a cut-off frequency of 10
0H, and the digital low-pass filter (50) is
The cant-off frequency is 7KH2.

Next, FIG. 4 shows an optimal SP for realizing the audio signal processing device with directional emphasis shown in FIG.
) (Bus 2) (511 and the data bus (Bus 1)
) (Bus2) f51) and the digital processing circuits (52) (53) connected to the data bus (BUSI
) (Bus2)+511 connected to the data input/output circuit (54), interface circuit (55), external-memory interface circuit (56), data exchange register (
57), a storage control register (58L) connected to the data bus (Bus2), a conditional branch control circuit (59), and a control circuit (60) connected to the data bus (Bus2) and controlling the operation of each of the circuits. This is a DSP system for audio signal processing, which is integrated on a single-chip semiconductor device.

The data bus (51) is composed of 24 pins of 8 bits x 3 each. The data input/output circuit (54) serially inputs 16-bit left channel and right channel sampling data applied externally to the input terminal IN, and the right channel data is input to the data bus BUSI, and the left channel data is input to the data bus BUSI. It receives and receives the processed data sent to the data bus BUS2, further sent to the data buses Bus1 and BtJS2, and serially outputs it from the output terminal OUT.

The data processing circuit (52) is for data processing of the right channel, and the data processing circuit (53) is for processing data of the left channel, and each has exactly the same configuration. That is, the data processing circuit f52) (53) includes a data RAM (61), constant RAM (621, constant ROM (63), address pointer f64) (65) f86), and a multiplier (MU
L:1 Fe2) A L U (68), accumulator (ACC) (69), temporary register (
TMPI to TMP8) (70). Data R
AM (6+1) has a capacity of 24 pints x 128 to store unprocessed data sent from the data input/output circuit (54) and data after arithmetic processing, and has a capacity of 24 pints x 128
1) and the input of the multiplier (67). constant RA
M (62) has a capacity of 16 bits x 256 to store the coefficients of the digital filter sent out from the interface circuit (55), and is connected to the data bus (51), the input of the multiplier (67), and Connected to the input of L U f[i8). In addition, the constant ROM (63) is a 24-bit memory that fixedly stores fixed multiplication coefficients for digital filters, data tables for logarithmic conversion and anti-logarithmic conversion, etc.)
X256 read-only memory, data bus (5
1) and the input of the multiplier (67).

The address pointer (64) is configured with 8 pins and specifies the address of the data RAM+81), and is configured by the microcode INCl output from the control circuit (60).
and DEC1. Also, the address pointer (
65) is a 10-bit pointer that specifies the address of the constant RAM (621), and is controlled by the microcode INC2 output from the control circuit (60).Furthermore,
The address pointer (66) is an 8-pin pointer that specifies the address of the constant ROMf83), and is controlled by the microcode DEC3 output from the control circuit (60).

The multiplier (67) multiplies 24 pins by 16 bits, the A input is 24 pins, the B input is 16 bits, and the multiplication result is determined after 1 cycle. Furthermore, input selection circuits MPXA and MPXB are provided at the A input and B input of the 1 multiplier (67), and the input selection circuit MPXA receives the microcode A from the control circuit (60).
-BUS selects the data bus (51), and microcode 1'A-DRAM selects the data RAM (611).
is selected and applied to the A input, and the input selection circuit MPXB is
The data bus (5j) is selected by the microcode B-BUS, and the constant RA is selected by the microcode B-ORAM.
M(621 is selected and the constant ROM(631 is selected and applied to the B input) by the microcode B-CROM. The 0 multiplication result is output in 32 bits.

ALU (68) is a 32-bit arithmetic circuit,
The 32-bit multiplication result input to one side and the 32-pin ACC (69) data input to the other side are added together using the microcode ADD, and the result is added to the ACC (69).
Transfer to (69). Of the 32 bits of the ACC (69), the upper 24 bits are connected to the data bus (51), and the lower 8 pins are connected to the lower 8 bits of the temporary register (0) by an auxiliary bus (71). The temporary register (70) is composed of 32-bit registers TMPI, TMP2n, and TMP8, and is a register that holds up to eight pieces of 32-bit data, and the upper 24 bits of each are connected to the data bus (51).

32 between temporary register (70) and ACC (69) by data bus (51) and auxiliary bus (71)
Bit data is transferred.

The control circuit (60) controls each section circuit according to a preprogrammed procedure, but it is also possible to control each section circuit of the data processing circuits (52) and (53) simultaneously or independently. This control circuit (60
) has a built-in program ROM (or RAM), and by executing the program read from the program ROM, the address pointer (64) (651 (6
8) Control lNCl, lNC2゜DECI, CLE
AR2, DEC3: A-Bus that controls input selection circuits MPXA and MPXB.

A-DRAM, B-Bus B-CRAM B
-CROM, ADD that controls ALU (68), TH
R, MD: CH that controls data exchange register (57)
G; ○VFR, 5 that controls the conditional branch control circuit (59)
IFR, CAFR, BOFR, storage control register (58
) is output.

The interface circuit (55) connects the DSP system and an external control device, such as a microcomputer (not shown).
It is used to send and receive data between.

The external memory interface circuit (56) is a circuit for specifying addresses and transmitting and receiving data to and from a memory externally connected to the DSP system.

When the signal processing device shown in FIG. 3 is realized using the DSP shown in FIG. , a digital bandpass filter (14) that filters the left channel and right channel digital data input after AD conversion is formed independently in each of the digital processing circuits (52) (531), and the output result is , to each of the digital processing circuits (52) and (53) using the data exchange register (57) of the DSP.From now on, basically, the processing of the left channel and the right channel is carried out by the digital processing circuit (52). The digital processing circuit (53) processes the center channel and surround channels.

Furthermore, in each of the digital processing circuits (52) and (53), when realizing the various digital filters shown in FIG. 3, multiplication of coefficients is performed by a multiplier (67), and addition and subtraction are Perform with A L U (68). That is, the digital data input to the filter is applied to the input A of the multiplier (67), the filter coefficient is read out from the constant ROM and applied to the input signal to perform multiplication, and then the data RAM (67) is
1) Read the data from one sampling ago and set the constant R.
Multiply the filter coefficient from OM (63) by multiplier (67). While repeating this multiplication, the multiplication results are output from the multiplier (67) and A L U (68) and A
Efficient (
Filter processing can be achieved.

The logarithmic converter (24) and the anti-logarithmic converter (29) store a logarithmic conversion table in the constant ROM (63) of one digital processing circuit, and store the logarithmic conversion table in the constant ROM (63) of one digital processing circuit, and the constant R of the other digital processing circuit.
This is achieved by storing an anti-logarithmic conversion table in the OM (63) and accessing each other's constant ROM (63).

Therefore, the operation according to the conversion method shown in FIG. 1 will be specifically explained with reference to the flowchart shown in FIG. 2. Data to be converted X,
is generated, the address pointer (66) is set with address data storing the slope and Y slice corresponding to the input data 215. Then, data X, is A
It is input to L U (68) and it is determined whether or not the highest focus is "1". If the result of the determination is "'1'', the constant ROM +
The result of 0 judgment when reading the slope data a16 and Y-axis intercept data bus stored in the address from 63+ is “0”
', the address pointer (66) is incremented, the input data input to the ALU is shifted by one pin in the direction of the upper bit, and the most significant bit is determined again. By performing similar operations until it is determined that the address pointer (
66) is address data for storing data corresponding to input data. The data read by the address pointer (66) is input to the ALU (68),
The shift function of the ALU (68) shifts the data down, leaving only the slope data a of the upper bits.The remaining slope data a is sent to the multiplier (6) via the ACC (69).
7) and applies the data X1 held in the data RAM (61+) to the input A of the multiplier (67) to start multiplication.0 While the multiplier (67) is performing multiplication. , the slope data a and the Y slice data b are stored in the constant ROM (
63) and input to the ALU (68). Then, using the mask function of ALU (68), mask the slope data a of the upper bits, hold only the Y thin slice data b of the lower focus in ACC (69), and
), that is, aX+ and the Y thin slice data b held in ACC (69) are added at ALU (68) to obtain converted data Y=aX1+b.

In this way, the slope data a and Y are stored in the constant ROM (63).
By storing the thin section data b, it is possible to calculate Y=aX, +b in extremely short steps.

Furthermore, since the amount of data for conversion is small, the constant RO
It is only necessary to use a part of M (63), and other data such as filter coefficients to be stored is not sacrificed.

(G) Effects of the Invention As described above, according to the present invention, the amount of data stored in the memory that serves as a table for data conversion is reduced, and calculations are performed based on data read from the memory. The number of program steps is small (
It is capable of high-speed data conversion. Furthermore, since conversion errors are significantly reduced, there is an advantage that highly accurate digital processing can be performed.

In addition, since the processing burden on the DSP can be significantly reduced, an audio signal processing device with directional emphasis, which was conventionally performed using analog processing, can be realized extremely easily and with high precision using digital processing using a DSP. be.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the present invention in detail, FIG. 2 is a flow diagram showing data conversion operation, FIG. 3 is a block diagram showing an audio signal processing device with directional emphasis, and FIG. 4 is a diagram showing a data conversion operation. FIG. 3 is a block diagram of a DSP suitable for realizing the audio signal processing device shown in FIG. 5, a block diagram showing a conventional example of the present invention, and FIG. 6 is a conventional data conversion method using a data table. FIG. (11)...First block, (12)...Second block, (13)...Third block, (14)...Digital band pass filter, (15)...Adder, ( 1
6)...Subtractor, (17)...Bypass filter,
(18+... Full wave rectifier, (24)... Logarithmic converter, (25)... Subtractor, (26)... Level detector, (27)... Digital low pass filter, (28
)... Polarity discriminator, (29)... Anti-logarithm converter, (
30)... Coefficient calculator, (43) (44)... Multiplier, (45)... Adder, (46)... Digital bypass filter, (47)... Subtractor, ( 48)
... Adder, (49) ... Delay element, (50) ... Digital low-pass filter.

Claims (4)

[Claims] (1) In a method of converting linear input data to nonlinear output data, the input is 2^n^-^1 starting from the point where the function curve representing the nonlinear output data for the input data intersects the X axis.
Approximate by a straight line connecting each point of (n=1, 2,...N),
A and b of the equation Y=aX+b representing each of the straight lines are stored in memory in advance as output data for the input data, and the data a and b corresponding to the input data are read from the memory and the equation Y= A method for nonlinear conversion of digital data, characterized by calculating aX+b and outputting converted data. (2) a and b stored in the memory are N-n-1
2. The digital data according to claim 1, wherein a and b are read out by specifying an address in the memory according to the number of bits that are first "1" from the most significant bit of the input data. Nonlinear transformation method. (3) Directionality is achieved by detecting the level ratio of the left channel signal and right channel signal, and the level ratio of the sum and difference of each channel signal, and amplifying or attenuating the level of each output channel based on the detection results. In a signal processing device for audio signals that performs enhancement, left channel and right channel digital data L and R to L+R and L- are input at every predetermined sampling period.
Calculate R, and calculate each digital data L, R, L+R, and
A first block that calculates each rectified value of L−R, and logarithmically transforms each rectified value calculated by the first block, and calculates the difference between L and R and the difference between L+R and L− from the logarithmically transformed output.
a second block that calculates the difference in R, performs antilogarithmic transformation on the calculation result, and creates a plurality of coefficients based on the antilogarithmic transformation; a third block that calculates directionally emphasized multi-channel output data by multiplying data L and R by the coefficients created in the second block; and logarithmic transformation of the first block. A signal processing device for an audio signal having directional emphasis, characterized in that the inverse logarithmic transformation of the second block and the second block is performed by the method according to claim 1. (4) Directionality is achieved by detecting the level ratio of the left channel signal and right channel signal, and the level ratio of the sum and difference of each channel signal, and amplifying or attenuating the level of each output channel based on the detection results. A signal processing device for audio signals that performs enhancement includes a digital bandpass filter that inputs digital data L and R of left and right channels that are input at every predetermined sampling period, and L+R and L from the output of the digital bandpass filter. a first block comprising an addition/subtraction means for calculating -R, and a full-wave rectification means for calculating the absolute value of each digital data L, R, L+R, and LR; and the first block. a logarithmic conversion means for logarithmically converting each of the absolute values calculated in , a level difference calculation means for calculating the difference between L and R and the difference between L+R and LR from the output of the logarithm conversion; A level detecting means for integrating each output with a first digital low-pass filter and detecting that the level has reached a predetermined level, and a time constant is controlled to switch according to the output of the level detecting means, and the output of the level difference calculating means is controlled by switching. a second digital low-pass filter for input;
polarity determining means for distributing the output according to the sign of the output of the second digital low-pass filter; anti-logarithm conversion means for inverse-logarithmically converting the output of the polarity determining means; and a plurality of coefficients based on the output of the anti-logarithm conversion means. a second block comprising a coefficient creating means for creating a coefficient, and a second block that multiplies the digital data L and R of the left channel and right channel input at each sampling period by the coefficient created in the second block. , a third block for calculating directionally emphasized output data of a plurality of channels;
^n^-^1 (n = 1, 2,...N) is approximated by a straight line connecting each point, and each a and b of y = a 1. A signal processing device for an audio signal having directional emphasis, characterized in that the device is a storage device in which a directional enhancement is stored.