JPH0399876A - Recording apparatus - Google Patents

Abstract

PURPOSE:To protect a line head sufficiently at the time of performing a multiple gradation picture recording by equipping a counting means for counting the number of strobing signals for every one line of picture records and a protection means for comparing the counted value with a reference value to detect driving abnormalities in a heating part to protect the line head. CONSTITUTION:When abnormality occurs, e.g. no strobe pulse comes out from a strobe pulse generator 27, a counter 30 outputs no counted-over signal CO because a counted values does not reach the counter and the inverted output signal of a flip-flop 31 does not lower to a low level because the flip-flop cannot be set. Therefore, the non-inverted output signal of a flip-flop 32 reaches a high level and is sent as an error signal to an OR circuit 28 so that the strobe pulse from the strobe pulse generator 27 is hindered by the OR circuit 28. That is, the output of the OR circuit 28 reaches a high level and the heating paper of a thermal head 29 is protected without application of excessive power to that part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording apparatus such as a printer or a copying machine that uses a line head such as a thermal head or an energized recording head.

[Conventional technology]

Japanese Unexamined Patent Publication No. 60-242077 discloses a recording device that records a binary image by applying a printing pulse to each heating section in a line head having a plurality of heating sections arranged in a line in accordance with binary data. A line head protection means is provided to protect the line head by detecting that the width of the printing pulse applied to the heat generating part of the line head exceeds the maximum printing pulse width and prohibiting energization to the line head. are listed.

[Problem to be solved by the invention]

In a recording device equipped with the above-mentioned line head protection means, the pixel to be recorded is a binary pixel that has only two states: presence and absence, so the width of the print pulse applied to the heat generating part is the maximum print pulse width. Exceeding this can be detected as abnormal operation.

Based on the detection signal, it is possible to protect the line head by prohibiting energization to the line head. However, it is difficult to apply this line head protection means in a recording apparatus that records binary images to a recording apparatus that records multi-tone images. In addition, in a recording device that divides a plurality of heat generating parts into two blocks, odd-numbered heat generating parts and even-numbered heat generating parts, and drives these blocks temporally with a common strobe pulse according to multi-value data. If an abnormality occurs in which a strobe pulse is generated and then disappears, for example, when an odd-numbered heating element is recorded, an even-numbered heating element will also be in the recording state, which means that the odd-numbered heating element and the even-numbered heating element are energized at the same time. If this continues, the line head will be destroyed.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a recording apparatus which can improve the above-mentioned drawbacks and can sufficiently protect a line head when performing multi-gradation image recording.

[Means to solve the problem]

In order to achieve the above object, the invention according to claim 1 records an image using a line head having a plurality of heat generating parts arranged in a line, and each of the heat generating parts records a pixel by each multi-value data. In a recording device for recording multi-gradation pixels by applying a number of pulse signals according to multi-value data using a plurality of strobe signals to a plurality of strobe signals, a counting means counts the number of strobe signals for each image recording for one line. and line head protection means for detecting abnormality in driving of the heat generating section and protecting the line head by comparing the count value of the counting means with a reference value, Claim 2. In the invention, an image is recorded using a line head having a plurality of heat generating parts arranged in a line, and each of the heat generating parts is converted into multi-value data by a plurality of strobe signals for each recording of a pixel of each multi-value data. In a recording device that records multi-tone pixels by applying a corresponding number of pulse signals, 1
A counter that reads a reference value every time an image is recorded for a line and counts down based on the strobe signal, and a line head protection means that protects the line head against drive abnormality of the heat generating section based on the count over signal of the counter. According to a third aspect of the invention, in the recording apparatus according to the first aspect, the plurality of heat generating parts are divided into a plurality of blocks, and these blocks are sequentially driven.

[For production]

In the invention of claim 1, the number of strobe signals for one line is counted by the counting means, and the line head protection means compares the count value of the counting means with a reference value, thereby detecting abnormality in the driving of the heat generating part. Line head is protected.

In the second aspect of the invention, a counter reads a reference value every time one line of image is recorded and counts down based on the strobe signal, and a count-over signal of the counter causes the line head protection means to protect the line head against drive abnormality of the heat generating section. protection.

In the third aspect of the invention, the plurality of heat generating parts are divided into a plurality of blocks, and these blocks are sequentially driven.

〔Example〕

FIG. 1 shows a portion of an embodiment of the present invention.

This embodiment is a recording device that performs multi-gradation recording using a line head consisting of a thermal head having a plurality of heating resistors, and a level frequency counter 11 represents the number of pulses applied to each pixel (for each heating resistor). The level frequency of the pulse number signal (representing the number of pulses to be applied to record one pixel),
That is, by counting the number of occurrences of each level of the pulse number signal for each level, the frequency (number of occurrences) of each level of the pulse number signal of one line is counted. A heat generation calculation section 12 consisting of an element (heat generating resistor) number calculation section calculates the number of operating elements at each gradation level based on the level frequency counted by the level frequency counter 11, and a pulse width control section 13 calculates the heat generation amount. The recording density is controlled to be constant by accumulating the number of operating elements at each gradation level calculated by the calculation unit I2 and changing the pulse application time to the thermal head based on the number of operating elements at each gradation level. .

FIG. 2 shows the structure of the level frequency counter 11. 2
Random access memory (RAM) each with a capacity of 56 bytes
The number of pulses is used alternately for each level frequency measurement for one line, and represents the number of pulses applied to each pixel (represents the number of pulses to be applied to each heating resistor in recording one stroke). A signal and a select signal for selecting odd-numbered and even-numbered elements are input to the address line. Then, the RAM 14.15 has an odd count part Odd which counts the level frequency by the pulse number signal of the odd numbered dot for one line as shown in FIG. 3 by inputting the select signal to the most significant bit of the address line. and an even count portion Even for counting the level frequency based on the pulse number signal of even numbered dots for one line are switched and used each time the pulse number signal of each dot is input. This is because when driving the plurality of elements in the thermal head, the plurality of elements are divided into two blocks, odd-numbered blocks and even-numbered blocks, and driven at different timings. Further, in the RAMIs 4 and 15, when the pulse number signal of each dot is input to the address line, 1 is added to the content of the address corresponding to the level of the pulse number signal by the adding means 16 and saved at that address. Needless to say, the contents of RAM 14 and 15 are set to zero in advance.

The RAMs 14 and 15 have an address structure as shown in FIG. 3, in which the level of the pulse number signal corresponds to the address, and the value obtained by counting the frequency of each gradation level becomes the content of each address. These two RAMs 14 and 15 toggle each time a pulse number signal for one line is input, and when one is counting the level frequency for one line, the other one transfers the count data to the next element number calculation section. Transfer to 12. This transfer is performed from multi-gradation O level to 254 level for odd-numbered elements, and then from multi-gradation O level to 254 level for even-numbered elements.
Perform up to level 4.

FIG. 4 shows the configuration of the element number calculation section 12.

The gate 17 is opened by the 1st level enable signal, and 0 level data A is output from the level frequency counter 11. is 12, which is the maximum number of elements to which simultaneous pulses can be applied in the subtracter 18.
80 and the result, which means the number of applied dots, is transferred to the next pulse width controller 13. Here, data A is at level 0 from 1280, which is the maximum number of elements to which simultaneous pulses can be applied. By subtracting , the number of odd-numbered elements that are simultaneously driven in the th level is determined. The latch circuit 19 operates when the first rubel enable signal is applied via the inverter 20 and the second rubel enable signal is turned off. Subtraction Fg! The subtraction result of 18 is latched by the latch circuit 19, and the gate 17 is closed by turning off the 1st rubel enable signal. - Lebel's data 80 from the level frequency counter 11 is subtracted from the value of the latch circuit 19 in the subtracter 18, and transferred to the next pulse width controller 13 as the number of odd-numbered elements driven simultaneously at the second level. and is latched by the latch circuit 19. Below, the second
The number of odd-numbered elements driven simultaneously at the level to the 254th level is determined and transferred to the pulse width control unit 13, and the number of odd-numbered elements driven simultaneously at each gradation level is similarly calculated for the even-numbered elements. The number is determined and transferred to the pulse width control section 13.

FIG. 5 shows the configuration of the pulse width control section 13.

The data transferred from the element number calculation section 12 is stored in the pulse width RAM 22. Pulse width RAM2
2 consists of two RAMs 23 and 24, and performs a 1-group operation each time one line of data is input. This RAM
23 and 24, when one side stores the data transferred from the element number calculation unit 12, the other side stores the stored data in synchronization with the strobe signal, the data of the 1st level for the odd-numbered elements, and the 1st level of data for the even-numbered elements. data, second level data for odd numbered elements, second level data for even numbered elements, ..., 255th level data for odd numbered elements, 255th level data for even numbered elements The data is output to the read-only memory (ROM) 25 for pulse width conversion in the order of data. The pulse width conversion ROM 25 converts the input data into a timer value that eliminates recording density fluctuations due to the number of simultaneously driven elements. The timer 26 is set to a timer value from the pulse width conversion ROM 25 when odd-numbered elements and even-numbered elements are driven at each gradation level, and is triggered by a timer start signal. The strobe pulse generator 27 generates strobe pulses from when the timer start signal is input until the timer 26 times up, and divides the strobe pulses into strobe pulses for odd-numbered elements and strobe pulses for even-numbered elements and applies them to the thermal head. do.

FIG. 7 shows the circuit configuration of the thermal head.

The thermal head has 2560 elements R1 to R25
60 are arranged in a row, and these elements R1 to R2
560, image recording is performed line by line. The shift register consisting of D flip-flops FFI to FF2560 transfers image data one line at a time and captures it by lock, and the latch circuit RTI to RT2560 sequentially latches the image data in shift registers FFI to FF2560 one line at a time by a latch signal. do.

The gates 61 to G2560 are connected to latch circuits RTI to G2560 by strobe pulses from the strobe pulse generator 27.
The image data from RT2560 is passed one line at a time in the order of odd-numbered dot data and even-numbered dot data, and transistors Tll to T12560°T are passed through.
21-T 22560 is element R1-R2560
is divided into two blocks, odd-numbered blocks and even-numbered blocks, and these blocks are sequentially energized by image data from the gates Gl-G 2560 to perform image recording. In this case, as shown in FIG. 6, after the image data of the second level is transferred to the shift register FF1-FF2560 and latched by the latch circuits RT1-RT2560, the image data of the odd-numbered gate 01. G3...The strobe pulse from the strobe pulse generator 1127 for G 2559 becomes active and the odd-numbered gates Gl, G3
...G2559 opens, and due to the timer end signal from timer 2G (due to timer 26 time-up)
When the strobe pulse is turned off, the odd-numbered gate Gl,
G3...G 2559 closes. Next, the strobe pulse from the strobe pulse generator 27 to the even-numbered gates G2°G4...G2560 becomes active, and the even-numbered gates G2. G4...
. . G2560 opens, the strobe pulse is turned off by the timer end signal from the timer 26, and the even numbered game F-G2. G4...Cx 2560 closes.

Next, the second level image data is transferred to the shift register FFI~
Transferred to FF2560 and latch circuit RTI~RT25
After being latched at 60, the odd numbered gates Gl, G
3...G2559, the strobe pulse from the strobe pulse generator 27 becomes active and the odd-numbered gate Gl, G3...G255
9 opens, the strobe pulse is turned off by the timer end signal from the timer 26, and the odd-numbered gates 01. G3
...G 2559 closes. Next, even-numbered gate G2. G4...G The strobe pulse from the strobe pulse generator 27 for G2560 becomes active and the even numbered gate G2.04...
G2560 opens, the strobe pulse is turned off by the timer end signal from timer 26, and the even numbered gate G
2.04...G 2560 closes. Thereafter, similar operations are repeated from the third level image data to the 255th level image data.

FIG. 8 shows the thermal head protector of this embodiment.

510 strobe pulses are generated from the strobe pulse generator 27 for each line of image recording, and are sent to the thermal head 29 via the OR circuit 28 and simultaneously inputted to the counter 30 as a clock. The counter 30 reads an initial value (reference value) of the number of pulses each time one line of image recording is performed using a line synchronization signal, and counts down using a strobe pulse from the strobe pulse generator 27. The initial value of the above pulse number is 50, which is close to the above 51O.
8, and if it is normal, the count value of the counter 30 will reach 508 near the end of one line of image recording as shown in FIG. Output as a clock. The flip-flop 31 is set to 1 by the clear signal.
It is cleared each time recording of a line starts, and is set by the count-over signal CO from the counter 30, so that the inverted output signal becomes low level. The flip-flop 32 receives the line synchronization signal as a clock and latches the inverted output signal of the flip-flop 31, so that the non-inverted output signal always remains at a low level.

Therefore, the strobe pulse from the strobe pulse generator 27 passes through the OR circuit 28 and is sent to the thermal head 29.

When an abnormality occurs and the strobe pulse generator 27 stops outputting strobe pulses as shown in FIG. is no longer set and its inverted output signal no longer goes low. Therefore, the non-inverted output signal of the flip-flop 32 becomes high level and is sent to the OR circuit 28 as an error signal, and the strobe pulse from the strobe pulse generator 27 is blocked by the OR circuit 28, that is, the output of the OR circuit 28. becomes a high level, and the heat generating portion of the thermal head 29 is protected from being overly energized.

FIG. 11 shows another embodiment of the invention.

This embodiment is an example in which the present invention is applied to a recording device that uses a thermal head having a plurality of heating resistors to record multi-gradation images depending on the number of pulses applied to the element. Instead of controlling the width of the applied pulses, the number of pulses applied to the element is controlled. The level frequency counter 11 and the calorific value calculation unit 12 are the same as those in the above embodiment,
The number of operating elements at each gradation level calculated by the calorific value calculation unit 12 is accumulated in the pulse number conversion unit 34.

Further, a pulse number signal representing the number of pulses applied to each dot (representing the number of pulses to be applied to each heating resistor in recording one dot) is stored in a one-line buffer 33, and a pulse number converter 34 converts each accumulated gradation level. Based on the number of operating elements at each level, the pulse number signal stored in the one-line buffer 33 is converted into data that eliminates recording density fluctuations due to the number of operating elements at each gradation level. The thermal head driving section drives the thermal head using the pulse number signal from the pulse number converting section 34 to perform multi-gradation image recording.

FIG. 12 shows the configuration of the pulse number conversion section 34.

The data on the number of operating elements at each gradation level transferred from the calorific value calculation unit 12 is stored in the pulse number conversion ROM 35.
The data is converted into data in which the recording density is constant regardless of the number of operating elements at each gradation level of the thermal head (data in which the recording density is equal to the recording density by one pulse when driving one element). Ru. The gate 36 is opened by the 1st rubel enable signal, and the 0 level data for the odd-numbered elements from the pulse number conversion ROM 35 is added to O in the adder 37.
The upper 8 bits are written to the next pulse number conversion RAM 38. Here, in the output data of the adder 35, the upper 8 bits are the integer part and the lower 4 bits are the part below the decimal point. The latch circuit 39 operates when the first rubel enable signal is applied via the inverter 40 and the second rubel enable signal is turned off. The subtraction result of the adder 37 is latched by the latch circuit 39, and the gate 36 is closed when the first rubel enable signal is turned off. The data of the 1st level for the odd-numbered element from the pulse number conversion ROM 35 is added to the value of the latch circuit 39 in the adder 37, and the upper 8 bits thereof are written to the next pulse number conversion RAM 38 and added to the adder 37. 37 output data is latched by the latch circuit 39. below,
The second to 254th level data for odd-numbered elements from the pulse number conversion ROM 35 are similarly processed and written to the pulse number conversion RAM 38,
The data of each gradation level for even-numbered elements is similarly processed and written to the pulse number conversion RAM 38.

RAMa8 for pulse number conversion is 256bitX each.
Consists of RAM 41.42 with a capacity of 2,
This RAM 41.42 toggles on a line-by-line basis, and when data from the adder 37 is written to one side, data from the 1-line buffer 33 becomes an address input to the other side, and the content of that address becomes the actual pulse. The signal is transferred to the thermal head drive unit as a numerical signal.

FIG. 13 shows the thermal head drive section of this embodiment,
FIG. 14 shows the timing chart.

This thermal head drive section is composed of a line buffer 43 and a data conversion section 44, and the line buffer 43 has four
It has line memories 43A and 43B of KB each, and these are alternately switched by a line synchronization signal. The counters 45A and 4513 specify addresses of the line memories 43A and 43B with an initial value of 2559,
Counter 45A is a write counter and counter 45B
is the read counter. This counter 45A.

45B counts down each time data is written or read, and after 0, no data is written. Counters 45A and 45B are Read/Write
The output is switched by the mode signal, and the output values are output alternately. The line memories 43A and 43B alternately store the data from the pulse number converter 34 as 2559.2558.・
...O is written to the lower memory address one by one, and the data read is 2559, 2495, etc.
..., 63,2558.2494. ..., 62.・
...O, starting from every 64th memory address. This is because each driver (the part that drives the elements) of the thermal head has a 64-bit configuration.

In the data conversion section 44, (1) line memory 43A;

Data from 43B is at memory address 2559, 249
5. . . . 63 data in order of first stage latch circuit Ll,
L2. ...Latched in L40, and all of the 40 data are latched in the first stage latch circuits L1 to L40, the contents of 1 to L4Q are transferred to the second stage latch circuits tot to L140. are latched at the same time. Next, the data in the second stage latch circuit LIOI to L140 is transferred to the next stage PNM (Pulse Number Module
) is compared with O of the comparison data from the comparison data generation counter 46 in the circuits 201 to 240, and if it is greater than 0, 'l
', if it is less than 0, it becomes '0' and the next stage head memory M
Written to l-M5. ■Second stage latch circuit 101
The data in ~L140 is compared with 1 of the comparison data from the comparison data generation counter 46 in the PNM circuits 201 to 240, and if it is greater than 1, it becomes '1', and if it is less than 1, it becomes 'O' and is written to the head memory old ~M5. It will be done. ■Similarly, the second stage latch circuit and the data in 101 to L140 are P
Comparison data generation counter 46 in NM circuits 201 to 240
The comparison data from 128 to 254 are compared with each other, and the results are written to head memories old to M5. As shown in FIG. 15, the comparison data generation counter 46
The comparison data from the PNM circuit 201 has its bit arrangement changed so that the least significant bit and the most significant bit are reversed.
1, 12 as shown in FIG.
8,129,64,65°192.193. ..., 2
There are discontinuous threshold levels such as 55. ■
The upper 6 bits of the data in the head memories M1 to M40 indicate the dot number, and the lower 8 bits indicate the level number, and the data is sent from the PNM circuits 201 to 240 to the head memories 1 to M5.
Data is written to dot number '0' and level numbers 'o' to '255'. ■
During the work in steps (1) to (2) above, data from the line memories 41A and 41B was transferred to memory addresses 255g, 2494. ...
, 62 data are sequentially transferred to the first stage latch circuits Ll, L2 .・
...Latched in L40 and waiting. ■The contents of the first stage latch circuit Ll-L40 are the second stage latch circuit LIOI
.about.LI is latched to 40, and the dot number is set to ``1'' in the step ①, and the operations ① to ① are performed, and similar operations are performed up to the dot number ``63''. ■Head memory M1
~ From M5 to the thermal head in synchronization with the head latch signal, level number 'O', dot number 'O' ~ '63
' data is sent, then level number '1' and dot numbers '0' to '63' are sent, and so on until level number '255' and dot numbers O1' to '63' are sent. Sent. ■The head memory Ml-M5 also has a line memo of 6 in the same way as the monthly IA and 41B.
It is divided into two areas of 4×256 bytes, and is switched for each line synchronization signal.

FIG. 17 shows the configuration of the pulse width timer of this embodiment.

The line synchronization pulse generator 51 generates a line synchronization signal and sends it to the thermal head etc., and the level synchronization pulse generator 5
2 generates a signal whose period is the time t for applying pulses to the elements of each block in the thermal head.

The head strobe generator 53 generates application enable signals for each application level (each gradation level) 1 to 255. Level synchronization pulse generator 52. Head strobe generator 5
3 are each reset by a line synchronization signal from the line synchronization pulse generator 51, and operate from the rising edge of the line synchronization signal. The signal from the level synchronization pulse generator 52 is divided by two by the divide-by-two circuit 54, and the signal is divided by two by the divide-by-two circuit 54. The strobe signal from the head strobe generator 53 is sent to the inverter 56, and the strobe signal from the head strobe generator 53 is sent to the buffer 5 at the OR gate 57.58.
5. It is gated by ORing with the output signal of the inverter 56 and is sent to the thermal head as a strobe signal for the first block and a strobe signal for the second block. Further, the output signals of the frequency divider circuit 54 and the level synchronization pulse generator 52 are inputted to a NAND circuit 59 and NANDed, and the output signal of the NAND circuit 59 is sent to the thermal head as a latch signal. The circuit 11 of the thermal head is the same as that of the above embodiment, and the thermal head protection part is the same as that of the above embodiment.
The strobe signal for the first block and the strobe signal for the second block from 7 and 58 are respectively sent to the thermal head via the OR circuit 28 and simultaneously input to the counter 30.

〔Effect of the invention〕

As described above, according to the invention of claim 1, an image is recorded using a line head having a plurality of heat generating parts arranged in a line, and each of the heat generating parts is recorded with each pixel by each multi-value data. In a recording device for recording multi-gradation pixels by applying a number of pulse signals corresponding to multi-value data using a plurality of strobe signals, a counting means for counting the number of strobe signals for each line of image recording; , line head protection means for detecting a driving abnormality of the heat generating section and protecting the line head by comparing the count value of the counting means with a reference value, thereby performing multi-gradation image recording. The line head can be sufficiently protected in this case.

Further, according to the invention of claim 2, an image is recorded using a line head having a plurality of heat generating parts arranged in a line,
In a recording device that records multi-tone pixels by applying a number of pulse signals according to the multi-value data using a plurality of strobe signals to each of the heat generating parts for each pixel recording based on multi-value data, A counter that reads a reference value every time an image is recorded and counts down based on the strobe signal, and a line head protection means that protects the line head against drive abnormality of the heat generating section based on the count over signal of the counter. The line head can be sufficiently protected when performing multi-gradation image recording.

Furthermore, according to the invention of claim 3, in the recording apparatus of claim 1, the plurality of heat generating parts are divided into a plurality of blocks and these blocks are sequentially driven. Even if such an abnormality occurs, the line head can be sufficiently protected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of the present invention, FIG. 2 is a block diagram showing a level frequency counter of the same embodiment, and FIG. 3 is a block diagram showing a frequency RAM of the same level frequency counter. FIG. 4 is a block diagram showing an element number calculation section of the same embodiment, and FIG. 5 is a block diagram showing a pulse width conversion section of the same embodiment. FIG. 6 is a timing chart of the same embodiment, FIG. 7 is a block diagram showing the four circuit components of the thermal head in the same embodiment, FIG. 8 is a block diagram showing the line head protection means of the same embodiment, and FIG. 9 1 is a timing chart showing the normal operation of the line head protection means, and FIG. 1O is a timing chart 1 showing the abnormal operation of the line head protection means.
~, Fig. 11 is a block diagram showing a part of another embodiment of the present invention, Fig. 12 is a block diagram showing a pulse number converter of the same embodiment, and Fig. 13 is a thermal head drive unit of the same embodiment. FIG. 14 is a timing chart of the thermal head drive unit, FIG. 15 is a block diagram showing the relationship between the comparison data generation counter and the PNM circuit in the same embodiment, and FIG. 16 is the comparison data generation counter of the same embodiment. FIG. 17 is a block diagram showing the pulse width timer of the same embodiment. 28...OR circuit, 30...Counter, 31, 32
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Claims (1)

[Claims] 1. An image is recorded using a line head having a plurality of heat generating parts arranged in a line, and a plurality of strobe signals are sent to each of the heat generating parts for each pixel recorded by each multi-value data. A recording device for recording multi-gradation pixels by applying a number of pulse signals corresponding to multi-value data, comprising: a counting means for counting the number of strobe signals for each recording of one line of image; 1. A recording apparatus comprising: line head protection means for detecting a driving abnormality of the heat generating section and protecting the line head by comparing a count value of 1 with a reference value. 2. An image is recorded using a line head having a plurality of heat-generating parts arranged in a line, and each of the heat-generating parts is responsive to the multi-value data using a plurality of strobe signals for each pixel recorded by each multi-value data. In a recording device that records pixels with multiple gradations by applying a number of pulse signals, there is a counter that reads a reference value every time an image is recorded for one line and counts down using the strobe signal, and a counter that counts down using the strobe signal. A recording apparatus comprising: a line head protection means for protecting the line head against driving abnormalities of the heat generating section. 3. The recording apparatus according to claim 1, wherein the plurality of heat generating parts are divided into a plurality of blocks and these blocks are sequentially driven.